○Product structure：Silicon monolithic integrated circuit ○ This product has no designed protection against radioactive rays
1/24
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TSZ22111･14･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
2.7V to 5.5V, 1.2A 1ch
Synchronous Buck Converter with
Integrated FET
BD9123MUV
General Description
BD9123MUV is ROHM’s high efficiency step-down
switching regulator designed to produce voltage as low
as 0.85V to 1.2V from a supply voltage of 5V/3.3V. It
offers high efficiency by using pulse skip control
technology and synchronous switches, and provides
fast transient response to sudden load changes by
implementing current mode control.
Features
■ Fast Transient Response with Current Mode PWM
Control System.
■ High Efficiency for All Load Range with
Synchronous Rectifier (Nch/Pch FET) and SLLMTM
(Simple Light Load Mode)
■ Output Voltage Selector (3 bit)
■ PGOOD Function
■ Soft-Start Function
■ Thermal Shutdown and UVLO Functions.
■ Short-Circuit Protection Circuit with Time Delay
Function.
■ Shutdown Function
Applications
Power Supply for LSI including DSP, Microcomputer and
ASIC
Key Specifications
Input Voltage Range: 2.7V to 5.5V
Output Voltage Range: 0.85V to 1.2V
Output Current: 1.2A (Max)
Switching Frequency: 1MHz(Typ)
Pch FET ON-Resistance: 0.35Ω(Typ)
Nch FET ON-Resistance: 0.25Ω(Typ)
Standby Current: 0μA (Typ)
Operating Temperature Range: -40°C to +95°C
Package W(Typ) x D(Typ) x H(Max)
Typical Application Circuit
Figure 1. Typical Application Circuit
VQFN016V3030
3.00mm x 3.00mm x 1.00mm
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VIN
VOUT
CIN
RITH
CITH
L
CO
VOUT
PGOOD
VCC
RPG
VID<2:0)
VID<2:0>
Datashee
t
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TSZ02201-0J3J0AJ00120-1-2
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Pin Configuration
Pin Description
Pin No.
Pin name
Function
1
SW
Pch/Nch FET drain output pin
2
3
4
PGND
Nch FET source pin
5
6
GND
Ground
7
PGOOD
Power good pin
8
ITH
Gm Amp output pin/connected phase
compensation capacitor
9
VOUT
Output voltage pin
10
VID<2>
Output voltage control pin<2>
11
VID<1>
Output voltage control pin<1>
12
VID<0>
Output voltage control pin<0>
13
EN
Enable pin(High Active）
14
VCC
VCC power supply input pin
15
PVCC
Pch FET source pin
16
Block Diagram
Figure 2. Pin Configuration
VCC
PVCC
PGND
SW
GND
Output
Gm Amp
4.7µH
VCC
R
S
Q
OSC
UVLO
TSD
22µF
VCC
CLK
SLOPE
Current
Comp
10µF
14
2
4
6
Soft
Start
Current
Sense/
Protect
+
Driver
Logic
VREF
ITH
RITH
CITH
8
SELECTOR
12
11
10
9
5
1
3
15
16
VID<0>
VID<1>
VID<2>
VOUT
PGOOD
7
PGOOD
VCC
EN
13
100Ω
0.1µF
Input
Figure 3. Block Diagram
(TOP VIEW)
(TOP VIEW)
12
13
8
4
11
10
9
6
5
3
2
1
15
16
SW
SW
SW
PGND
PGND
GND
VID<0>
>
VID<1>
VID<2>
VOUT
VCC
PVCC
PVCC
7
14
PGOOD
ITH
EN
3/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
VCC Voltage
VCC
-0.3 to +7 (Note 1)
V
PVCC Voltage
PVCC
-0.3 to +7 (Note 1)
V
EN,SW,ITH Voltage
VEN, VSW, VITH
-0.3 to +7
V
Logic Input Voltage
VVID<2:0>
-0.3 to +7
V
Power Dissipation 1
Pd1
0.27 (Note 2)
W
Power Dissipation 2
Pd2
0.62 (Note 3)
W
Power Dissipation 3
Pd3
1.77 (Note 4)
W
Power Dissipation 4
Pd4
2.66 (Note 5)
W
Operating Temperature Range
Topr
-40 to +95
°C
Storage Temperature Range
Tstg
-55 to +150
°C
Maximum Junction Temperature
Tjmax
+150
°C
(Note 1) Pd should not be exceeded.
(Note 2) IC only
(Note 3) Mounted on a 1-layer 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 6.28mm2
(Note 4) Mounted on a 4-layer 74.2mmx74.2mmx1.6mm glass-epoxy board, 1st and 4th copper foil area : 6.28mm2 , 2nd and 3rd copper foil area : 5505mm2
(Note 5) Mounted on a 4-layer 74.2mmx74.2mmx1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta=-40°C to +95°C)
Parameter
Symbol
Rating
Unit
Min
Typ
Max
Power Supply Voltage
VCC
2.7
3.3
5.5
V
PVCC
2.7
3.3
5.5
V
EN Voltage
VEN
0
-
VCC
V
Logic Input Voltage
VVID<2:0>
0
-
5.5
V
Output Voltage Setting Range
VOUT
0.85
-
1.2
V
SW Average Output Current
ISW
-
-
1.2(Note 6)
A
(Note 6) Pd should not be exceeded.
4/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Electrical Characteristics
(Ta=25°C VCC=PVCC=5V, VEN=VCC, VVID<2>= VVID <1>= VVID <0>= 0V, unless otherwise specified.)
Parameter
Symbol
Limit
Unit
Conditions
Min
Typ
Max
Standby Current
ISTB
-
0
10
µA
EN=GND
Active Current
ICC
-
300
500
µA
EN Low Voltage
VENL
-
GND
0.8
V
Standby mode
EN High Voltage
VENH
2.0
VCC
-
V
Active mode
EN Input Current
IEN
-
5
10
µA
VEN=5V
VID Low Voltage
VVIDL
-
GND
0.8
V
VID High Voltage
VVIDH
2.0
VCC
-
V
VID Input Current
IVID
-
5
10
µA
VVID=5V
Oscillation Frequency
fOSC
0.8
1
1.2
MHz
Pch FET ON-Resistance
RONP
-
0.35
0.60
Ω
PVCC=5V
Nch FET ON-Resistance
RONN
-
0.25
0.50
Ω
PVCC=5V
Output Voltage
VOUT
0.98
1.0
1.02
V
VVID<2:0>=(0,0,0)
ITH SInk Current
ITHSI
25
50
-
µA
VOUT =1.2V
ITH Source Current
ITHSO
25
50
-
µA
VOUT =0.8V
UVLO Threshold Voltage
VUVLO1
2.4
2.5
2.6
V
VCC=5V to 0V
UVLO Release Voltage
VUVLO2
2.425
2.55
2.7
V
VCC=0V to 5V
Power Good Threshold
VPGOOD1
70
75
80
%
VOUT to 0V
Power Good Release
VPGOOD2
85
90
95
%
0V to VOUT
Power Good Delay
tPG
2.5
5
10
ms
PGOOD ON-Resistance
RONPG
-
140
280
Ω
Soft-Start Time
tSS
0.4
0.8
1.6
ms
Timer Latch Time
tLATCH
1
2
4
ms
Output Short Circuit Threshold Voltage
VSCP
-
VOUTx0.5
VOUTx0.7
V
VOUT to 0V
5/24
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TSZ02201-0J3J0AJ00120-1-2
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Typical Performance Curves
Figure 4. Output Voltage vs Input Voltage
Output Voltage: VOUT[V]
Input Voltage: VCC[V]
EN Voltage:VEN[V]
Figure 5. Output Voltage vs EN Voltage
Output Voltage: VOUT[V]
EN Voltage:VEN[V]
VCC=5V
IO=0A
Ta=25°C
Figure 7. Output Voltage vs Input Voltage
Input Voltage: VCC[V]
Output Voltage: VOUT[V]
VCC=5V
IO=0A
[ VOUT = 1.0V]
Figure 6. Output Voltage vs EN Volatge
Output Voltage: VOUT[V]
EN Voltage: VEN[V]
VCC=5V
Ta=25°C
[ VOUT = 1.0V]
IO=1.2A
Ta=25°C
[VOUT=1.0V]
[VOUT=1.0V]
6/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Typical Performance Curves - continued
Figure 10. Frequency vs Temperature
Temperature:Ta[°C]
Frequency: fOSC [MHz]
VCC=5V
Figure 11. On-Resistance vs Temperature
Temperature:Ta[°C]
ON-Resistance : RON [Ω]
VCC=5.0V
[ VOUT = 1.0]
Figure 9. Frequency vs Input Voltage
Frequency: fOSC [MHz]
Input Voltage:VCC[V]
Ta=25°C
Figure 8. Efficiency vs Output
Current
Efficiency:η [%]
Output Current:IO [A]
VCC=5.0V
Ta=25°C
[VOUT=1.0V]
7/24
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Datasheet
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Typical Performance Curves - continued
Figure 12. EN Voltage vs Temperature
Temperature:Ta[°C]
EN Voltage: VEN[V]
VCC=5V
Figure 13. ON-Resistance vs Temperature
Temperature:Ta[°C]
ON-Resistamce:RON[Ω]
VCC=5V
8/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Typical Waveforms
Figure 15. SW Waveform
(IO=0mA)
SW
VOUT
VCC=5V
[ SLLM control VOUT=1.0V]
IO=0A Ta=25°C
Figure 14. Soft-Start Waveform
SW
VOUT
VCC=5V
[VOUT=1.0V]
IO=1.2A
Ta=25°
C
Figure 17. Transient Response
(IO=125mA to 850mA, 2µA)
VOUT
IOUT
Figure 16. SW Waveform
(IO=1.2A)
SW
VOUT
VCC=5V
IO=1.2A
Ta=25°C
Ta=25°C
9/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Typical Waveforms – continued
Figure 20. Bit Chance Response
VID
VOUT
Figure 21. PGOOD Delay
VPGOOD
VOUT
VCC=5V
VO=1V
Ta=25°C
Figure 19. Bit Chance Response
a 25°C
VID
VOUT
Figure 18. Transient Response
(IO=850mA～125mA, 2µA)
VOUT
IOUT
10/24
BD9123MUV
Datasheet
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Application Information
1. Operation
BD9123MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by
employing current mode PWM control system. Its switching operation utilizes PWM (Pulse Width Modulation) mode for
heavier load, while SLLMTM (Simple Light Load Mode) operation for lighter load to improve efficiency.
(1) Synchronous Rectifier
Integrated synchronous rectification using two MOSFETS reduces power dissipation and increases efficiency when
compared to converters using external diodes. Internal shoot-through current limiting circuit further reduces power
dissipation.
(2) Current Mode PWM Control
The PWM control signal of this IC depends on two feedback loops, the voltage feedback and the inductor current
feedback.
(a) PWM (Pulse Width Modulation) Control
The clock signal coming from OSC has a frequency of 1MHz. When OSC sets the RS latch, the P-Channel
MOSFET is turned ON and the N-Channel MOSFET is turned OFF, causing an inductor current IL to increase.
The opposite happens when the current comparator (Current Comp) resets the RS latch i.e. the P-Channel
MOSFET is turned OFF and the N-Channel MOSFET is turned ON. Current Comp’s output is a comparison of two
signals, the current feedback control signal “SENSE” which is a voltage proportional to the current IL and the
voltage feedback control signal, FB.
(b) SLLMTM (Simple Light Load Mode) Control
When the control mode is shifted by PWM from heavier load to the one for lighter load or vice versa, the switching
pulse is designed to turn OFF with the device held operating in normal PWM control loop. This allows linear
operation without voltage drop or deterioration in transient response during sudden load changes. .
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from
Current Comp, it is designed such that the RESET signal is kept constant when shifted to the light load mode
where the switching is tuned OFF and the switching pulses disappear. Activating the switching discontinuously
reduces the switching dissipation and improves the efficiency.
Figure 22. Diagram of Current Mode PWM Control
Figure 23. PWM Switching Timing Chart
Figure 24. SLLMTM Switching Timing Chart
Current
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
IL(AVE)
VOUT(AVE)
SENSE
FB
Current
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
0A
VOUT(AVE)
SENSE
FB
IL
Not switching
IL
OSC
Level
Shift
Driver
Logic
R
Q
S
IL
SW
RITH
Current
Comp
Gm Amp
SET
RESET
FB
Load
SENSE
VOUT
VOUT
11/24
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TSZ02201-0J3J0AJ00120-1-2
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2. Description of Functions
(1) Soft-Start Function
When EN terminal is shifted to “High” activates a soft-starter to gradually establish the output voltage with the current
being limited during startup. It prevents an overshoot of output voltage and an inrush current.
The slope of input signal is different and the soft start time is different depending on the value offset output voltage.
When set to 1V ,tSS=1msec(Typ)
Figure 25. Soft-Start Action
(2) Shutdown Function
When EN terminal is shifted to “Low”, the device turns to Standby Mode, and all the functional blocks including
reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µA(Typ).
(3) UVLO Function
It detects whether the input voltage supplied is sufficient to secure the output voltage of this IC. A hysteresis of 50mV
(Typ) is designed to prevent output chattering.
Figure 26. Soft-Start, Shutdown, UVLO Timing Chart
(4) PGOOD Function
When the output voltage falls below 75% (Typ) of a set value, the output of an Open-Drain PGOOD pin is turned OFF. A
hysteresis width of 15% (Typ) is designed to prevent output chattering.
Figure 27. PGOOD Timing Chart
UVLO
EN
UVLO
UVLO
Hysteresis 50mV
tss
tss
tss
Soft start
Standby Mode
Operating Mode
Standby
Mode
Operating Mode
Standby
Mode
Operating Mode
Standby Mode
EN
Vcc
VOUT
VCC,EN
tSS
tSS’
1.2V
0.85V
[ms]
VOUT
90%
The hysteresis width
VOUT
75%
PGOOD
tGP
12/24
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TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
3. About Setting the Output Voltage
Output voltage shifts step by step as often as bit setting to control the overshoot/undershoot that occurs when changing the
of output voltage value. 8 steps (max) delay will occur from the bit switching until output voltage reach to setting value.
(a) Switching 3 bit synchronously
(b) Switching 3 bit with the time lag
(c) Switching 3 bit with the time lag
It is possible to set output voltage, shown in diagram 1 below, by setting VID<0> to <2> 0 or 1.
VID<2:0> terminal is set to VID<2:0>=(0,0,0) originally by the pull down resistor while in high impedance inside IC.
By pulling up/ pulling down about 10kΩ, the original value can be changed optionally.
Table of output voltage setting
VID<2>
VID<1>
VID<0>
VOUT
0
0
0
1.0V
0
0
1
0.85V
0
1
0
0.9V
0
1
1
0.95V
1
0
0
1.05V
1
0
1
1.1V
1
1
0
1.15V
1
1
1
1.2V
(Note) After 10µs(max) from the bit change, VOUT change starts.
Requiring time for one step (50 mV shift) of VOUT is 5µs(max).
From the bit switching until output voltage reach to setting value, tVID(max)=0.06ms delay will occur.
VOUT
VID<2:0>
(0,0,1)
(1,1,1)
1.2V
0.85V
tVID (max)=0.06ms
Figure 28. Timing Chart of Setting the Output voltage
About 10µs from bit switching
VID<2>
VOUT
Count STOP
VID<1>
VID<0>
5µs(max)
〈1〉
V2D〈2〉
VOUT
〈0〉
Count STOP
About 10µs from bit switching
VOUT
Count STOP
About 10µs from switching the last bit
VID<2>
VID<1>
VID<0>
13/24
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TSZ02201-0J3J0AJ00120-1-2
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(1) Short-Current protection circuit with time delay function
It turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously
for the fixed time (tLATCH) or more. The output may be recovered from OFF state by restarting EN or by re-unlocking
UVLO.
Figure 29. Short-current protection circuit with time delay timing chart
4. Information on Advantages
Advantage 1: Offers fast transient response with current mode control system.
Figure 30. Comparison of Transient Response
Advantage 2: Offers High Efficiency for all Load Range.
(a) For lighter load:
Utilizes the current mode control called SLLMTM for lighter load, which reduces various dissipations such as switching
dissipation (PSW), gate charge/discharge dissipation (PGATE), ESR dissipation of output capacitor (PESR) and
ON-Resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves Efficiency Improvement for Lighter Load.
(b) For heavier load:
Utilizes the synchronous rectifying mode and the low ON-Resistance MOS FETs incorporated as power transistor.
ON-Resistance of Pch side MOS FET : 0.35mΩ(Typ)
ON-Resistance of Nch side MOS FET : 0.25mΩ(Typ)
Achieves Efficiency Improvement for Heavier Load.
Offers high efficiency for all load range with the improvements mentioned above.
Conventional product (Load response IO=0.1A to 0.6A)
BD9123MUV (Load response IO=0.6A to 0.1A)
0.001
0.01
0.1
1
0
50
100
①
②
PWM
SLLM
①improvement by SLLM system
②improvement by synchronous rectifier
Efficiency ɳ [%]
Figure 31. Efficiency
Output current IOUT[A]
Output voltage OFF Latch
t2=tLATCH
VCC
VOUT
Output Short circuit
Threshold Voltage
IL
Output voltage
OFF
Operated mode
Operated mode
UVLO
Timer Latch
UVLO
Output voltage
OFF
IL Limit
t1<tLATCH
VOUT
27mV
VOUT
37mV
IOUT
IOUT
14/24
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TSZ22111･15･001
TSZ02201-0J3J0AJ00120-1-2
02.Oct.2014 Rev.002
Advantage 3:
(a) Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 10µF ceramic capacitor
・Inductor L required for the operating frequency of 1 MHz: 4.7µH inductor
Reduces a Mounting Area Requirement.
Figure 32. Example of Application
5. Switching Regulator Efficiency
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors Pdα as follows:
Dissipation factors:
(1) ON-Resistance Dissipation of Inductor and FET: Pd(I2R)
Where:
RCOIL is the DC resistance of inductor.
RON is the ON-Resistance of FET.
IOUT is the output current.
(2) Gate Charge/Discharge Dissipation: Pd(Gate)
Where:
Cgs is the gate capacitance of FET.
f is the switching frequency.
V is the gate driving voltage of FET.
(3) Switching Dissipation: Pd(SW)
Where:
CRSS is the reverse transfer capacitance of FET.
IDRIVE is the peak current of gate.
(4) ESR Dissipation of Capacitor: Pd(ESR)
Where:
IRMS is the ripple current of capacitor.
ESR is the equivalent series resistance.
(5) Operating Current Dissipation of IC: Pd(IC)
Where:
ICC is the circuit current.
DC/DC
Convertor
RITH
L
CO
VOUT
CITH
VCC
CIN
VCC
RPGOOD
15mm
20mm
CITH
Co
RITH
CIN
L
RPGOOD
Cf
Rf
)()( 2
2ONCOILOUT RRIRIPd
2
)( VfCGatePd gs
DRIVE
OUTRSSIN
I
fICV
SWPd
2
)(
ESRIESRPd RMS 2
)(
CCIN IVICPd )(
%100100100
PdP
P
P
P
LV
IV
OUT
OUT
IN
OUT
ININ
OUTOUT
15/24
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TSZ02201-0J3J0AJ00120-1-2
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6. Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage,
higher output voltage, heavier load, and/or higher temperature, the allowable dissipation and/or heat generation must be
carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON-Resistance of FET are considered. The
reason is that the conduction losses are considered to play the leading role among other dissipation mentioned above
including gate charge/discharge dissipation and switching dissipation.
If VCC=5V, VOUT=1.2V, RONP=0.35mΩ, RONN=0.25mΩ
IOUT=1.2A, for example,
D=VOUT/VCC=1.2/5=0.24
RON=0.24x0.35+(1-0.24)x0.25
=0.084+0.19
=0.274[Ω]
P=1.22x0.274=0.394[W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON time becomes greater. With the consideration on
the dissipation as mentioned above, thermal design must be carried out with sufficient margin allowed.
ONLONHON
ONOUT RDRDR
RIP
1
2
Where:
D is the ON duty (=VOUT/VCC).
RONH is the ON-Resistance of Highside MOSFET.
RONL is the ON-Resistance of Lowside MOSFET.
IOUT is the Output current.
Figure 33. Thermal Derating Curve
(VQFN016V3030)
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=47.0°C/W
② 4 layers (1st and 4th copper foil area : 6.28m2)
(2nd and 3rd copper foil area: 5505m2)
(copper foil in each layers)
θj-a=70.62°C/W
③ 1 layer (Copper foil area : 6.28m2)
θj-a=201.6°C/W
④ IC only.
θj-a=462.9°C/W
Ambient temperature:Ta [°C]
0
25
50
75
100
125
150
0
2.0
3.0
4.0
②1.77W
①2.66W
Power dissipation: Pd [W]
1.0
③0.62W
④0.27W
105
16/24
BD9123MUV
Datasheet
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7. Selection of Components Externally Connected
(1) Selection of Inductor (L) The inductance significantly depends on output ripple current. As seen
in equation (1), the ripple current decreases as the inductor and/or
switching frequency increases.
Appropriate ripple current at output should be 30% more or less of the
maximum output current.
Note: Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which
decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may
not exceed its current rating.
If VCC=5.0V, VOUT=1.2V, f=1MHz, ΔIL=0.3x1.2A=0.36A, for example,
Note: Select the inductor with low resistance component (such as DCR and ACR) to minimize dissipation in the inductor
for better efficiency.
(2) Selection of Output Capacitor (CO) Output capacitor should be selected in consideration with the stability
region and the equivalent series resistance required to smoothen the
ripple voltage.
Output ripple voltage is determined by the equation (4):
VESRIV LOUT
・・・(4)
Where:
ΔIL is the Output ripple current, and
ESR is the Equivalent series resistance of output capacitor.
Note:Rating of the capacitor should be determined allowing sufficient
margin against output voltage. A 10µF to 100µF ceramic capacitor is
recommended.
Less ESR allows reduction in output ripple voltage.
(3) Selection of Input Capacitor (CIN) The input capacitor to be selected must have sufficiently low ESR to cope with
high ripple current to prevent high transient voltage. The ripple current IRMS is
given by the equation (5):
RMSRMS AI 51.0
5
2.152.1
2.1
A low ESR 10µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better
efficiency.
Figure 34. Output ripple current
ΔIL
VCC
IL
L
Co
VOUT
IL
Figure 35. Output Capacitor
VCC
L
CO
VOUT
ESR
Figure 36. Input Capacitor
VCC
L
Co
VOUT
CIN
A
fVL
VVV
I
CC
OUTOUTCC
L
][
3.0 AOUTMaxL II
H
fVI
VVV
L
CCL
OUTOUTCC
H
M
L
7.453.2
156.0 2.12.15
When VCC=2xVOUT,
IRMS=
< Worst case > IRMSMax
If VCC=5V, VOUT=1.2V, and IOUTMax=1.2A,
]A[
VVVV
II CC
OUTCCOUT
OUTRMS
Where:
ΔIL is the Output ripple current, and
f is the Switching frequency.
・・・(1)
・・・(2)
・・・(3)
・・・(5)
2
I
IOUT
RMS
17/24
BD9123MUV
Datasheet
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Figure 39. Typical Application
(4) Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit the inductor current, a pole (phase lag) appears in the low frequency
area due to a CR filter consists of an output capacitor and a load resistance, while a zero (phase lead) appears in the
high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero
to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
Figure 37. Open Loop Gain Characteristics
Figure 38. Error Amp Phase Compensation Characteristics
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
Zero at Power Amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
Gain
[dB]
Phase
[deg]
A
0
0
-90
A
0
0
-90
fZ(Amp)
fp(Min)
fp(Max)
fZ(ESR)
IOUTMin
IOUTMax
Gain
[dB]
Phase
[deg]
OO CR
fp
21
O
ESR
ZCESR
f
21
loadlighterwithHz
CR
fp
OOMax
Min
21
loadheavierwithHz
CR
fp
OOMin
Max
21
ITHITH
Amp
ZCR
f
21
OMaxOITHITH
Min
Amp
Z
CRCR
fpf
21
21
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
VOUT
CIN
RITH
CITH
L
CO
VOUT
PGOOD
VCC
RPG
VID<2:0)
VID<2:0>
18/24
BD9123MUV
Datasheet
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©2012 ROHM Co., Ltd. All rights reserved.
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8. Cautions on PC Board Layout
Figure 40. Layout Diagram
(1) Lay out the input ceramic capacitor CIN close to the pins PVCC and PGND, and the output capacitor Co close to pin
PGND.
(2) Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
Note: VQFN016V3030 has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of
PCB.
9. Recommended Components Lists on Above Application
Symbol
Part
Value
Manufacturer
Series
L
Coil
4.7µH
TDK
VLF5014S-4R7M1R7
CIN
Ceramic Capacitor
10µF
KYOCERA
CM316X5R106M10A
CO
Ceramic Capacitor
22µF
KYOCERA
CM316B226M06A
CITH
Ceramic Capacitor
1500pF
Murata
GRM18 Series
RITH
Resistance
9.1kΩ
ROHM
MCR03 Series
Cf
Ceramic Capacitor
0.1µF
Murata
GRM18 Series
Rf
Resistance
100Ω
ROHM
MCR03 Series
Note: The parts list presented above is an example of recommended parts. Although the parts are standard, actual circuit
characteristics should be checked carefully on your application before use. Be sure to allow sufficient margins to
accommodate variations between external devices and this IC when employing the depicted circuit with other circuit
constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC
pins, and a Schottky Barrier diode or snubber connected between the SW and PGND pins.
19/24
BD9123MUV
Datasheet
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I/O Equivalent Circuit
【BD9123MUV】
・EN pin
・SW pin
・VOUT pin
・ITH pin
・PGOOD
・VID〈2:0〉 pin
Figure 41. I/O Equivalent Circuit
EN
PVCC
SW
PVCC
PVCC
ITH
VCC
VOUT
VID〈2:0〉
PGOOD
20/24
BD9123MUV
Datasheet
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02.Oct.2014 Rev.002
Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush
current may flow instantaneously due to the internal powering sequence and delays, especially if the IC
has more than one power supply. Therefore, give special consideration to power coupling capacitance,
power wiring, width of ground wiring, and routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
21/24
BD9123MUV
Datasheet
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Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Figure 42. Example of monolithic IC structure
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14. Selection of Inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, note that use of
a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue
for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will
be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between
external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is
recommended to start up the output with EN after supply voltage is within.
N N
P+PN N
P+
P Substrate
GND
NP+N N
P+
NP
P Substrate
GND GND
Parasitic
Elements
Pin A
Pin A
Pin B Pin B
B C
EParasitic
Elements
GND
Parasitic
Elements
CB
E
Transistor (NPN)Resistor
N Region
close-by
Parasitic
Elements
22/24
BD9123MUV
Datasheet
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02.Oct.2014 Rev.002
Ordering Information
B
D
9
1
2
3
M
U
V
E 2
Part Number
Package
MUV : VQFN016V3030
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN016V3030 (TOP VIEW)
23
Part Number Marking
LOT Number
1PIN MARK
D 9 1
Notice – GE
Rev.003
© 2014 ROHM Co., Ltd. All rights reserved.
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅣ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice – GE
Rev.003
© 2014 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
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When disposing Products please dispose them properly using an authorized industry waste company.
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third parties with respect to the information contained in this document.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
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3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
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4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
DatasheetDatasheet
Notice – WE Rev.001
© 2014 ROHM Co., Ltd. All rights reserved.
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
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3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred by you or third parties resulting from inaccur acy or errors of or
concerning such information.
