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Device Features _äìÉ`çêÉ»QJolj=`pm=bao
Single Chip Bluetooth®
v2.0 + EDR System
Product Data Sheet for
BC41B143A
September 2005
! Fully Qualified Bluetooth v2.0 + EDR System
! Enhanced Data Rate (EDR) compliant with
v2.0 of specification for both 2Mbits/s and
3Mbits/s modulation modes
! Full-speed Bluetooth Operation with Full
Piconet Support
! Scatternet Support
! 1.8V core, 1.7 to 3.6V I/O Split Rails
! Ultra Low Power Consumption
! Excellent Compatibility with Cellular
Telephones
! Minimum External Components Required
! Integrated 1.8V Linear Regulator
! USB and UART Port to 3MBits/s
! Support for 802.11 Co-existence
! RoHS Compliant
General Description Applications
_äìÉ`çêÉQJolj=`pm is a single-chip radio and
baseband IC for Bluetooth 2.4GHz systems
including EDR to 3Mbits/s.
With the on-chip CSR Bluetooth software stack it
provides a fully compliant Bluetooth system to
v2.0 + EDR of the specification for data and voice
communications.
! Cellular Handsets
! Personal Digital Assistants (PDAs)
! Digital cameras and other high-volume consumer
products
! Space critical applications
SPI
UART/USB
2.4
GHz
Radio I/O
XTAL
RF OUT
RAM
Baseband
DSP
MCU
ROM
PIO
PCM
RF IN
BlueCore4-ROM CSP is designed to reduce the number
of external components required. This ensures that
production costs are minimised.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and device
firmware is fully compliant with the Bluetooth v2.0 + EDR
Specification (all mandatory and optional features).
To improve the performance of both Bluetooth and
802.11b/g co-located systems a wide range of
co-existence features are available including a variety of
hardware signalling: basic activity signalling and Intel
WCS activity and channel signalling.
BlueCore4-ROM CSP System Architecture
Contents
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Contents
1 Status Information .........................................................................................................................................7
2 Key Features ..................................................................................................................................................8
3 CSP Package Information .............................................................................................................................9
3.1 BlueCore4-ROM CSP Pinout Diagram .................................................................................................... 9
3.2 BC41B143AXX-IXF Device Terminal Functions .................................................................................... 10
4 Electrical Characteristics............................................................................................................................13
4.1 Power Consumption .............................................................................................................................. 19
5 Radio Characteristics – Basic Data Rate...................................................................................................20
5.1 Temperature +20°C ............................................................................................................................... 20
5.1.1 Transmitter................................................................................................................................. 20
5.1.2 Receiver..................................................................................................................................... 22
5.2 Temperature -40°C................................................................................................................................ 24
5.2.1 Transmitter................................................................................................................................. 24
5.2.2 Receiver..................................................................................................................................... 24
5.3 Temperature -25°C................................................................................................................................ 25
5.3.1 Transmitter................................................................................................................................. 25
5.3.2 Receiver..................................................................................................................................... 25
5.4 Temperature +85°C ............................................................................................................................... 26
5.4.1 Transmitter................................................................................................................................. 26
5.4.2 Receiver..................................................................................................................................... 26
5.5 Temperature +105°C ............................................................................................................................. 27
5.5.1 Transmitter................................................................................................................................. 27
5.5.2 Receiver..................................................................................................................................... 27
6 Radio Characteristics – Enhanced Data Rate............................................................................................28
6.1 Temperature +20°C ............................................................................................................................... 28
6.1.1 Transmitter................................................................................................................................. 28
6.1.2 Receiver..................................................................................................................................... 29
6.2 Temperature -40°C................................................................................................................................ 30
6.2.1 Transmitter................................................................................................................................. 30
6.2.2 Receiver..................................................................................................................................... 31
6.3 Temperature -25°C................................................................................................................................ 32
6.3.1 Transmitter................................................................................................................................. 32
6.3.2 Receiver..................................................................................................................................... 33
6.4 Temperature +85°C ............................................................................................................................... 34
6.4.1 Transmitter................................................................................................................................. 34
6.4.2 Receiver..................................................................................................................................... 35
6.5 Temperature +105°C ............................................................................................................................. 36
6.5.1 Transmitter................................................................................................................................. 36
6.5.2 Receiver..................................................................................................................................... 37
7 Device Diagram............................................................................................................................................38
8 Description of Functional Blocks...............................................................................................................39
8.1 RF Receiver........................................................................................................................................... 39
8.1.1 Low Noise Amplifier ................................................................................................................... 39
8.1.2 Analogue to Digital Converter .................................................................................................... 39
8.2 RF Transmitter....................................................................................................................................... 39
8.2.1 IQ Modulator .............................................................................................................................. 39
8.2.2 Power Amplifier .......................................................................................................................... 39
8.2.3 Auxiliary DAC............................................................................................................................. 39
8.3 RF Synthesiser ...................................................................................................................................... 39
8.4 Power Control and Regulation............................................................................................................... 39
8.5 Clock Input and Generation ................................................................................................................... 40
8.6 Baseband and Logic.............................................................................................................................. 40
Contents
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8.6.1 Memory Management Unit......................................................................................................... 40
8.6.2 Burst Mode Controller ................................................................................................................ 40
8.6.3 Physical Layer Hardware Engine DSP....................................................................................... 40
8.6.4 RAM ........................................................................................................................................... 40
8.6.5 ROM........................................................................................................................................... 40
8.6.6 USB............................................................................................................................................ 41
8.6.7 Synchronous Serial Interface ..................................................................................................... 41
8.6.8 UART ......................................................................................................................................... 41
8.6.9 Audio PCM Interface .................................................................................................................. 41
8.7 Microcontroller ....................................................................................................................................... 41
8.7.1 Programmable I/O...................................................................................................................... 41
8.7.2 802.11 Coexistence Interface ....................................................................................................41
9 CSR Bluetooth Software Stacks.................................................................................................................42
9.1 BlueCore HCI Stack .............................................................................................................................. 42
9.1.1 Key Features of the HCI Stack – Standard Bluetooth Functionality ........................................... 42
9.1.2 Key Features of the HCI Stack - Extra Functionality .................................................................. 44
9.2 BCHS Software ..................................................................................................................................... 45
9.3 Additional Software for Other Embedded Applications .......................................................................... 45
9.4 CSR Development Systems .................................................................................................................. 45
10 Enhanced Data Rate ....................................................................................................................................46
10.1 Enhanced Data Rate Baseband ............................................................................................................ 46
10.2 Enhanced Data Rate π/4 DQPSK .......................................................................................................... 46
10.3 Enhanced Data Rate 8DPSK................................................................................................................. 47
11 Device Terminal Descriptions.....................................................................................................................49
11.1 RF_A and RF_B .................................................................................................................................... 49
11.1.1 Transmit RF Power Control for Class 1 Applications ................................................................. 50
11.1.2 Control of External RF Components .......................................................................................... 51
11.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 51
11.2.1 External Mode............................................................................................................................ 51
11.2.2 XTAL_IN Impedance in External Mode ...................................................................................... 52
11.2.3 Clock Timing Accuracy............................................................................................................... 52
11.2.4 Clock Start-Up Delay.................................................................................................................. 52
11.2.5 Input Frequencies and PS Key Settings..................................................................................... 53
11.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 54
11.3.1 XTAL Mode ................................................................................................................................ 54
11.3.2 Load Capacitance ...................................................................................................................... 55
11.3.3 Frequency Trim .......................................................................................................................... 55
11.3.4 Transconductance Driver Model ................................................................................................56
11.3.5 Negative Resistance Model .......................................................................................................56
11.3.6 Crystal PS Key Settings ............................................................................................................. 57
11.3.7 Crystal Oscillator Characteristics ............................................................................................... 57
11.4 UART Interface...................................................................................................................................... 60
11.4.1 UART Bypass............................................................................................................................. 62
11.4.2 UART Configuration while RESETB is Active ............................................................................ 62
11.4.3 UART Bypass Mode................................................................................................................... 62
11.5 USB Interface ........................................................................................................................................ 63
11.5.1 USB Data Connections .............................................................................................................. 63
11.5.2 USB Pull-Up Resistor................................................................................................................. 63
11.5.3 Power Supply............................................................................................................................. 63
11.5.4 Self-powered Mode .................................................................................................................... 63
11.5.5 Bus-powered Mode .................................................................................................................... 64
11.5.6 Suspend Current ........................................................................................................................ 65
11.5.7 Detach and Wake-Up Signalling ................................................................................................ 65
11.5.8 USB Driver ................................................................................................................................. 65
11.5.9 USB Compliance........................................................................................................................ 66
11.5.10 USB 2.0 Compatibility .......................................................................................................... 66
11.6 Serial Peripheral Interface ..................................................................................................................... 66
11.6.1 Instruction Cycle......................................................................................................................... 66
11.6.2 Writing to BlueCore4-ROM CSP ................................................................................................ 67
Contents
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11.6.3 Reading from BlueCore4-ROM CSP.......................................................................................... 67
11.6.4 Multi-Slave Operation................................................................................................................. 67
11.7 Audio PCM Interface ............................................................................................................................. 68
11.7.1 PCM Interface Master/Slave ......................................................................................................68
11.7.2 Long Frame Sync....................................................................................................................... 69
11.7.3 Short Frame Sync ...................................................................................................................... 69
11.7.4 Multi Slot Operation.................................................................................................................... 70
11.7.5 GCI Interface.............................................................................................................................. 70
11.7.6 Slots and Sample Formats......................................................................................................... 71
11.7.7 Additional Features .................................................................................................................... 71
11.7.8 PCM Timing Information ............................................................................................................ 72
11.7.9 PCM Slave Timing ..................................................................................................................... 74
11.7.10 PCM_CLK and PCM_SYNC Generation ............................................................................. 75
11.7.11 PCM Configuration .............................................................................................................. 76
11.8 I/O Parallel Ports ................................................................................................................................... 77
11.8.1 PIO Defaults for BlueCore4-ROM CSP...................................................................................... 77
11.9 I2C Master.............................................................................................................................................. 78
11.10 TCXO Enable OR Function ........................................................................................................ 78
11.11 Resetting BlueCore4-ROM CSP ................................................................................................ 79
11.11.1 Pin States during Reset ....................................................................................................... 79
11.11.2 Status after Reset ................................................................................................................ 80
11.12 Power Supply............................................................................................................................. 80
11.12.1 Voltage Regulator ................................................................................................................ 80
11.12.2 Sequencing.......................................................................................................................... 80
11.12.3 Sensitivity to Disturbances................................................................................................... 80
12 Application Schematic.................................................................................................................................81
13 Package Dimensions...................................................................................................................................82
14 Ordering Information...................................................................................................................................83
14.1 BlueCore4-ROM CSP............................................................................................................................ 83
15 Contact Information.....................................................................................................................................84
16 Document References.................................................................................................................................85
Terms and Definitions ........................................................................................................................................86
Document History...............................................................................................................................................89
Contents
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List of Figures
Figure 3.1: BlueCore4-ROM CSP Package ............................................................................................................ 9
Figure 7.1: BlueCore4-ROM CSP Device Diagram for CSP Package .................................................................. 38
Figure 9.1: BlueCore HCI Stack ............................................................................................................................ 42
Figure 10.1: Basic Data Rate and Enhanced Data Rate Packet Types ................................................................46
Figure 10.2: π/4 DQPSK Constellation Pattern ..................................................................................................... 47
Figure 10.3: 8DPSK Constellation Pattern ............................................................................................................ 48
Figure 11.1: Circuit RF_A and RF_B..................................................................................................................... 49
Figure 11.2: Internal Power Ramping.................................................................................................................... 50
Figure 11.3: TCXO Clock Accuracy ...................................................................................................................... 52
Figure 11.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting......................................... 53
Figure 11.5: Crystal Driver Circuit ......................................................................................................................... 54
Figure 11.6: Crystal Equivalent Circuit .................................................................................................................. 55
Figure 11.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency............................. 57
Figure 11.8: Crystal Driver Transconductance vs. Driver Level Register Setting..................................................58
Figure 11.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting ......................................... 59
Figure 11.10: Break Signal.................................................................................................................................... 61
Figure 11.11: UART Bypass Architecture ............................................................................................................. 62
Figure 11.12: USB Connections for Self Powered Mode ...................................................................................... 64
Figure 11.13: USB Connections for Bus-Powered Mode ...................................................................................... 64
Figure 11.14: USB_DETACH and USB_WAKE_UP Signalling.............................................................................65
Figure 11.15: Write Operation............................................................................................................................... 67
Figure 11.16: Read Operation............................................................................................................................... 67
Figure 11.17: BlueCore4-ROM CSP as PCM Interface Master............................................................................. 68
Figure 11.18: BlueCore4-ROM CSP as PCM Interface Slave............................................................................... 69
Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)............................................................. 69
Figure 11.20: Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 69
Figure 11.21: Multi Slot Operation with Two Slots and 8-bit Companded Samples .............................................. 70
Figure 11.22: GCI Interface................................................................................................................................... 70
Figure 11.23: 16-Bit Slot Length and Sample Formats ......................................................................................... 71
Figure 11.24: PCM Master Timing Long Frame Sync ........................................................................................... 73
Figure 11.25: PCM Master Timing Short Frame Sync........................................................................................... 73
Figure 11.26: PCM Slave Timing Long Frame Sync ............................................................................................. 74
Figure 11.27: PCM Slave Timing Short Frame Sync............................................................................................. 75
Figure 11.28: Example EEPROM Connection ...................................................................................................... 78
Figure 11.29: Example TXCO Enable OR Function .............................................................................................. 78
Figure 12.1: Application Circuit for CSP Package ................................................................................................. 81
Figure 14.1: BlueCore4-ROM CSP Package Dimensions..................................................................................... 82
Contents
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List of Tables
Table 10.1: Data Rate Schemes ........................................................................................................................... 46
Table 10.2: 2-Bits Determine Phase Shift Between Consecutive Symbols........................................................... 47
Table 10.3: 3-Bits Determine Phase Shift Between Consecutive Symbols........................................................... 48
Table 11.1: PSKEY_TXRX_PIO_CONTROL Values ............................................................................................ 51
Table 11.2: External Clock Specifications ............................................................................................................. 51
Table 11.3: PS Key Values for CDMA/3G Phone TCXO Frequencies .................................................................. 53
Table 11.4: Crystal Specification........................................................................................................................... 55
Table 11.5: Possible UART Settings ..................................................................................................................... 60
Table 11.6: Standard Baud Rates ......................................................................................................................... 61
Table 11.7: USB Interface Component Values ..................................................................................................... 65
Table 11.8: Instruction Cycle for an SPI Transaction ............................................................................................ 66
Table 11.9: PCM Master Timing............................................................................................................................ 72
Table 11.10: PCM Slave Timing............................................................................................................................ 74
Table 11.11: PSKEY_PCM_LOW_JITTER_CONFIG Description ........................................................................ 76
Table 11.12: PSKEY_PCM_LOW_JITTER_CONFIG Description ........................................................................ 77
Table 11.13: Pin States of BlueCore4-ROM CSP on Reset.................................................................................. 79
List of Equations
Equation 11.1: Output Voltage with Load Current ≤ 10mA.................................................................................... 50
Equation 11.2: Output Voltage with No Load Current ........................................................................................... 50
Equation 11.3: Load Capacitance ......................................................................................................................... 55
Equation 11.4: Trim Capacitance .......................................................................................................................... 55
Equation 11.5: Frequency Trim ............................................................................................................................. 56
Equation 11.6: Pullability....................................................................................................................................... 56
Equation 11.7: Transconductance Required for Oscillation .................................................................................. 56
Equation 11.8: Equivalent Negative Resistance.................................................................................................... 56
Equation 11.9: Baud Rate ..................................................................................................................................... 61
Equation 11.10: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock........................ 75
Equation 11.11: PCM_SYNC Frequency Relative to PCM_CLK........................................................................... 75
Status Information
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1 Status Information
The status of this Data Sheet is Advance Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of
the design. Minimum and maximum values specified are only given as guidance to the final specification limits
and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-Production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not
be considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
RoHS Compliance
BlueCore4-ROM devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the
Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Paten t s and Licenses
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by
Cambridge Silicon Radio Limited or its affiliates. Bluetooth® and the Bluetooth logos are trademarks owned by
Bluetooth SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have
been trademarked by their respective owners.
Windows®, Windows 98™, Windows 2000™, Windows XP™ and Windows NT™ are registered trademarks of
the Microsoft Corporation.
OMAP™ is a trademark of Texas Instruments Inc.
The publication of this information does not imply that any license is granted under any patent or other rights
owned by Cambridge Silicon Radio Limited.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
CSR’s products are not authorised for use in life-support or safety-critical applications
.
Key Features
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2 Key Features
Radio
! Common TX/RX terminals simplify external
matching and eliminates external antenna switch
! BIST minimises production test time. No external
trimming is required in production
! Full RF reference designs are available
! Bluetooth v2.0 + EDR Specification compliant
Transmitter
! +6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
! Class 2 and Class 3 support without the need for
an external power amplifier or TX/RX switch
! Class 1 support using external power amplifier, with
RF power controlled by an internal 8-bit DAC
! Supports DQPSK (2Mbps) and 8DPSK (3Mbps)
modulation
Receiver
! Integrated channel filters
! Digital demodulator for improved sensitivity and co-
channel rejection
! Real-time digitised RSSI available on HCI interface
! Fast AGC for enhanced dynamic range
! Supports DQPSK and 8DPSK modulation
! Channel classification
Synthesiser
! Fully integrated synthesizer requires no external
VCO varactor diode, resonator or loop filter
! Compatible with crystals between 8 and 40MHz (in
multiples of 250kHz) or an external clock
! Accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44,
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic
level signals
Auxiliary Features
! Crystal oscillator with built-in digital trimming
! Power management includes digital shut down and
wake up commands with an integrated low-power
oscillator for ultra-low Park/Sniff/Hold mode
! Clock Request output to control an external clock
source
Auxiliary Features (continued)
! Device can run in low power modes from an
external 32KHz clock signal
! Auto Baud Rate setting for different TCXO
frequencies
! On-chip linear regulator, producing 1.8V output
from 2.2-4.2V input
! Power-on-reset cell detects low supply voltage
Baseband and Software
! Internal 48-KByte RAM, allows full-speed data
transfer, mixed voice and data, and full piconet
operation, including all medium rate preset types
! Logic for forward error correction, header error
control, access code correlation, CRC,
demodulation, encryption bit stream generation,
whitening and transmit pulse shaping. Supports all
Bluetooth v2.0 + EDR features including eSCO and
AFH
! Transcoders for A-law, μ-law and linear voice from
host and A-law, μ-law and CVSD voice over air
Physical Interfaces
! Synchronous serial interface up to 4Mbaud for
system debugging
! UART interface with programmable baud rate up to
3Mbits/s with an optional bypass mode
! Full-speed USB v2.0 interface supports OHCI and
UHCI host interfaces
! Synchronous bi-directional serial programmable
audio interface
! Optional I2C™ compatible interfaces
! Optional 802.11 co-existence interfaces
Bluetooth Stack
CSR’s Bluetooth protocol stack runs on the on-chip
MCU in a variety of configurations:
! Standard HCI (UART or USB)
! Customised builds with embedded application code
Package Options
! 47-ball CSP 3.8 x 4.0 x 0.7mm
CSP Package Information
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3 CSP Package Information
3.1 BlueCore4-ROM CSP Pinout Diagram
A
B
C
D
E
F
G
1234567
A2 A3 A4 A5 A6 A7
A2 A3 A4 A5 A6 A7
B1 B2 B3 B4 B5 B6 B7
C1 C2 C3 C4 C5 C6 C7
D2 D3
E1 E2 E3
F1 F2 F3
G1 G2 G3
D5 D6 D7
E5 E6 E7
F5 F6 F7
G5 G6 G7
D4
E4
F4
G4
Orientation from top of device
Figure 3.1: BlueCore4-ROM CSP Package
CSP Package Information
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3.2 BC41B143AXX-IXF Device Terminal Functions
Radio Ball Pad Type Description
RF_A E2 Analogue Transmitter output/switched receiver input
RF_B E1 Analogue Complement of RF_A
AUX_DAC D2 Analogue Voltage DAC
Synthesiser and
Oscillator Ball Pad Type Description
XTAL_IN A3 Analogue For crystal or external clock input
XTAL_OUT B3 Analogue Drive for crystal
PCM Interface Ball Pad Type Description
PCM_OUT E4
CMOS output, tri-statable
with weak internal pull-
down
Synchronous data output
PCM_IN B7
CMOS input, with weak
internal pull-down Synchronous data input
PCM_SYNC D5
Bi-directional with weak
internal pull-down Synchronous data sync
PCM_CLK B6
Bi-directional with weak
internal pull-down Synchronous data clock
USB and UART Ball Pad Type Description
UART_TX C5
CMOS output, tri-statable
with weak internal pull-up UART data output active high
UART_RX D4
CMOS input with weak
internal pull-down UART data input active high
UART_RTS A7
CMOS output, tri-statable
with weak internal pull-up UART request to send active low
UART_CTS C4
CMOS input with weak
internal pull-down UART clear to send active low
USB_DP B5 Bi-directional
USB data plus with selectable internal
1.5kΩ Pull-up resistor
USB_DN A6 Bi-directional USB data minus
CSP Package Information
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Test and Debug Ball Pad Type Description
RESETB E7
CMOS input with weak
internal pull-up
Reset if low. Input debounced so must be
low for >5ms to cause a reset
SPI_CSB G6
CMOS input with weak
internal pull-up
Chip select for Serial Peripheral Interface
(SPI), active low
SPI_CLK G5
CMOS input with weak
internal pull-down SPI clock
SPI_MOSI F6
CMOS input with weak
internal pull-down SPI data input into BlueCore
SPI_MISO F7
CMOS output, tri-state with
weak internal pull-down SPI data output from BlueCore
TEST_EN G7
CMOS input with strong
internal pull-down For test purposes only (leave unconnected)
PIO Port Ball Pad Type Description
PIO[0] F3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[1] F4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[2] G1
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[3] G2
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[4] E6
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[5] F5
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[6] D7
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[7] E5
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[8] E3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[9] F1
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[10] F2
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
AIO[0] D3 Bi-directional Programmable input/output line
AIO[2] C3 Bi-directional Programmable input/output line
CSP Package Information
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Power Supplies and
Control Ball Pad Type Description
VREG_IN A2 Regulator input Regulator input
VDD_USB A5 VDD Positive supply for UART ports and AIOs
VDD_PIO G4 VDD Positive supply for PIO [3:0] and [10:8]
VDD_PADS D6 VDD Positive supply for all other digital
input/output ports, and PIO [7:4]
VDD_CORE C6 VDD Positive supply for internal digital circuitry
VDD_LO B2 VDD Positive supply for VCO and synthesiser
circuitry
VDD_RADIO C2 VDD Positive supply for RF circuitry
VDD_ANA A4 VDD/Regulator output
Positive supply for analogue circuitry and
internal 1.8V regulator output
VSS_DIG C7 VSS Ground connection for internal digital
circuitry and digital ports
VSS_PADS G3 VSS Ground connection for digital ports
VSS_RADIO C1 VSS Ground connections for RF circuitry
VSS_ANA B4 VSS Ground connections for analogue circuitry
VSS_LO B1 VSS Ground connection for VCO and synthesiser
circuitry
Electrical Characteristics
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4 Electrical Characteristics
Absolute Maximum Ratings
Rating Minimum Maximum
Storage temperature -40°C 150°C
Supply voltage: VDD_RADIO, VDD_LO, VDD_ANA, and
VDD_CORE -0.4V 2.2V
Supply voltage: VDD_PADS, VDD_PIO and VDD_USB -0.4V 3.7V
Supply voltage: VREG_IN -0.4V 5.6V
Other terminal voltages VSS-0.4V VDD+0.4V
Recommended Operating Conditions
Operating Condition Minimum Maximum
Operating temperature range -40°C 105°C
Guaranteed RF performance range(1) -40°C 105°C
Supply voltage: VDD_RADIO, VDD_LO, VDD_ANA, and
VDD_CORE 1.7V 1.9V
Supply voltage: VDD_PADS, VDD_PIO and VDD_USB 1.7V 3.6V
Supply voltage: VREG_IN 2.2V 4.2V(2)
Note:
(1) Typical figures are given for RF performance between -40°C and +105°C.
(2) The device will operate without damage with VREG_IN as high as 5.6V. However the RF performance is
not guaranteed above 4.2V.
Electrical Characteristics
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Input/Output Terminal Charac teris tic s
Linear Regulator Minimum Typical Maximum Unit
Normal Operation
Output voltage (Iload = 70mA / VREG_IN = 3.0V) 1.70 1.78 1.85 V
Temperature coefficient -250 - 250 ppm/°C
Output noise(1) - - 1 mV rms
Load regulation (Iload < 70mA) - - 50 mV/A
Settling time(2) - - 50
μs
Maximum output current 70 - - mA
Output current: Minimum load current 5 - - μA
Input voltage - - 4.2(3) V
Dropout voltage (Iload = 70mA) - - 350 mV
Quiescent current (excluding Ioad, Iload < 1mA) 25 35 50 μA
Low Power Mode(4)
Quiescent current (excluding Ioad, Iload < 100μA) 4 7 10
μA
Disabled Mode(5)
Quiescent current 1.5 2.5 3.5 μA
Notes:
(1) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors. Frequency range 100Hz to
100kHz
(2) 1mA to 70mA pulsed load
(3) Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to
damage the rest of BlueCore4-ROM CSP, but output regulation and other specifications are no longer
guaranteed at input voltages in excess of 4.2V
(4) Low power mode is entered and exited automatically when the IC enters/leaves Deep Sleep mode
(5) Regulator is disabled when VREG_EN is pulled low. It can also be disabled by VREG_IN when it is
either open circuit or driven to the same voltage as VDD_ANA
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Digital Terminals Minimum Typical Maximum Unit
Input Voltage Levels
2.7V ≤ VDD ≤ 3.0V -0.4 - 0.8 V
VIL input logic level low 1.7V ≤ VDD ≤ 1.9V -0.4 - 0.4 V
VIH input logic level high 0.7VDD - VDD+0.4 V
Output Voltage Levels
VOL output logic level low,
(lo = 4.0mA) (1), 2.7V ≤ VDD ≤ 3.0V - - 0.2 V
VOL output logic level low,
(lo = 4.0mA) (1), 1.7V ≤ VDD ≤ 1.9V - - 0.4 V
VOH output logic level high,
(lo = -4.0mA) (2), 2.7V ≤ VDD ≤ 3.0V VDD-0.2 - - V
VOH output logic level high,
(lo = -4.0mA) (2), 1.7V ≤ VDD ≤ 1.9V VDD-0.4 - - V
Input and Tri-State Current with:
Strong pull-up -100 -40 -10 μA
Strong pull-down 10 40 100 μA
Weak pull-up -5 -1 -0.2 μA
Weak pull-down 0.2 1 5.0
μA
I/O pad leakage current -1 0 1 μA
CI input capacitance 1.0 - 5.0 pF
Notes:
(1) Current sunk into terminal
(2) Current sourced out of terminal
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
USB Terminals Minimum Typical Maximum Unit
VDD_USB for correct USB operation 3.1 3.6 V
Input threshold
VIL input logic level low - - 0.3VDD_USB V
VIH input logic level high 0.7VDD_USB - - V
Input leakage current
VSS_USB< VIN< VDD_USB(1) -1 1 5
μA
CI Input capacitance 2.5 - 10.0 pF
Output Voltage levels
To correctly terminated USB Cable
VOL output logic level low 0.0 - 0.2 V
VOH output logic level high 2.8 - VDD_USB V
Notes:
(1) Internal USB pull-up disabled
Input/Output Terminal Characteristics (Continued)
Power-on reset Minimum Typical Maximum Unit
VDD_CORE falling threshold 1.40 1.50 1.60 V
VDD_CORE rising threshold 1.50 1.60 1.70 V
Hysteresis 0.05 0.10 0.15 V
Input/Output Terminal Characteristics (Continued)
Auxiliary ADC Minimum Typical Maximum Unit
Resolution - - 8 Bits
Input voltage range
(LSB size = VDD_ANA/255) 0 - VDD_ANA V
Accuracy INL -1 - 1 LSB
(Guaranteed monotonic) DNL 0 - 1 LSB
Offset -1 - 1 LSB
Gain error -0.8 - 0.8 %
Input bandwidth - 100 - kHz
Conversion time - 2.5 -
μs
Sample rate - - 700
Samples/
s
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Auxiliary DAC Minimum Typical Maximum Unit
Resolution - - 8 Bits
Average output step size(1) 12.5 14.5 17.0 mV
Output Voltage monotonic
Voltage range (IO=0mA) VSS_PADS - VDD_PIO V
Current range -10.0 - +0.1 mA
Minimum output voltage (IO=100μA) 0.0 - 0.2 V
Maximum output voltage (IO=10mA) VDD_PIO-0.3 - VDD_PIO V
High Impedance leakage current -1 - +1
μA
Offset -220 - +120 mV
Integral non-linearity(1) -2 - +2 LSB
Settling time (50pF load) - - 10
μs
Note:
(1) Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Output is high impedance when chip
is in Deep Sleep mode."
Electrical Characteristics
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Input/Output Terminal Characteristics (Continued)
Crystal Oscillator Minimum Typical Maximum Unit
Crystal frequency (1) 8.0 - 40.0 MHz
Digital trim range (2) 5.0 6.2 8.0 pF
Trim step size (2) - 0.1 - pF
Transconductance 2.0 - - mS
Negative resistance(3) 870 1500 2400
Ω
External Clock
Input frequency(4) 8.0 - 40.0 MHz
Clock input level(5) 0.4 - VDD_ANA V pk-pk
Allowable jitter - - 15 ps rms
XTAL_IN input impedance - ≥10 - kΩ
XTAL_IN input capacitance - ≤4 - pF
Notes:
VDD_CORE, VDD_RADIO, VDD_LO and VDD_ANA are at 1.8V unless shown otherwise.
VDD_PADS, VDD_PIO and VDD_USB are at 3.0V unless shown otherwise.
The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
(1) Integer multiple of 250kHz.
(2) The difference between the internal capacitance at minimum and maximum settings of the internal
digital trim.
(3) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
(4) Clock input can be any frequency between 8 and 40MHz in steps of 250kHz and also covers the
CDMA/3G TCXO frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(5)
Clock input can either be sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or
above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN.
Electrical Characteristics
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4.1 Power Consumption
Operation Mode Connection
Type UART Rate
(Kbits/s) Average Unit
Page scan, time interval 1.28s - 115.2 0.41 mA
Inquiry & page scan - 115.2 0.77 mA
ACL data transfer no traffic Master 115.2 6.4 mA
ACL data transfer with file transfer Master 115.2 11 mA
ACL data transfer no traffic Slave 115.2 14 mA
ACL data transfer with file transfer Slave 115.2 17 mA
ACL data transfer 40ms sniff Master 38.4 1.5 mA
ACL data transfer 1.28s sniff Master 38.4 0.19 mA
SCO connection HV1 Master 38.4 34 mA
SCO connection HV3 Master 38.4 17 mA
SCO connection HV3 30ms sniff Master 38.4 17 mA
ACL data transfer 40ms sniff Slave 38.4 1.5 mA
ACL data transfer 1.28s sniff Slave 38.4 0.24 mA
SCO connection HV1 Slave 38.4 34 mA
SCO connection HV3 Slave 38.4 21 mA
SCO connection HV3 30ms sniff Slave 38.4 17 mA
Parked 1.28s beacon Slave 38.4 0.18 mA
Standby Host connection - 38.4 0.03 mA
Reset (RESETB low) - - 40 µA
Note:
Conditions: 20°C, 1.80V supply
Radio Characteristics – Basic Data Rate
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5 Radio Characteristics – Basic Data Rate
5.1 Temperature +20°C
5.1.1 Transmitter
Radio Characteristics VDD = 1.8V Temperature = +20°C
Min Typ Max
Bluetooth
Specification Unit
Maximum RF transmit power(1)(2) - 5.5 - -6 to +4(3) dBm
Variation in RF power over temperature range with
compensation enabled (±)(4) - 1.5 - - dB
Variation in RF power over temperature range with
compensation disabled (±)(4) - 2.5 - - dB
RF power control range - 35 - ≥16 dB
RF power range control resolution (5) - 0.5 - - dB
20dB bandwidth for modulated carrier - 790 - ≤1000 kHz
Adjacent channel transmit power F=F0 ±2MHz(6)(7) - -40 - ≤-20 dBm
Adjacent channel transmit power F=F0 ±3MHz(6)(7) - -45 - ≤-40 dBm
Adjacent channel transmit power F=F0>±3MHz(6)(7) - -55 - ≤-40 dBm
Δf1avg “Maximum Modulation” - 165 -
140<Δf1avg<175 kHz
Δf2max “Minimum Modulation” - 155 - ≥115 kHz
Δf2avg / Δf1avg - 0.99 - ≥0.80 -
Initial carrier frequency tolerance - 6 - ±75 kHz
Drift Rate - 8 - ≤20 kHz/50μs
Drift (single slot packet) - 9 - ≤25 kHz
Drift (five slot packet) - 9 - ≤40 kHz
2nd Harmonic content - -40 - ≤-30 dBm
3rd Harmonic content - -50 - ≤-30 dBm
Note
(1) BlueCore4-ROM CSP firmware maintains the transmit power to be within the Bluetooth specification
v2.0+EDR limits.
(2) Measurement made using a PSKEY_LC_MAX_TX_POWER setting corresponds to a
PSKEY_LC_POWER_TABLE power table entry of 63.
(3) Class 2 RF transmit power range, Bluetooth specification v2.0+EDR.
(4) To some extent these parameters are dependent on the matching circuit used, and its behaviour over
temperature. Therefore these parameters may be beyond CSR’s direct control.
(5) Resolution guaranteed over the range -5dB to -25dB relative to maximum power for Tx Level >20.
(6) Measured at F0 = 2441MHz.
(7) Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-ROM CSP is
guaranteed to meet the ACP performance as specified by the Bluetooth specification v2.0+EDR.
Radio Characteristics – Basic Data Rate
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Radio Characteristics VDD = 1.8V Temperature = +20°C (Continued)
Frequency
(GHz) Min Typ Max Cellular Band Unit
0.869 – 0.894(1) - -130 - GSM 850
0.869 – 0.894(2) - -134 - CDMA 850
0.925 – 0.960(1) - -133 - GSM 900
1.570 – 1.580(3) - -137 - GPS
1.805 – 1.880(1) - -141 - GSM 1800 /
DCS 1800
1.930 – 1.990(4) - -142 - PCS 1900
1.930 – 1.990(1) - -140 - GSM 1900
1.930 – 1.990(2) - -140 - CDMA 1900
2.110 – 2.170(2) - -140 - W-CDMA 2000
Emitted power in
cellular bands
measured at the
unbalanced port of
the balun.
Output power
≤5dBm
2.110 – 2.170(5) - -140 - W-CDMA 2000
dBm
/Hz
Notes:
(1) Integrated in 200kHz bandwidth and then normalised to a 1Hz bandwidth.
(2) Integrated in 1.2MHz bandwidth and then normalised to a 1Hz bandwidth.
(3) Integrated in 1MHz bandwidth and then normalised to a 1Hz bandwidth.
(4) Integrated in 30kHz bandwidth and then normalised to a 1Hz bandwidth.
(5) Integrated in 5MHz bandwidth and then normalised to a 1Hz bandwidth.
Radio Characteristics – Basic Data Rate
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5.1.2 Receiver
Radio Characteristics VDD = 1.8V Temperature = +20°C
Frequency
(GHz) Min Typ Max Bluetooth
Specification Unit
2.402 - -84 -
2.441 - -84 -
Sensitivity at 0.1% BER for all
packet types
2.480 - -84 -
≤-70 dBm
Maximum received signal at 0.1% BER - >10 - ≥-20 dBm
Frequency
(MHz) Min Typ Max Bluetooth
Specification Unit
30 – 2000 - >0 - -10
2000 – 2400 - >-10 - -27
2500 – 3000 - >0 - -27
Continuous power required to
block Bluetooth reception (for
sensitivity of -67dBm with 0.1%
BER) measured at the
unbalanced port of the balun. 3000 – 3300 - >3 - -10
dBm
C/I co-channel - 8 - ≤11 dB
Adjacent channel selectivity C/I F=F0 +1MHz(1) (2) - -5 - ≤0 dB
Adjacent channel selectivity C/I F=F0 −1MHz(1) (2) - -4 - ≤0 dB
Adjacent channel selectivity C/I F=F0 +2MHz(1) (2) - -45 - ≤-30 dB
Adjacent channel selectivity C/I F=F0 −2MHz(1) (2) - -22 - ≤-20 dB
Adjacent channel selectivity C/I F≥F0 +3MHz(1) (2) - -48 - ≤-40 dB
Adjacent channel selectivity C/I F≤F0 −5MHz(1) (2) - -45 - ≤-40 dB
Adjacent channel selectivity C/I F=FImage(1) (2) - -23 - ≤-9 dB
Maximum level of intermodulation interferers (3) - -30 - ≥-39 dBm
Spurious output level (4) - -160 - - dBm/Hz
Notes:
(1) Up to five exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-ROM CSP is
guaranteed to meet the C/I performance as specified by the Bluetooth specification v2.0+EDR.
(2) Measured at F0 = 2441MHz.
(3) Measured at f1-f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test
RCV/CA/05/c. i.e. wanted signal at -64dBm.
(4) Measured at the unbalanced port of the balun. Integrated in 100kHz bandwidth and then normalized to
1Hz. Actual figure is typically below -160dBm/Hz except for peaks of -60dBm at 1.6GHz, -45dBm inband
at 2.4GHz and -60dBm at 3.2GHz.