DM74ALS241ANX_NL - FAIRCHILD SEMICONDUCTOR

September 1986

Revised February 2000

DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

DM74ALS74A

Dual D Positive-Edge-Triggered Flip-Flop

with Preset and Clear

General Descript ion

The DM74ALS74A contains two independent positive

edge-triggered flip-flops. Each flip-flop has individual D,

clock, clea r and prese t inputs, and also compl ementary Q

and Q outputs.

Informati on at input D is transf erred to the Q ou tput o n the

positive going edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not

directly related to the transition time of the positive going

pulse. Wh en the clock in put is at either the HIGH or LOW

level, the D input signal has no effect.

Asynchronous preset and clear inputs will set or clear Q

output respectively upon the application of low level signal.

Features

■Switching specifications at 50 pF

■Switching specifications guaranteed over full tempera-

ture and VCC range

■Advanced oxide-isolated, ion-implanted Schottky TTL

process

■Functionally and pin-for-pin compatible with Schottky

and LS TTL counterpart

■Improved AC performance over LS74 at approximately

half the power

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering c ode.

Connection Diagram Function Table

L = LOW State

H = HIGH State

X = Don't Care

↑ = Positi v e Edge Transition

Q0 = Previou s Co ndition of Q

Note 1: This condit ion is nonstable; it wil l not persist whe n preset and clear

inputs ret urn to their inac tive (HIGH) level. The ou tput levels in th is condi-

tion are not guarant eed to me et th e VOH spec if ic at ion.

Order Number Package Number Package Description

DM74ALS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74ALS74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74ALS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

PR CLR CLK D Q Q

LHXX H L

HLXX L H

L L X X H (Note 1) H (Note 1)

HH↑HH L

HH↑LL H

HHLX Q

0Q 0

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DM74ALS74A

Logic Diagram

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DM74ALS74A

Absolute Maximum Ratings(Note 2)

Note 2: The “A bsol ute M axim um Ratin gs” are those valu es b eyo nd which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 3: Th e (↑) arrow indicates t he positiv e edge of th e C lock is used for ref erence.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Typical θJA

N Package 87.0°C/W

M Package 117.0°C/W

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.5 5 5.5 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency 0 34 MHz

tW(CLK) Width of Clock Pulse HIGH 14.5 ns

LOW 14.5 ns

tWPulse Width LOW 14.5 ns

Preset & Clear

tSU Data Setup Time Data 15↑ (Note 3)

PRE or CLR 10↑ (Note 3) ns

Inactive

tHData Hold Time 0↑ (Note 3) ns

TAFree Air Operating Temperature 0 70 °C

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DM74ALS74A

Electrical Characteristics

over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Note 4: ICC is meas ured wit h D , CL K and PR ESET grounded, t hen with D, CL K and CL EAR grounded.

Note 5: IIL PRE and CL R pins not gua rantee d t o m eet specif ic at ions with both PRE and CLK LOW.

Switching Characteri stics

over recommended operating free air temperature range.

Symbol Parameter Conditions Min Typ Max Units

VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.5 V

VOH HIGH Level IOH = −0.4 mA VCC − 2V

Output Voltage VCC = 4.5V to 5.5V

VOL LOW Level VCC = 4.5V IOL = 8 mA 0.35 0.5 V

Output Voltage VIH = 2V

IIInput Current @ VCC = 5.5V, Clock, D 0.1 mA

Max Input V oltag e VIH = 7V Preset, Clear 0.2

IIH HIGH Level VCC = 5.5V, Clock, D 20 µA

Input Current VIH = 2.7V Preset, Clear 40

IIL LOW Level VCC = 5.5V, Clock, D −0.2 mA

Input Current VIL = 0.4V Preset, Clear (Note 5) −0.4

IOOutput Drive Current VCC = 5.5V, VO = 2.25V −30 −112 mA

ICC Supply Current VCC = 5.5V (Note 4) 2.4 4 mA

Parameter Conditions From To Min Max Units

fMAX VCC = 4.5V to 5.5V 34 MHz

tPLH RL = 500ΩPreset or Clear Q or Q 313ns

tPHL CL = 50 pF 515ns

tPLH Clock Q or Q 516ns

tPHL 518ns

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DM74ALS74A

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M14A

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DM74ALS74A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Packag e Num be r N14A

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the labe l ing, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any compo nent o f a l ife supp ort

device or system whose failure to perform can be rea-

sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t

device or system, or to affect its safety or effectiveness.