VNH7100AS Automotive fully integrated H-bridge motor driver Datasheet - production data Description SO-16N GAPGCFT00648 Features Type RDS(on) Iout VCCmax VNH7100AS 100 mtyp per leg) 12 A 41 V The device is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver and two low-side switches. Both switches are designed using STMicroelectronics' well known and proven proprietary VIPower(R) M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/protection circuitry. The three dies are assembled in SO-16N package on electrically isolated leadframes. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals INA and INB can directly interface the microcontroller to select the motor direction and the brake condition. A SEL0 pin is available to address the information available on the MultiSense to the microcontroller. The MultiSense pin allows to monitor the motor current by delivering a current proportional to the motor current value. Automotive qualified Output current: 15 A 3 V CMOS-compatible inputs Undervoltage shutdown Overvoltage clamp Thermal shutdown Cross-conduction protection Current and power limitation Very low standby power consumption Protection against loss of ground and loss of VCC PWM operation up to 20 kHz The PWM, up to 20 kHz, allows to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin turns off both the LSA and LSB switches. Table 1. Device summary MultiSense diagnostic functions - Analog motor current feedback - Output short to ground detection - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection Order codes Package SO-16N Tube Tape and reel -- VNH7100ASTR Output protected against short to ground and short to VCC Standby Mode Half Bridge Operation Package: ECOPACK(R) May 2016 This is information on a product in full production. DocID028092 Rev 6 1/38 www.st.com Contents VNH7100AS Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 6 2/38 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 OFF-state open-load detection - External circuitry dimensioning . . . . . . 23 3.3 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 24 3.4 Device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 SO16-N thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Package thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 Thermal characterization in steady state conditions . . . . . . . . . . . . . . . 28 4.2.2 Thermal characterization during transients . . . . . . . . . . . . . . . . . . . . . . 29 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 SO-16N packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID028092 Rev 6 VNH7100AS List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40C < Tj < 150C) . . . . . . . . . . . . 10 Switching (VCC = 13 V; RLOAD = 5.2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics (VCC = 7 V up to 18 V; -40C < Tj < 150C). . . . . . . . . . . . . . 11 CS (7 V < VCC < 18 V; -40 C < Tj < 150 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state fault conditions - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Off-state - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 24 Thermal model for junction temperature calculation in steady-state conditions\ . . . . . . . . 29 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO-16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO-16N carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID028092 Rev 6 3/38 3 List of figures VNH7100AS List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. 4/38 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Time to shutdown for the low-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input reset time for HSD - fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input reset time for LSD - fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . . . 17 Normal operative conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OUT shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application schematic with reverse battery protection connected to Vbatt . . . . . . . . . . . . . 22 Application schematic with reverse battery protection connected to GND . . . . . . . . . . . . . 22 Suggested PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Half-bridge configuration (case a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Half-bridge configuration (case b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2 . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCB 4 layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chipset configuration configuration in steady state conditions . . . . . . . . . . . . . . . . . . . . . . 28 Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air condition . . . . . . . . 29 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electrical equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO-16N package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO-16N reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO-16N carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO-16N schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SO-16N marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID028092 Rev 6 VNH7100AS 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram 9&& 32:(5 /,0,7$7,21 /6$B29(57(03(5$785( /6%B29(57(03(5$785( 89 +6$B29(57(03(5$785( +6%B29(57(03(5$785( &/$03+6$ +6$ &/$03+6% '5,9(5 +6$ 0QFOMPBE 0''TUBUF" +6% '5,9(5 +6% /2*,& &855(17 /,0,7$7,21% &855(17 /,0,7$7,21$ 0QFOMPBE 0''TUBUF# )$8/7 287$ . '(7(&7,21 287% . &/$03/6$ &/$03/6% '5,9(5 /6 $ /6$ '5,9(5 /6% .69 /6% /6'%29(5/2$' /6'$29(5/2$' '(7(&725$ '(7(&725% ,1$ *1'$ &6 6(/ ,1% 3:0 *1'% ("1($'5 Table 2. Block description Name Description Logic control Allows the turn-on and the turn-off of the high-side and the low-side switches according to the truth table. Undervoltage Shuts down the device for battery voltage lower than 4 V. High-side and low-side clamp voltage Protect the high-side and the low-side switches from the high voltage on the battery line. High-side and low-side driver Drive the gate of the concerned switch to allow a proper Ron for the leg of the bridge. Current limitation Limits the motor current in case of short circuit. In case of short-circuit with the increase of the junction High-side and low-side overtemperature temperature, it shuts down the concerned driver to prevent protection degradation and to protect the die. Low-side overload detector Detects when low side current exceeds shutdown current and latches off the concerned Low side. DocID028092 Rev 6 5/38 37 Block diagram and pin description VNH7100AS Table 2. Block description (continued) Name Description Fault detection Signalizes the abnormal behavior of the switch through MultiSense pin. Power limitation Limits the power dissipation of the high-side driver inside safe range in case of short to ground condition. Figure 2. Configuration diagram (top view) *1'$ *1'$ 287$ 287$ ,1 $ 9&& 6(/ 9&& &6 9&& ,1% 3:0 287% 287% *1'% *1'% 621 *$3*&)7 Table 3. Pin definitions and functions 6/38 Pin N Symbol Function 1, 16 GNDA Source of low-side switch A 2, 15 OUTA Source of high-side switch A / drain of low-side switch A 3 INA Clockwise input 4, 5, 12 VCC Power supply voltage 6 INB Counter clockwise input 7, 10 OUTB Source of high-side switch B / drain of low-side switch B 8, 9 GNDB Source of low-side switch B 11 PWM Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low-side FETS get modulated by the PWM signal during their on phase allowing speed control of the motor. Active high. 13 CS Multiplexed analog sense output pin; it delivers a current proportional to the motor current. 14 SEL0 Active high compatible with 3 V and 5 V CMOS outputs pin; in combination with INA, INB, it addresses the CurrentSense information delivered to the micro according to the operative truth table. DocID028092 Rev 6 VNH7100AS 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions *4 **/" **/# *065" 7$$ */" 065" */# *4&- 065# 4&- *18. $4 18. (/% 7$$ *065# 7065" *4&/4& 74&/4& 7065# *(/% 7*/" 7*/# 74&- 718. ("1($'5 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage 38 V -VCC Reverse DC Supply Voltage 0.3 V Imax Maximum output current (continuous) Internally limited A IR Reverse output current (continuous) -15 A VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V Input current (INA and INB pins) -1 to 10 mA ISEL0 SEL0 DC input current -1 to 10 mA IPWM PWM input current -1 to 10 mA IIN ISENSE CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 CS pin DC output current in reverse (VCC < 0 V) -20 DocID028092 Rev 6 mA 7/38 37 Electrical specifications VNH7100AS Table 4. Absolute maximum ratings (continued) Symbol Value Unit VESD Electrostatic discharge (Human body model: R = 1.5 k; C = 100 pF) - INA,INB, PWM - SEL0 - CS - VCC - Output 2 2 2 4 4 VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 C Storage temperature -55 to 150 C Tc TSTG 2.2 Parameter kV Thermal data Table 5. Thermal data Symbol Rthj-pin Parameter Thermal resistance junction-pin Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 2. Device mounted on four-layers 2s2p PCB. 8/38 DocID028092 Rev 6 Unit HSD 32 C/W LSD 45 C/W 51-2)(1) Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2)(2) 1. Device mounted on two-layers 2s0p PCB. Max. value See Figure 24 C/W HSD 40.7 C/W LSD 55.4 C/W VNH7100AS 2.3 Electrical specifications Electrical characteristics Values specified in this section are for VCC = 7 V up to 28 V; -40C < Tj < 150C, unless otherwise specified. Table 6. Power section Symbol VCC IS Parameter Test conditions Operating supply voltage Min. 4 Supply current V Off-state (standby) INA = INB = 0; SEL0 = 0; PWM = 0; Tj = 25 C; VCC = 13 V; 1 A Off-state (standby) INA = INB = 0; SEL0 = 0; PWM = 0; VCC = 13 V; Tj = 85C 1 A Off-state (standby) INA = INB = 0; SEL0 = 0; PWM = 0; VCC = 13 V; Tj = 125 C 3 A 2 4 mA 3.5 6 mA 1 1.8 ms On-state: INA or INB = 5 V; PWM = 0 or PWM = 5; SEL0 = X Standby mode blanking time RONHS Static high-side resistance RONLS Static low-side resistance Vf IL(off) IL(off_h) VCC = 13 V; INA = INB = PMW = 0 V; VSEL0 from 5 V to 0 V 0.2 IOUT = 2.5 A; Tj = 25C 60 IOUT = 2.5 A; Tj = -40 to 150C 40 IOUT = 2.5 A; Tj = -40C to 150C IOUT = -2.5 A; Tj = 150C Off-state output current of one leg Off-state output current of one leg with other HSD on m 120 IOUT = 2.5 A; Tj = 25C Free-wheeling diode forward voltage Max. Unit 28 Off-state (no standby) INA = INB = 0; SEL0 = 5 V; PWM= 0 tD_STBY(1) Typ. 0.7 m m 80 m 0.9 V INA = INB = 0; PWM = 0; VCC = 13 V; Tj = 25 C 0 0.5 A INA = INB = 0; PWM = 0; VCC = 13 V; Tj = 125 C 0 3 A INA = 0; INB = 5 V; PWM = 0; VCC = 13 V 20 60 A 1. To power on the device from the standby, it is recommended to: -- toggle INA or INB from 0 to 1 first to come out from STBY mode -- toggle PWM from 0 to 1 with a delay of 20 s this avoids any over-stress on the device in case of existing short-to-battery. DocID028092 Rev 6 9/38 37 Electrical specifications VNH7100AS Table 7. Logic inputs (INA, INB, PWM) (VCC = 7 V up to 28 V; -40C < Tj < 150C) Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V VIL Input low level voltage VIH Input high level voltage 2.1 V VIHYST Input hysteresis voltage 0.2 V IIN = 1 mA VICL Input clamp voltage IINL Input current VIN = 0.9 V IINH Input current VIN = 2.1 V 5.3 7.2 IIN = -1 mA -0.7 V V 1 A 10 A 0.9 V SEL0 (VCC = 7 V up to 18 V; -40C < Tj < 150C) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL VSEL = 0.9 V 1 A 2.1 V VSEL = 2.1 V 0.2 ISEL = 1 mA Input clamp voltage 10 A V 5.3 7.5 ISEL = -1 mA -0.8 V V PWM (VCC= 7 V up to 28 V; -40C < Tj < 150C) VPWM Input low level voltage IPWM Low level input current VPWM Input high level voltage IPWMH High level input current 0.9 VPWM = 0.9 V VPMWCL A 2.1 V 10 0.2 IPWM = 1 mA Input clamp voltage 1 VPWM = 2.1 V VPWM(hyst) Input hysteresis voltage V A V 5.3 7.2 IPWM = -1 mA -0.7 V V Table 8. Switching (VCC = 13 V; RLOAD = 5.2 ) Symbol f(1) Parameter Test conditions PWM frequency Min. Typ. Max. 0 kHz td(on) Turn-on delay time Input rise time < 1s (see Figure 6) 20 s td(off) Turn-off delay time Input rise time < 1s (see Figure 6) 13 s tr Rise time See Figure 5 0.7 1.5 s tf Fall time See Figure 5 0.2 0.5 s Low-side turn-on delay time Input rise time < 1 s (see Figure 7) 150 350 s tcross 40 1. Parameter guaranteed by design and characterization; not subjected to production test. 10/38 20 Unit DocID028092 Rev 6 VNH7100AS Electrical specifications Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40C < Tj < 150C) Symbol Parameter Test conditions Min. Typ. Max. Unit VUSD Undervoltage shutdown 4 V VUSDreset Undervoltage shutdown reset 5 V VUSDHyst Undervolatge shutdown Hysteresis 0.4 V ILIM_H High-side current limitation 12 18 24 A ISD_LS Shutdown LS current 14 22 30 A tSD_LS Time to shutdown for the VINA = VINB = 0 V; low-side PWM = 5 V (see Figure 8) 5 s VCL_HSD High-side clamp voltage (VCC to OUTA = 0 or OUTB = 0) IOUT = 100 mA; tCLAMP = 1 ms 38 46 V VCL_LSD Low-side clamp voltage (OUTA = VCC or OUTB = VCC to GND) IOUT = 100 mA; tCLAMP = 1 ms 38 46 V TTSD_HS High-side thermal shutdown temperature INx = 2.1 V 150 175 TTR_HS High-side thermal reset temperature THYST_HS 200 135 High-side thermal hysteresis (TSD_HS TR_HS) C C 7 C Low-side thermal shutdown temperature INx = 0 V 150 175 200 C VCL Total clamp voltage (VCC to GND) IOUT = 100 mA; tCLAMP = 1 ms 38 46 52 V VOL OFF-state open-load voltage detection threshold INA = INB = 0; PWM = 0; VSEL0 = 5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB 2 3 4 V IL(off2) OFF-state output sink current INA = INB = 0; VOUTx = VOL; PWM = 0 V; VSEL0 = 5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB -15 A tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 4) INA = 5 V to 0 V; INB = 0 V; VSEL0 = 5 V; IOUT = 0 A; VOUTA = 4 V; PWM = 0 V 150 350 s tD_VOL(1) OFF-state diagnostic delay time from rising edge of VOUT (see Figure 11) INA = INB = 0 V; PWM = 0 V; VOUTx = 0 V to 4 V; VSEL0 = 5 V for CHA; VSEL0 = 0 V and within tD_STBY for CHB 5 30 s TTSD_LS DocID028092 Rev 6 -100 40 11/38 37 Electrical specifications VNH7100AS Table 9. Protections and diagnostics (VCC = 7 V up to 18 V; -40C < Tj < 150C) Symbol Parameter Test conditions Min. Typ. Max. Unit Input reset time for highVINx = 5 V to 0 V; HSDx tLatch_RST_HD(1) side fault unlatch (see faulting Figure 9) 3 10 20 s Input reset time for lowtLatch_RST_LS(1) side fault unlatch (see Figure 10) 3 10 20 s VINx = 0 V to 5 V; LSDx faulting 1. Parameter guaranteed by design and characterization; not subjected to production test. Table 10. CS (7 V < VCC < 18 V; -40 C < Tj < 150 C) Symbol VSENSE_CL Test conditions MultiSense clamp voltage Min. VCC = 18 V; ISENSE = -5 mA Typ. Max. Unit 11 VCC = 18 V; ISENSE = 5 mA -13 V -9 K0 IOUT/ISENSE IOUT = 0.05 A; VSENSE = 0.5 V; Tj = -40C to 150C 420 K1 IOUT/ISENSE IOUT = 0.2 A; VSENSE = 0.5 V; Tj = -40C to 150C 710 1190 1670 K2 IOUT/ISENSE IOUT = 2.5 A; VSENSE = 4 V; Tj = -40C to 150C 980 1120 1247 K3 IOUT/ISENSE IOUT = 4 A; VSENSE = 4 V; Tj = -40C to 150C 990 1120 1235 V dK0/K0(1)(2) Analog sense current IOUT = 0.05 A; VSENSE = 0.5 V; drift Tj = -40C to 150C -25 25 % dK1/K1(1)(2) Analog sense current IOUT = 0.2 A; VSENSE = 0.5 V; drift Tj = -40C to 150C -21 21 % dK2/K2(1)(2) Analog sense current IOUT = 2.5 A; VSENSE = 4 V; drift Tj = -40C to 150C -5 5 % dK3/K3(1)(2) Analog sense current IOUT = 4 A; VSENSE = 4 V; drift Tj = -40C to 150C -4 4 % VSENSE_SAT Max analog sense output voltage ISENSE0 12/38 Parameter MultiSense leakage current VCC = 7 V; RSENSE = 10 k; VSEL0 = 5 V; IOUTA = 4 A; VINA = 5 V; PWM = 0; Tj = 150 C 5 IOUT = 0 A; VSENSE = 0 V; INx = 0 V; SEL0 = 0; Tj = -40C to 150C (standby) 0 0.5 A IOUT = 0 A; VSENSE = 0 V; INx = 0 V; SEL0 = 5 V; Tj = -40C to 150C (no standby) 0 0.5 A INx = 5 V; PWM = 5 V: Tj = -40C to 150C; IOUT = 0 A 0 5 A DocID028092 Rev 6 V VNH7100AS Electrical specifications Table 10. CS (7 V < VCC < 18 V; -40 C < Tj < 150 C) (continued) Symbol VSENSEH Parameter Test conditions MultiSense output voltage in fault condition VCC = 13 V; RSENSE = 1 k - E.g: OUTA in open-load INA = 0 V; IOUTA = 0 A; VOUTA = 4 V; VSEL0 = 5 V VOUT_MSD(2) VINA = 5 V; VINB = 0 V; Output Voltage for VSEL0 = 5 V; RSENSE = 2.7 k MultiSense shutdown IOUT = 2.5 A ISENSE_SAT(2) MultiSense saturation current VCC = 13 V; VSENSE = 4 V; VINA = 5 V; VINB = 0 V; VSEL0 = 5 V; Tj = 150 C IOUT_SAT(2) Output saturation current ISENSEH MultiSense output voltage in fault condition Min. Typ. Max. Unit 5 7 5 V V 5.8 mA VCC = 13 V; VSENSE = 4 V; VINA = 5 V; VINB = 0 V; VSEL0 = 5 V; IOUT = 7 A; Tj = 150C 7 A VCC = 13 V; VSENSE = VSENSEH 7 20 30 mA 1. Analog sense current drift is deviation of factor K for a given device over (-40 C to 150 C and 9 V < VCC < 18 V) with respect to its value measured at Tj = 25 C, VCC = 13 V. 2. Parameter guaranteed by design and characterization; not subjected to production test. Figure 4. TDSTKON 9,1387 9287 9287!92/ 0XOWL6HQVH 7'67.21 *$3*&)7 DocID028092 Rev 6 13/38 37 Electrical specifications VNH7100AS Figure 5. Definition of the low-side switching times PWM t VOUTA, B 90% tf 80% 20% 10% tr t Figure 6. Definition of the high-side switching times VINA tD(off) tD(on) t VOUTA 90% 10% t 14/38 DocID028092 Rev 6 VNH7100AS Electrical specifications Figure 7. Low-side turn-on delay time ,1$ W ,1% W 3:0 W 2XW$ WFURVV W 2XW% W ("1(3* Figure 8. Time to shutdown for the low-side driver ,/6' ,6'B/6 ,RS 9VHQVH 9VHQVH 9VHQVH+ W6'B/6 9VHQVHBQRP ("1($'5 DocID028092 Rev 6 15/38 37 Electrical specifications VNH7100AS Figure 9. Input reset time for HSD - fault unlatch ,1$ 287$ 5HVHW3XOVH )DXOW+6$ )DXOWUHPRYLQJ 0XOWL6HQVH )DXOWFOHDQLQJ 9 PXOWLBVHQVH+ 7ODWFKB567B+6' 9VHQVHBQRP *$3*&)7 Figure 10. Input reset time for LSD - fault unlatch ,1$ 287$ 5HVHW3XOVH WFURVV )DXOW/6$ 2XW$6KRUWWR9&& )DXOWUHPRYLQJ 0XOWLVHQVH )DXOWFOHDQLQJ 9 PXOWLBVHQVH+ 7B/DFKWB567B/6' *$3*&)7 16/38 DocID028092 Rev 6 VNH7100AS Electrical specifications Figure 11. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) ,1$ 287$ )DXOW9287!92/ &6 9VHQVH+ W'B92/ *$3*&)7 DocID028092 Rev 6 17/38 37 Electrical specifications VNH7100AS Table 11. Operative condition - truth table Pin status INA INB 1 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 SEL0 PWM 1 x 0 1 0 1 (2) On Off On Off On Off Off On On Off Off Off On Off Off On On Off Off Off Off On On Off Off Off On Off Off On On Off Off Off On Off Off On Off On Off Off Off Off Off Off Off Off Current Monitoring HSDA Hi-Z Hi-Z 0 0 LSDA Current Monitoring HSDB 1 0 HSDA Current Monitoring HSDA 0 1 0 CS 1 1 HSDs and LDSs Status Current Monitoring HSDB 1 Hi-Z 0 x(1) HSDB LSDB 1. Refer to Table 13: Off-state - truth table 2. For INA =INB=SEL0 = PWM = 0, the device enters in standby after tD_STBY Table 12. On-state fault conditions - truth table Digital Input pins CS Note: 18/38 Comment INA INB PWM SEL0 0 0 1 0 VsenseH LSB protection triggered; LSB latched off 0 0 1 1 VsenseH LSA protection triggered; LSA latched off 0 1 X 0 VsenseH HSB protection triggered; HSB latched off 0 1 1 1 VsenseH LSA protection triggered; LSA latched off 1 0 1 0 VsenseH LSB protection triggered; HSB latched off 1 0 X 1 VsenseH HSA protection triggered; HSA latched off 1 1 X 0 Hi-Z HSB protection triggered; HSB latched off 1 1 X 1 Hi-Z HSA protection triggered; HSA latched off Other logic combinations on digital input pins not reported on the above table don't allow to detect a latched off channel. DocID028092 Rev 6 VNH7100AS Electrical specifications Table 13. Off-state - truth table INA INB SEL0 PWM OutA OutB CS Description VSENSEH Case 1. OutA shorted to VCC if no pull-up is applied Case 2. No open-load in full bridge configuration with an external pullup on OutB Case 3. open-load in half bridge configuration with an external pullup on OutA(motor connected between OutA and Ground) Hi-Z Case 1. Open-load in full Bridge configuration with an external pullup on OutB Case 2. No open-load in half Bridge configuration with external pull-up on OutA (motor connected between OutA and Ground) Off-state diagnostic VoutA>VOL x 1 VoutA<VOL 0 0 x 0 Case 1. OutB shorted to VCC if no pull-up is applied X VoutB>VOL VSENSEH Case 2. No open-load in full bridge configuration with external pull-up on OutA Case 3. Open-load in half bridge configuration with external pull-up on OutB (motor connected between OutB and Ground) 0(1)(2) X VoutB<VOL Hi-Z Case1. Open-load in full Bridge configuration with an external pullup on OutA Case 2. No open-load in half Bridge configuration with external pull-up on OutB (motor connected between OutB and Ground) 1. The device enters standby mode after tD_STBY 2. To power on the device from the standby, it is recommended to toggle INA or INB from 0 to 1 first and then PWM from 0 to 1 to avoid any over-stress on the device in case of short-to-battery. DocID028092 Rev 6 19/38 37 Electrical specifications 2.4 VNH7100AS Waveforms Figure 12. Normal operative conditions 9,1$ 9,1% 93:0 96(/ 9287$ 9287% ,/RDG 9VHQVH ("1($'5 Figure 13. OUT shorted to ground and short clearing 0VUY4IPSUFE5P(OE 'BVMU$MFBSJOH s/E ZW K^ZZ' &ZZ s/E ZW K^ZZ' &ZZ sWtD s^> sKhd sKhd sZ s^, />ZZ s^E^ />K ("1($'5 20/38 DocID028092 Rev 6 VNH7100AS Electrical specifications Figure 14. OUT shorted to Vcc and short clearing 0VUY4IPSUFE5P7DD 'BVMU$MFBSJOH s/E ZW K^ZZs s/E &ZZ ZW K^ZZs &ZZ sWtD s^> sKhd sKhd s^E^ s^, />ZZ />K ("1($'5 DocID028092 Rev 6 21/38 37 Application information 3 VNH7100AS Application information Here following there is the typical application schematic suggested for a proper operation of the device in DC or PWM conditions. Figure 15. Application schematic with reverse battery protection connected to Vbatt 9%DWW 30RVIHW 5HJ 9 =' 9 . 9FF Q) . ,1$ . ,1% . 3:0 5SXOOBXS & ) +6% +6$ ([WHUQDO SXOOXS VZLWFK & . 6(/ 287% 287$ 0 . &6 2SHQORDGLQRII VWDWHGHWHFWLRQ FLUFXLWU\ /6$ /6% Q 5VHQVH *1' *1' ("1($'5 Figure 16. Application schematic with reverse battery protection connected to GND 9FF 5HJ9 Q) 9FF . ,1$ . ,1% & ) +6$ . 3:0 . 6(/ 5SXOOBXS +6% & . Q 287$ 0 287% ([WHUQDO SXOOXS VZLWFK /6$ &6 /6% 5VHQVH *1' *1' Q) 2SHQORDGLQRII VWDWHGHWHFWLRQ FLUFXLWU\ ']!9 . 10RVIHW ("1($'5 22/38 DocID028092 Rev 6 VNH7100AS Application information Figure 17. Suggested PCB layout Note: PCB layout recommendation: Optimized connection (short) between Drain LSD and Source HSD Optimized GNDa and GNDb connection (symmetric connection) 3.1 Reverse battery protection Three possible solutions can be considered: A Schottky diode D connected to VCC pin An N-channel MOSFET connected to the GND pin A P-channel MOSFET connected to the VCC pin In case the reverse battery protection is not present, the device sustains no more than -15 A because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of the device is pulled down to the VCC line (approximately -1.5 V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is: V IOs - V CC R = -----------------------------I Rmax 3.2 OFF-state open-load detection - External circuitry dimensioning The detection of an open-load in off state requires an external circuitry to be connected between Output and VBATT. For the detection it is necessary to put one network on each leg in case of Half Bridge operation or one network on one of the output in case of full bridge (see Table 13: Off-state truth table). The external circuitry is made up by an external pull-up resistor Rpull_up connecting the output to a positive supply voltage VPU (VBatt). DocID028092 Rev 6 23/38 37 Application information VNH7100AS It is preferable to switch-off VPU by using an external pull_up switch to reduce the overall standby current during he module standby mode. Rpull_up must be dimensioned to ensure that in normal operative conditions VOUT > VOLmax. To satisfy this condition the Rpull_up must be selected according to: if the device is used in half bridge configuration, the equation is: V BATTmin - V OLmax R pull_up -------------------------------------------------------I L(off2)min[@VOLmax] if the device is used in H-bridge configuration, the equation is: V BATTmin - V OLmax R pull_up -------------------------------------------------------------2 I L(off2)min[@VOLmax] 3.3 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 14. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 14. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112 V 500 pulses 0,5 s 2a III +55 V 500 pulses 0,2 s 5s 50s, 2 3a IV -220 V 1h 90 ms 100 ms 0.1s, 50 3b IV +150 V 1h 90 ms 100 ms 0.1s, 50 (2) IV -7 V 1 pulse 4 min max 2ms, 10 100ms, 0.0 1 Load dump according to ISO 16750-2:2010 Test B(3) 40 V 5 pulse 1 min 400 ms, 2 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 24/38 DocID028092 Rev 6 VNH7100AS Application information 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40C < Tj < 150C). 3.4 Device configurations Figure 18. Half-bridge configuration (case a) 9FF ,1$ 3:0 6(/ &6 ,1% 2XW$ 2XW% 0 0 *1' *1' *1' ("1($'5 Note: The VNH7100AS can be used in half bridge configuration as the two legs can be independently driven. The SEL0 pin can be used to address the diagnostic on the CS according to the operative truth table. Figure 19. Half-bridge configuration (case b) 9FF ,1$ ,1% 6(/ &6 3:0 2XW$ 2XW% 0 *1' 3:0 ,1$ ,1% 6(/ &6 2XW% 2XW$ *1' ("1($'5 Note: The VNH7100AS can be used in applications where an half-bridge with a resistance of 50 m per leg is needed. DocID028092 Rev 6 25/38 37 Application information VNH7100AS Figure 20. Multi-motors configuration 9FF ,1$ 3:0 6(/ &6 ,1% 2XW$ 2XW% 0 *1' ,1% ,1$ 3:0 6(/ &6 2XW% 2XW$ *1' 0 0 ("1($'5 Note: 26/38 The VNH7100AS can easily be designed in multi motor driving configuration in the applications where only one motor at a time must be activated. The SEL0 pin can be used to read the diagnostic on the CS according to the operative truth table. DocID028092 Rev 6 VNH7100AS Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO16-N thermal data Figure 21. PCB layout (top and bottom): footprint, 2+2+2 cm2, 8+8+8 cm2 DocID028092 Rev 6 27/38 37 Package and PCB thermal data VNH7100AS Figure 22. PCB 4 layer Note: Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board dimension 77x86 mm; Board Material FR4; Cu thickness 0.070mm (outer layers); Cu thickness 0.035mm (inner layers); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm. 4.2 Package thermal data 4.2.1 Thermal characterization in steady state conditions Figure 23. Chipset configuration configuration in steady state conditions $IJQ 3UI# 3UI"# $IJQ 3UI" 3UI"$ 3UI#$ $IJQ 3UI$ ("1($'5 28/38 DocID028092 Rev 6 VNH7100AS Package and PCB thermal data Figure 24. Auto and mutual Rthj-amb vs. PCB heat-sink area in open box free air condition 5WK$ 5WK% 5WK& 5WK$% 5WK$& 5WK%& &: FP RI&X$UHD UHIHUWR3&%/D\HUOD\RXW ("1($'5 Table 15. Thermal model for junction temperature calculation in steady-state conditions\ Chip 1 Chip 2 Chip 3 4.2.2 Tjchip1 Tjchip2 Tjchip3 ON OFF ON Pdchip1 * RthA + Pdchip3 * RthAC + Tamb Pdchip1 * RthAB + Pdchip3 * RthBC + Tamb Pdchip1 * RthAC + Pdchip3 * RthC + Tamb ON ON OFF Pdchip1 * RthA + Pdchip2 * RthAB + Tamb Pdchip1 * RthAB + Pdchip2 * RthB + Tamb Pdchip1 * RthAC + Pdchip2 * RthBC + Tamb ON OFF OFF Pdchip1 * RthA+ Tamb Pdchip1 * RthAB + Tamb Pdchip1 * RthAC + Tamb ON ON ON Pdchip1 * RthA + (Pdchip2 Pdchip2 * RthB + Pdchip1 * Pdchip1 * RthAB + Pdchip2 + Pdchip3) * RthAB + RthAB + Pdchip3 * RthBC * RthBC + Pdchip3 * RthC Tamb + Tamb + Tamb Thermal characterization during transients Ths= Pdhs * Zhs + Zhsls * (PdlsA + PdlsB) + Tamb TlsA= PdlsA * Zls + Pdhs * Zhsls + PdlsB * Zlsls + Tamb TlsB= PdlsB * Zls + Pdhs * Zhsls + PdlsA * Zlsls + Tamb DocID028092 Rev 6 29/38 37 Package and PCB thermal data VNH7100AS Figure 25. HSD thermal impedance junction ambient single pulse =7++6'#FXDUHD &: +6'IRRWSULQW +6'FPA&X +6'FPA&X +6'/D\HU +V/V'IRRWSULQW =KV +V/V'FPA&X +V/V'FPA&X +V/V'/D\HU =KVOV WLPH VHF ("1($'5 Figure 26. LSD thermal impedance junction ambient single pulse =7+/6'#FXDUHD &: /6'IRRWSULQW /6'FPA&X /6'FPA&X /6'/D\HU /V/V'IRRWSULQW =OV /V/V'FPA&X /V/V'FPA&X /V/V'/D\HU =OVOV WLPH VHF 30/38 DocID028092 Rev 6 ("1($'5 VNH7100AS Package and PCB thermal data Figure 27. Electrical equivalent model Table 16. Thermal parameters Area/island (cm2) FP 2 8 4L R1 (C/W) 5.3 5.3 5.3 5.3 R2 (C/W) 12 12 12 12 R3 (C/W) 30 25 25 30 R4 (C/W) 42 12 12 2 R5 (C/W) 85 45 30 17 R6 (C/W) 5.3 5.3 5.3 5.3 R7 (C/W) 5.1 5.1 5.1 5.1 R8 (C/W) 12 12 12 12 R9 (C/W) 30 30 30 42 R10 (C/W) 68 52 48 10 R11 (C/W) 75 80 60 26 R12 (C/W) 5.1 5.1 5.1 5.1 R13 (C/W) 12 12 12 12 R14 (C/W) 30 30 30 42 R15 (C/W) 68 52 48 10 R16 (C/W) 75 80 60 26 R17 (C/W) 120 100 100 100 R18 (C/W) 120 100 100 100 R19 (C/W) 180 170 170 170 R20 (C/W) 180 170 170 170 DocID028092 Rev 6 31/38 37 Package and PCB thermal data VNH7100AS Table 16. Thermal parameters (continued) 32/38 Area/island (cm2) FP 2 8 4L C1 (W*s/C) 0.00065 0.00065 0.00065 0.00065 C2 (W*s/C) 0.018 0.018 0.018 0.018 C3 (W*s/C) 0.08 0.1 0.1 0.1 C4 (W*s/C) 0.2 0.5 1 2 C5 (W*s/C) 1.5 2 6 12 C6 (W*s/C) 0.00065 0.00065 0.00065 0.00065 C7 (W*s/C) 0.001 0.001 0.001 0.001 C8 (W*s/C) 0.02 0.02 0.02 0.02 C9 (W*s/C) 0.06 0.06 0.06 0.06 C10 (W*s/C) 0.08 0.1 0.2 0.5 C11 (W*s/C) 1 2.5 3 6 C12 (W*s/C) 0.00065 0.00065 0.00065 0.00065 C13 (W*s/C) 0.02 0.02 0.02 0.02 C14 (W*s/C) 0.06 0.06 0.06 0.06 C15 (W*s/C) 0.08 0.1 0.2 0.5 C16 (W*s/C) 1 2.5 3 6 DocID028092 Rev 6 VNH7100AS 5 Package and packing information Package and packing information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.1 SO-16N mechanical data Figure 28. SO-16N package dimensions ("1($'5 DocID028092 Rev 6 33/38 37 Package and packing information VNH7100AS Table 17. SO-16N mechanical data Millimeters Symbol Min. Typ. Max. A 1.75 A1 0.10 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8 ccc 5.2 0.10 SO-16N packing information Figure 29. SO-16N reel 13" "DDFTT)PMFBU 4MPU-PDBUJPO NNNJO 8 " / % $ 8 # 34/38 *GQSFTFOU UBQFTMPUJODPSF GPSUBQFTUBSU NNNJOXJEUIY NNNJOEFQUI 5"1($'5 DocID028092 Rev 6 VNH7100AS Package and packing information Table 18. Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 16.4 W2 (max) 22.4 1. All dimensions are in mm. Figure 30. SO-16N carrier tape ("1($'5 Table 19. SO-16N carrier tape dimensions Description Value A0 6.55 0.1 B0 10.38 0.1 K0 2.10 0.1 K1 1.80 0.1 F 7.50 0.1 DocID028092 Rev 6 35/38 37 Package and packing information VNH7100AS Table 19. SO-16N carrier tape dimensions (continued) Description Value P1 8.00 0.1 W 16.00 0.3 Figure 31. SO-16N schematic drawing of leader and trailer tape 5.3 SO-16N marking information Figure 32. SO-16N marking information .BSLJOHBSFB 4QFDJBMGVODUJPOEJHJU &4&OHJOFFSJOHTBNQMF CMBOL$PNNFSDJBMTBNQMF 40/5017*&8 OPUJOTDBMF ("1($'5 Note: Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. 36/38 DocID028092 Rev 6 VNH7100AS 6 Revision history Revision history Table 20. Document revision history Date Revision Changes 16-Jul-2015 1 Initial release. 01-Sep-2015 2 Table 8: Switching (VCC = 13 V; RLOAD = 5.2 ): - tcross: updated values Table 9: Protections and diagnostics (VCC = 7 V up to 18 V; -40C < Tj < 150C): - ISD_LS, tDSTKON: updated values Table 10: CS (7 V < VCC < 18 V; -40 C < Tj < 150 C): - K2, K3, ISENSE_SAT: updated values 04-Sep-2015 3 Table 4: Absolute maximum ratings: - IR: updated value 07-Oct-2015 4 Table 4: Absolute maximum ratings: - -IGND: removed row Updated Table 5: Thermal data Table 6: Power section: - Vf: updated parameter Updated Figure 9: Input reset time for HSD - fault unlatch and Figure 10: Input reset time for LSD - fault unlatch Added Section 2.4: Waveforms and Chapter 4: Package and PCB thermal data Updated Chapter 3: Application information 21-Oct-2015 5 Updated Table 12: On-state fault conditions - truth table 23-May-2016 6 Table 8: Switching (VCC = 13 V; RLOAD = 5.2 ): - Tr, Tf: updated maximum values Updated Table 12: On-state fault conditions - truth table DocID028092 Rev 6 37/38 37 VNH7100AS IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved 38/38 DocID028092 Rev 6