LM2722
LM2722 High Speed Synchronous/Asynchronous MOSFET Driver
Literature Number: SNVS169B
LM2722
OBSOLETE
September 23, 2011
High Speed Synchronous/Asynchronous MOSFET Driver
General Description
The LM2722, part of the LM2726 family, is designed to be
used with multi-phase controllers. This part differs from the
LM2726 by changing the functionality of the SYNC_EN pin
from a whole chip enable to a low side MOSFET enable. As
a result, the SYNC_EN pin now provides control between
Synchronous and Asynchronous operations. Having this con-
trol can be advantageous in portable systems since Asyn-
chronous operations can be more efficient at very light loads.
The LM2722 drives both top and bottom MOSFETs in a push-
pull structure simultaneously. It takes a logic level PWM input
and splits it into two complimentary signals with a typical 20ns
dead time in between. The built-in cross-conduction protec-
tion circuitry prevents the top and bottom FETs from turning
on simultaneously. The cross-conduction protection circuitry
detects both the driver outputs and will not turn on a driver
until the other driver output is low. With a bias voltage of 5V,
the peak sourcing and sinking current for each driver of the
LM2722 is typically 3A. In an SO-8 package, each driver is
able to handle 50mA average current. Input UVLO (Under-
Voltage-Lock-Out) forces both driver outputs low to ensure
proper power-up and power-down operation. The gate drive
bias voltage needed by the high side MOSFET is obtained
through an external bootstrap. Minimum pulse width is as low
as 55ns.
Features
Synchronous or Asynchronous Operation
Adaptive shoot-through protection
Input Under-Voltage-Lock-Out
Typical 20ns internal delay
Plastic 8-pin SO package
Applications
Driver for LM2723 Intel Mobile Northwood CPU core
power supply.
High Current DC/DC Power Supplies
High Input Voltage Switching Regulators
Fast Transient Microprocessors
Typical Application
20028901
Note: National is an Intel Mobile Voltage Positioning (IMVP) licensee.
© 2011 National Semiconductor Corporation 200289 www.national.com
200289 Version 3 Revision 3 Print Date/Time: 2011/09/23 15:04:03
LM2722 High Speed Synchronous/Asynchronous MOSFET Driver
Connection Diagram
8-Lead Small Outline Package
20028902
Top View
Ordering Information
Order Number Package Type NSC Package Drawing Supplied As
LM2722 LM2722M M08A 95 Units/Rail
LM2722MX 2500 Units/Reel
Pin Descriptions
Pin Name Function
1 SW Top driver return. Should be connected to the common node of top and bottom FETs
2 HG Top gate drive output
3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver
4 PWM_IN Accepts a 5V-logic control signal
5 SYNC_EN Low gate Enable
6 VCC Connect to +5V supply
7 LG Bottom gate drive output
8 GND Ground
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LM2722
Block Diagram
20028904
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LM2722
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC 7.5V
CBOOT 42V
CBOOT to SW 8V
SW to PGND 36V
Junction Temperature +150°C
Power Dissipation
(Note 2) 720mW
Storage Temperature −65° to 150°C
ESD Susceptibility
Human Body Model (Note 3) 1kV
Soldering Time, Temperature 10sec., 300°C
Operating Ratings (Note 1)
VCC 4V to 7V
Junction Temperature Range −40° to 125°C
Electrical Characteristics
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ =
+25°C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol Parameter Condition Min Typ Max Units
POWER SUPPLY
Iq_op Operating Quiescent Current PWM_IN = 0V 190 300 µA
TOP DRIVER
Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R =
0.1
3.0 A
Pull-Up Rds_on ICBOOT = IHG = 0.7A 1.0 Ω
Peak Pull-down Current Test Circuit 2, Vbias = 5V, R =
0.1
−3.2 A
Pull-down Rds_on ISW = IHG = 0.7A 0.5 Ω
t4Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns
t6Fall Time 12 ns
t3Pull-Up Dead Time Timing Diagram 23 ns
t5Pull-Down Delay Timing Diagram, from PWM_IN
Falling Edge 27 ns
BOTTOM DRIVER
Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R =
0.1 3.2 A
Pull-up Rds_on IVCC = ILG = 0.7A 1.0 Ω
Peak Pull-down Current Test Circuit 4, Vbias = 5V, R =
0.1 3.2 A
Pull-down Rds_on IGND = ILG = 0.7A 0.5
t8Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns
t2Fall Time 14 ns
t7Pull-up Dead Time Timing Diagram 28 ns
t1Pull-down Delay Timing Diagram, from PWM_IN
Rising Edge 13 ns
LOGIC
Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 43.7 V
Vuvlo_dn Under-Voltage-Lock-Out
Threshold
3.0 2.5 V
Vuvlo_hys Under-Voltage-Lock-Out
Hysteresis
0.7 V
VIH_EN SYNC_EN Pin High Input 2.4 V
VIL_EN SYNC_EN Pin Low Input 0.8 V
Ileak_EN SYNC_EN Pin Leakage
Current
EN = 5V −2 2µA
EN = 0V −2 2
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LM2722
Symbol Parameter Condition Min Typ Max Units
ton_min Minimum Positive Input Pulse
Width
(Note 4)
55
ns
toff_min Minimum Negative Input Pulse
Width
(Note 5)
55
VIH_PWM PWM_IN High Level Input
Voltage
When PWM_IN pin goes high
from 0V 2.4
V
VIL_PWM PWM_IN Low Level Input
Voltage
When PWM_IN pin goes low from
5V 0.8
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the
ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-to-
ambient thermal resistance, θJA, for the LM2722, it is 172°C/W. For a TJMAX of 150°C and TA of 25°C, the maximum allowable power dissipation is 0.7W.
Note 3: ESD machine model susceptibility is 100V.
Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is
off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is
off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
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LM2722
Timing Diagram
20028903
Test Circuits
20028905
Test Circuit 1
20028906
Test Circuit 2
20028907
Test Circuit 3
20028908
Test Circuit 4
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LM2722
Typical Waveforms
20028913
FIGURE 1. Switching Waveforms of Test Circuit
20028914
FIGURE 2. When Input Goes High
20028915
FIGURE 3. When Input Goes Low
20028916
FIGURE 4. Minimum Positive Pulse
Application Information
MINIMUM PULSE WIDTH
In order for the shoot-through prevention circuitry in the
LM2722 to work properly, the pulses into the PWM_IN pin
must be longer than 55ns. The internal logic waits until the
first FET is off plus 20ns before turning on the opposite FET.
If, after a falling edge, a rising edge occurs sooner than the
specified time, toff_min, the IC may intermittently fail to turn on
the top gate when the bottom gate is off. As the rising edge
occurs sooner and sooner, the driver may start to ignore the
pulse and produce no output. This condition results in the
PWM_IN pin in a high state and neither FET turned on. To get
out of this state, the PWM_IN pin must see a low signal for
greater than 55ns, before the rising edge.
This will also assure that the gate drive bias voltage has been
restored by forcing the top FET source and Cboot to ground
first. Then the internal circuitry is reset and normal operation
will resume.
Conversely, if, after a rising edge, a falling edge occurs soon-
er than the specified miniumum pulse width, ton_min, the IC
may intermittently fail to turn on the bottom FET. As the falling
edge occurs sooner and sooner, the driver will start to ignore
the pulse and produce no output. This will result in the toff in-
ductor current taking a path through a diode provided for non-
synchronous operation. The circuit will resume synchronous
operation when the rising PWM pulses exceed 55ns in dura-
tion.
HIGH INPUT VOLTAGES OR HIGH OUTPUT CURRENTS
At input voltages above twice the output voltage and at higher
power levels, the designer may find snubber networks and
gate drive limiting useful in reducing EMI and preventing in-
jurious transients. A small resistor, 1 to 5, between the
driver outputs and the MOSFET gates will slightly increase
the rise time and fall time of the output stage and reduce
switching noise. The trade-off is 1% to 2% in efficiency.
A series R-C snubber across in parallel with the bottom FET
can also be used to reduce ringing. Values of 10nF and
10 to 100 are a good starting point.
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LM2722
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Package
NS Package Number M08A
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LM2722
Notes
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LM2722
Notes
LM2722 High Speed Synchronous/Asynchronous MOSFET Driver
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