I2C-Compatible, 256-Position Digital Potentiometers AD5241/AD5242 FEATURES APPLICATIONS Multimedia, video, and audio Communications Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage-to-current conversion Line impedance matching FUNCTIONAL BLOCK DIAGRAM A1 W1 B1 O1 O2 SHDN VDD RDAC REGISTER 1 REGISTER 2 VSS ADDR DECODE SDA SCL GND 8 AD5241 PWR-ON RESET SERIAL INPUT REGISTER AD0 00926-001 256 positions 10 k, 100 k, 1 M Low temperature coefficient: 30 ppm/C Internal power on midscale preset Single-supply 2.7 V to 5.5 V or dual-supply 2.7 V for ac or bipolar operation I2C-compatible interface with readback capability Extra programmable logic outputs Self-contained shutdown feature Extended temperature range: -40C to +105C AD1 Figure 1. AD5241 Functional Block Diagram A1 W1 B1 A2 W2 B2 SHDN O1 O2 REGISTER VDD RDAC REGISTER 1 RDAC REGISTER 2 VSS ADDR DECODE SDA SCL GND AD5242 8 SERIAL INPUT REGISTER AD0 PWR-ON RESET AD1 00926-002 1 Figure 2. AD5242 Functional Block Diagram GENERAL DESCRIPTION The AD5241/AD5242 provide a single-/dual-channel, 256position, digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper, or the B terminal and the wiper. For the AD5242, the fixed A-to-B terminal resistance of 10 k, 100 k, or 1 M has a 1% channel-to-channel matching tolerance. The nominal temperature coefficient of both parts is 30 ppm/C. Wiper position programming defaults to midscale at system power on. When powered, the VR wiper position is programmed by an I2C(R)-compatible, 2-wire serial data interface. Both parts have two extra programmable logic outputs available that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. The AD5241/AD5242 are available in surface-mount, 14-lead SOIC and 16-lead SOIC packages and, for ultracompact solutions, 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended temperature range of -40C to +105C. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2001-2009 Analog Devices, Inc. All rights reserved. AD5241/AD5242 TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 11 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 Functional Block Diagram .............................................................. 1 Programming the Variable Resistor ......................................... 12 General Description ......................................................................... 1 Programming the Potentiometer Divider ............................... 13 Revision History ............................................................................... 2 Digital Interface .......................................................................... 13 Specifications..................................................................................... 3 Readback RDAC Value .............................................................. 14 10 k, 100 k, 1 M Version .................................................... 3 Multiple Devices on One Bus ................................................... 14 Timing Diagrams.......................................................................... 5 Level-Shift for Bidirectional Interface ..................................... 14 Absolute Maximum Ratings............................................................ 6 Additional Programmable Logic Output ................................ 15 ESD Caution .................................................................................. 6 Shutdown Function .................................................................... 15 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 18 REVISION HISTORY 12/09--Rev. B to Rev. C 2/02--Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to 10 k, 100 k, 1 M Version Section ...................... 3 Changes to Table 3 ............................................................................ 6 Deleted Digital Potentiometer Selection Guide Section ........... 14 Changed Self-Contained Shutdown Function Section to Shutdown Function Section .......................................................... 15 Changes to Shutdown Function Section ..................................... 15 Changes to Ordering Guide .......................................................... 18 Edits to Features.................................................................................1 Edits to Functional Block Diagrams ...............................................1 Edits to Absolute Maximum Ratings ..............................................4 Changes to Ordering Guide .............................................................4 Edits to Pin Function Descriptions .................................................5 Edits to Figures 1, 2, 3 .......................................................................6 Added Readback RDAC Value Section, Additional Programmable Logic Output Section, and Figure 7; Renumbered Sequentially ............................................................. 11 Changes to Digital Potentiometer Selection Guide ................... 14 8/02--Rev. A to Rev. B Additions to Features ....................................................................... 1 Changes to General Description .................................................... 1 Changes to Specifications ................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 4 Additions to Ordering Guide .......................................................... 4 Changes to TPC 8 and TPC 9 ......................................................... 8 Changes to Readback RDAC Value Section................................ 11 Changes to Additional Programmable Logic Output Section .. 11 Added Self-Contained Shutdown Section ................................... 12 Added Figure 8 ................................................................................ 12 Changes to Digital Potentiometer Selection Guide ................... 14 Rev. C | Page 2 of 20 AD5241/AD5242 SPECIFICATIONS 10 k, 100 k, 1 M VERSION VDD = 2.7 V to 5.5 V, VA = VDD, VB = 0 V, -40C < TA < +105C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS, RHEOSTAT MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution Differential Nonlinearity 3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 4 Capacitance (A, B) 5 Capacitance (W)5 Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (AD0 and AD1) Input Logic Low (AD0 and AD1) Input Logic High Input Logic Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Logic Low (SDA) Output Logic Low (O1 and O2) Output Logic High (O1 and O2) Three-State Leakage Current (SDA) Output Capacitance5 POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation 6 Power Supply Sensitivity Symbol Conditions N R-DNL R-INL RAB/RAB RWB, VA = no connect RWB, VA = no connect TA = 25C, RAB = 10 k TA = 25C, RAB = 100 k/1 M VAB = VDD, wiper = no connect IW = VDD/R (RAB/RAB)/ T x 106 RW N DNL INL (VW/VW)/T x 106 VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL VIH VIL VIH VIL IIL CIL VOL VOL VOL VOH IOZ COZ VDD RANGE VDD/VSS RANGE IDD ISS PDISS Min 8 -1 -2 -30 -30 Max Unit 0.4 0.5 +1 +2 +30 +50 Bits LSB LSB % % 30 8 -1 -2 Code = 0x80 Code = 0xFF Code = 0x00 Typ 1 -1 0 60 120 0.4 0.5 5 -0.5 0.5 +1 +2 VSS f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 V A = VB = V W VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIH = 5 V or VIL = GND ppm/C 0 1 VDD VSS = 0 V V pF 60 pF 1 nA 0.7 x VDD -0.5 2.4 0 2.1 0 VDD + 0.5 V +0.3 x VDD VDD 0.8 VDD 0.6 1 0.4 0.6 0.4 4 PSS -0.01 Rev. C | Page 3 of 20 3 1 8 0.1 +0.1 0.5 5.5 2.7 50 -50 250 +0.002 +0.01 2.7 2.3 VIH = 5 V or VIL = GND VSS = -2.5 V, VDD = +2.5 V VIH = 5 V or VIL = GND, VDD = 5 V Bits LSB LSB ppm/C LSB LSB 45 3 IOL = 3 mA IOL = 6 mA ISINK = 1.6 mA ISOURCE = 40 A VIH = 5 V or VIL = GND V V V V V V A pF V V V V A pF V V A A W %/% AD5241/AD5242 Parameter DYNAMIC CHARACTERISTICS5, 7, 8 -3 dB Bandwidth Symbol Conditions Total Harmonic Distortion BW_10 k BW_100 k BW_1 M THDW VW Settling Time tS RAB = 10 k, code = 0x80 RAB = 100 k, code = 0x80 RAB = 1 M, code = 0x80 VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, 1 LSB error band, RAB = 10 k RWB = 5 k, f = 1 kHz Resistor Noise Voltage INTERFACE TIMING CHARACTERISTICS (APPLIES TO ALL PARTS5, 9 ) SCL Clock Frequency Bus Free Time Between Stop and Start, tBUF eN_WB fSCL t1 Hold Time (Repeated Start), tHD; STA t2 Low Period of SCL Clock, tLOW High Period of SCL Clock, tHIGH Setup Time for Repeated Start Condition, tSU; STA Data Hold Time, tHD; DAT Data Setup Time, tSU; DAT Rise Time of Both SDA and SCL Signals, tR t3 t4 t5 t6 t7 t8 Fall Time of Both SDA and SCL Signals, tF Setup Time for Stop Condition, tSU; STO t9 t10 Min 0 1.3 After this period, the first clock pulse is generated Typ 1 Max 650 69 6 0.005 kHz kHz kHz % 2 s 14 nVHz 400 600 1.3 0.6 600 300 s s ns ns ns ns 300 ns 50 900 Typicals represent average readings at 25C, VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37. 4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design, not subject to production test. 6 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use VDD = 5 V. 9 See timing diagram in Figure 3 for location of measured values. 2 Rev. C | Page 4 of 20 kHz s ns 100 1 Unit AD5241/AD5242 TIMING DIAGRAMS t8 SDA t1 t8 t9 t2 t4 t2 P t3 S t7 t5 t10 S t6 P 00926-005 SCL Figure 3. Detail Timing Diagram Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format. Table 2. S 0 1 0 R/W 1 1 AD1 AD0 Slave Address Byte A A/B RS SD O1 O2 X Instruction Byte X X A D7 D6 D5 D4 D3 Data Byte D2 D1 D0 A P where: S = start condition P = stop condition A = acknowledge X = don't care AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0. R/W = Read enable at high and output to SDA. Write enable at low. A/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2. RS = Midscale reset, active high. SD = Shutdown in active high. Same as SHDN except inverse logic. O1, O2 = Output logic pin latched values D7, D6, D5, D4, D3, D2, D1, D0 = data bits. 1 9 1 9 1 9 SCL 1 0 1 1 AD1 R/W AD0 A/B RS SD O1 O2 X X X ACK BY AD5241 START BY MASTER D7 D6 D5 D4 D3 D2 D1 ACK BY AD5241 FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE ACK BY AD5241 STOP BY MASTER FRAME 3 DATA BYTE Figure 4. Writing to the RDAC Serial Register 9 1 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W ACK BY AD5241 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE D7 D6 D5 D4 D3 D2 D1 D0 NO ACK BY MASTER STOP BY FRAME 2 DATA BYTE FROM PREVIOUSLY SELECTED MASTER RDAC REGISTER IN WRITE MODE Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. C | Page 5 of 20 D0 00926-006 0 00926-007 SDA AD5241/AD5242 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND IA, IB, IW RAB = 10 k in TSSOP-14 RAB = 100 k in TSSOP-14 RAB = 1 M in TSSOP-14 Digital Input Voltage to GND Operating Temperature Range Thermal Resistance JA 14-Lead SOIC 16-Lead SOIC 14-Lead TSSOP 16-Lead TSSOP Maximum Junction Temperature (TJ max) Package Power Dissipation Storage Temperature Range Lead Temperature Vapor Phase, 60 sec Infrared, 15 sec 1 Rating -0.3 V to +7 V 0 V to -7 V 7V VSS to VDD ESD CAUTION 5.0 mA 1 1.5 mA1 0.5 mA1 0 V to VDD + 0.3 V -40C to +105C 158C/W 73C/W 206C/W 180C/W 150C PD = (TJ max - TA)/JA -65C to +150C 215C 220C Maximum current increases at lower resistance and different packages. Rev. C | Page 6 of 20 AD5241/AD5242 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A1 1 14 O1 O1 1 16 A2 W1 2 13 NC A1 2 15 W2 12 O2 W1 3 14 B2 SHDN 5 AD5241 TOP VIEW (Not to Scale) AD5242 O2 TOP VIEW VDD 5 (Not to Scale) 12 VSS B1 4 11 VSS 10 DGND 13 9 AD1 SHDN 6 11 DGND 8 AD0 SCL 7 10 AD1 SDA 8 9 AD0 NC = NO CONNECT 00926-003 SCL 6 SDA 7 Figure 6. AD5241 Pin Configuration 00926-004 B1 3 VDD 4 Figure 7. AD5242 Pin Configuration Table 4. AD5241 Pin Function Descriptions Table 5. AD5242 Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic A1 W1 B1 VDD Pin No. 1 2 3 4 5 Mnemonic O1 A1 W1 B1 VDD 5 SHDN 6 SHDN 7 8 9 SCL SDA AD0 10 AD1 11 12 DGND VSS 13 14 15 16 O2 B2 W2 A2 6 7 8 SCL SDA AD0 9 AD1 10 11 DGND VSS 12 13 14 O2 NC O1 Description Resistor Terminal A1. Wiper Terminal W1. Resistor Terminal B1. Positive Power Supply, Specified for Operation from 2.2 V to 5.5 V. Active low, asynchronous connection of Wiper W to Terminal B, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. Serial Clock Input. Serial Data Input/Output. Programmable Address Bit for Multiple Package Decoding. Bit AD0 and Bit AD1 provide four possible addresses. Programmable Address Bit for Multiple Package Decoding. Bit AD0 and Bit AD1 provide four possible addresses. Common Ground. Negative Power Supply, Specified for Operation from 0 V to -2.7 V. Logic Output Terminal O2. No Connect. Logic Output Terminal O1. Rev. C | Page 7 of 20 Description Logic Output Terminal O1. Resistor Terminal A1. Wiper Terminal W1. Resistor Terminal B1. Positive Power Supply, Specified for Operation from 2.2 V to 5.5 V. Active Low, Asynchronous Connection of Wiper W to Terminal B, and Open Circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD, if not used. Serial Clock Input. Serial Data Input/Output. Programmable Address Bit for Multiple Package Decoding. Bit AD0 and Bit AD1 provide four possible addresses. Programmable Address Bit for Multiple Package Decoding. Bit AD0 and Bit AD1 provide four possible addresses. Common Ground. Negative Power Supply, Specified for Operation from 0 V to -2.7 V. Logic Output Terminal O2. Resistor Terminal B2. Wiper Terminal W2. Resistor Terminal A2. AD5241/AD5242 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.5 VDD/VSS = +2.7V/0V 0 VDD/VSS = +5.5V/0V, 2.7V -1.0 0 32 64 96 128 160 CODE (Decimal) 192 224 256 0.25 VDD/VSS = +2.7V 0 VDD/VSS = +2.7V/0V, +5.5V/0V -0.25 -0.50 0 32 64 NOMINAL RESISTANCE (k) VDD/VSS = +5.5V/0V, 2.7V -0.5 128 160 192 224 256 VDD = 2.7V TA = 25C CODE (Decimal) 1k 100k 100 10k 10 1 -40 00926-009 Figure 9. RINL vs. Code 0 20 40 TEMPERATURE (C) 60 80 Figure 12. Nominal Resistance vs. Temperature 0.25 10k VDD = +2.7V VDD = +5.5V VDD = 2.7V IDD SUPPLY CURRENT ( A) 0.13 VDD/VSS = +2.7V/0V, +5.5V/0V, 2.7V 0 -0.13 VDD = 5V 1k VDD = 3V 100 10 VDD = 2.5V -0.25 0 32 64 96 128 160 CODE (Decimal) 192 224 256 00926-010 POTENTIOMETER MODE DIFFERENTIAL NONLINEARITY (LSB) -20 1 0 1 2 3 INPUT LOGIC VOLTAGE (V) 4 Figure 13. Supply Current vs. Input Logic Voltage Figure 10. DNL vs. Code Rev. C | Page 8 of 20 5 00926-013 RHEOSTAT MODE INTEGRAL NONLINEARITY (LSB) 0 96 256 1M 0.5 64 224 1 92 10k VDD = +2.7V VDD = +5.5V VDD = 2.7V VDD/VSS = +2.7V/0V 32 160 Figure 11. INL vs. Code 1.0 0 128 CODE (Decimal) Figure 8. RDNL vs. Code -1.0 96 00926-012 -0.5 VDD = +2.7V VDD = +5.5V VDD = 2.7V 00926-011 POTENTIOMETER MODE INTEGRAL NONLINEARITY (LSB) VDD = +2.7V VDD = +5.5V VDD = 2.7V 00926-008 RHEOSTAT MODE DIFFERENTIAL NONLINEARITY (LSB) 1.0 AD5241/AD5242 100 RAB = 10k VDD = 5.5V TA = 25C 90 80 VDD/VSS = +2.7V/0V 0.01 70 60 50 VDD/VSS = 2.7V/0V 40 30 VDD/VSS = +5.5V/0V 20 0 -20 40 20 60 10 00926-014 0.001 -40 80 TEMPERATURE (C) -3 300 IDD SUPPLY CURRENT (A) 10k VERSION 40 100k VERSION 20 10 0 2 3 4 5 6 B: VDD/VSS = 3.3V/0V CODE = 0xFF C: VDD/VSS = 2.5V/0V CODE = 0xFF D: VDD/VSS = 5.5V/0V CODE = 0x55 200 D A E: VDD/VSS = 3.3V/0V CODE = 0x55 150 F: VDD/VSS = 2.5V/0V CODE = 0x55 100 -10 E B F C 50 0 32 64 96 128 160 192 224 256 CODE (Decimal) 0 10 100 FREQUENCY (kHz) 1k Figure 18. Supply Current vs. Frequency Figure 15. VWB/T Potentiometer Mode Temperature Coefficient 6 120 VDD/VSS = 2.7V/0V TA = 25C 100 0xFF 0 100k VERSION 0x80 -6 80 0x40 -12 60 GAIN (dB) 40 20 0 0x20 -18 0x10 -24 0x08 -30 0x04 -36 -20 10k VERSION 10M VERSION 96 128 160 192 224 256 CODE (Decimal) Figure 16. RWB/T Rheostat Mode Temperature Coefficient Rev. C | Page 9 of 20 -54 100 1k 10k FREQUENCY (Hz) 100k Figure 19. AD5242 10 k Gain vs. Frequency vs. Code 1M 00926-019 64 00926-016 32 0x01 -48 -60 0 0x02 -42 -40 -80 00926-018 -20 -30 RHEOSTAT MODE TEMPCO (ppm/C) 1 A: VDD/VSS = 5.5V/0V CODE = 0xFF 250 00926-015 POTENTIOMETER MODE TEMPCO (ppm/C) 10M VERSION 50 30 0 Figure 17. Incremental Wiper Contact vs. VDD/VSS VDD/VSS = 2.7V/0V TA = 25C 60 -1 COMMON-MODE (V) Figure 14. Shutdown Current vs. Temperature 70 -2 00926-017 WIPER RESISTANCE () SHUTDOWN CURRENT (A) 0.1 AD5241/AD5242 6 6 0 0x80 -6 GAIN (dB) 0x08 -30 0x04 -36 0x20 -18 0x10 -24 0x08 -30 0x04 -36 0x02 -42 0x02 -42 0x01 -48 0x01 -48 -54 100 1k 10k FREQUENCY (Hz) 100k 00926-020 GAIN (dB) 0x10 -24 0x40 -12 0x20 -18 0x80 -6 0x40 -12 0xFF 0 Figure 20. AD5242 100 k Gain vs. Frequency vs. Code -54 100 1k 10k FREQUENCY (Hz) Figure 21. AD5242 1 M Gain vs. Frequency vs. Code Rev. C | Page 10 of 20 100k 00926-021 0xFF AD5241/AD5242 TEST CIRCUITS Figure 22 to Figure 30 define the test conditions used in the product specifications table. 5V OP279 V+ = VDD 1 LSB = V+/2N A VIN W V+ OFFSET GND B W A DUT B OFFSET BIAS 00926-029 VMS VOUT Figure 22. Potentiometer Divider Nonlinearity Error (INL, DNL) 00926-034 DUT Figure 27. Noninverting Gain NO CONNECT A A IW W DUT OFFSET GND B 00926-030 VMS DUT W RSW = 0.1V ISW CODE = 0x00 W IW = VDD/RNOMINAL VW -15V Figure 28. Gain vs. Frequency DUT A VOUT OP42 B 2.5V Figure 23. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) VMS2 +15V W VIN 00926-035 DUT B 0.1V ISW RW = [VMS1 - VMS2]/IW VSS TO VDD Figure 29. Incremental On Resistance Figure 24. Wiper Resistance NC V+ = VDD 10% PSRR (dB) = 20 LOG A W PSS (%/%) = B VMS% VDD DUT VDD VSS VDD% VMS 00926-032 VDD VMS DUT B 5V OFFSET BIAS VOUT 00926-033 OP279 B ICM VCM Figure 30. Common-Mode Leakage Current W OFFSET GND GND W NC Figure 25. Power Supply Sensitivity (PSS, PSRR) A A Figure 26. Inverting Gain Rev. C | Page 11 of 20 00926-037 VA V+ 00926-036 VMS1 00926-031 B AD5241/AD5242 THEORY OF OPERATION The AD5241/AD5242 provide a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. The terms VR, RDAC, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. Figure 31 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string is not accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. To program the VR settings, refer to the Digital Interface section. Both parts have an internal power-on preset that places the wiper in midscale during power-on that simplifies the fault condition recovery at power-up. In addition, the shutdown pin (SHDN) of AD5241/AD5242 places the RDAC in an almost zero power consumption state where Terminal A is open circuited and Wiper W is connected to Terminal B, resulting in only leakage current being consumed in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part returns from shutdown, the stored VR setting is applied to the RDAC. The general equation determining the digitally programmed resistance between W and B is SHDN SWSHDN R N SW 2-1 R N SW 2-2 D x RAB + RW 256 (1) where: D is the decimal equivalent of the binary code between 0 and 255, which is loaded in the 8-bit RDAC register. RAB is the nominal end-to-end resistance. RW is the wiper resistance contributed by the on resistance of the internal switch. Again, if RAB = 10 k, Terminal A can be either open circuit or tied to W. Table 6 shows the RWB resistance based on the code set in the RDAC latch. A D7 D6 D5 D4 D3 D2 D1 D0 RWB(D) = Table 6. RWB (D) at Selected Codes for RAB = 10 k W R SW1 R SW0 RWB () 10021 Output State Full-scale (RWB - 1 LSB + RW) 128 1 0 5060 99 60 Midscale 1 LSB Zero-scale (wiper contact resistance) R RAB/2N B DIGITAL CIRCUITRY OMITTED FOR CLARITY Note that in the zero-scale condition, a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. 00926-022 RDAC LATCH AND DECODER D (DEC) 255 Figure 31. Equivalent RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B is available in 10 k, 100 k, and 1 M. The final two or three digits of the part number determine the nominal resistance value, for example, 10 k = 10, 100 k = 100, and 1 M = 1 M. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 k part is used; the first connection of the wiper starts at the B terminal for Data 0x00. Because there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between Terminal W and Terminal B. The second connection is the first tap point that corresponds to 99 (RWB = RAB/256 + RW = 39 + 60) for Data 0x01. The third connection is the next tap point representing 138 (39 x 2 + 60) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,021 [RAB - 1 LSB + RW]. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled resistance, RWA. When these terminals are used, Terminal B can be opened or tied to the wiper terminal. The minimum RWA resistance is for Data 0xFF and increases as the data loaded in the latch decreases in value. The general equation for this operation is RWA(D) = 256 - D x RAB + RW 256 (2) For RAB = 10 k, Terminal B can be either open circuit or tied to W. Table 7 shows the RWA resistance based on the code set in the RDAC latch. Table 7. RWA (D) at Selected Codes for RAB = 10 k D (DEC) RWA () Output State 255 128 1 0 99 5060 10021 10060 Full-scale Midscale 1 LSB Zero-scale Rev. C | Page 12 of 20 AD5241/AD5242 The typical distribution of the nominal resistance RAB from channel to channel matches within 1% for AD5242. Deviceto-device matching is process lot dependent, and it is possible to have 30% variation. Because the resistance element is processed in thin film technology, the change in RAB with temperature has no more than a 30 ppm/C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Unlike the polarity of VDD /VSS, which must be positive, voltage across terminal A to terminal B, terminal W to terminal A, and terminal W to terminal B can be at either polarity provided that VSS is powered by a negative supply. DIGITAL INTERFACE 2-Wire Serial Bus The AD5241/AD5242 are controlled via an I2C-compatible serial bus. The RDACs are connected to this bus as slave devices. Referring to Figure 3 and Figure 4, the first byte of AD5241/ AD5242 is a slave address byte. It has a 7-bit slave address and an R/W bit. The five MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow users to use up to four of these devices on one bus. The 2-wire, I2C serial bus protocol operates as follows: 1. If ignoring the effect of the wiper resistance for approximation, connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 positions of the potentiometer divider. Because AD5241/AD5242 can be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D ) = D 256 - D VA + VB 256 256 (3) which can be simplified to VW (D ) = D V AB + V B 256 2. (4) where D is the decimal equivalent of the binary code between 0 to 255 that is loaded in the 8-bit RDAC register. For a more accurate calculation, including the effects of wiper resistance, VW can be found as VW (D ) = R (D) RWB (D) V A + WA VB R AB R AB (5) where RWB(D) and RWA(D) can be obtained from Equation 1 and Equation 2. Operation of the digital potentiometer in divider mode results in a more accurate operation over temperature. Unlike rheostat mode, the output voltage is dependent on the ratio of the internal resistors, RWA and RWB, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/C. 3. Rev. C | Page 13 of 20 The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The following byte is the Frame 1, slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master reads from the slave device. If the R/W bit is low, the master writes to the slave device. A write operation contains an extra instruction byte more than the read operation. The Frame 2 instruction byte in write mode follows the slave address byte. The MSB of the instruction byte labeled A/B is the RDAC subaddress select. A low selects RDAC1 and a high selects RDAC2 for the dualchannel AD5242. Set A/B to low for the AD5241. The second MSB, RS, is the midscale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where RWA = RWB. The third MSB, SD, is a shutdown bit. A logic high on SD causes the RDAC to open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields almost a 0 rheostat mode or 0 V in potentiometer mode. This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low. The following two bits are O2 and O1. They are extra programmable logic outputs that users can use to drive other digital loads, logic gates, LED drivers, analog switches, and the like. The three LSBs are don't care (see Figure 4). After acknowledging the instruction byte, the last byte in write mode is the, Frame 3 data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 4). AD5241/AD5242 5. Unlike the write mode, the data byte follows immediately after the acknowledgment of the slave address byte in Frame 2 read mode. Data is transmitted over the serial bus in sequences of nine clock pulses (slightly different from the write mode, there are eight data bits followed by a no acknowledge Logic 1 bit in read mode). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 5). When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 4). In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, which goes high to establish a stop condition (see Figure 5). MULTIPLE DEVICES ON ONE BUS Figure 33 shows four AD5242 devices on the same serial bus. Each has a different slave address because the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C-compatible interface. Note, a device is addressed properly only if the bit information of AD0 and AD1 in the slave address byte matches with the logic inputs at the AD0 and AD1 pins of that particular device. LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE While most old systems can operate at one voltage, a new component may be optimized at another. When they operate the same signal at two different voltages, a proper method of level-shifting is needed. For instance, a 3.3 V E2PROM can be used to interface with a 5 V digital potentiometer. A level-shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 32 shows one of the techniques. M1 and M2 can be N-channel FETs (2N7002) or low threshold FDV301N if VDD falls below 2.5 V. A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte updates the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output is updated. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. If different instructions are needed, the write mode has to start a completely new sequence with a new slave address, instruction, and data bytes transferred again. Similarly, a repeated read function of the RDAC is also allowed. VDD = 3.3V VDD = 5V RP RP S SDA1 RP G D SDA2 M1 G S SCL1 3.3V E2PROM AD5242 Figure 32. Level-Shift for Different Voltage Devices Operation 5V RP SDA MASTER SCL SDA SCL VDD SDA SCL VDD SDA SCL AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD5242 AD5242 AD5242 Figure 33. Multiple AD5242 Devices on One Bus Rev. C | Page 14 of 20 AD5242 00926-023 VDD SCL2 5V Specific to the AD5242 dual-channel device, the channel of interest is the one that was previously selected in the write mode. In addition, to read both RDAC values consecutively, users have to perform two write-read cycles. For example, users may first specify the RDAC1 subaddress in write mode (it is not necessary to issue the data byte and stop condition), and then change to read mode to read the RDAC1 value. To continue reading the RDAC2 value, users have to switch back to write mode, specify the subaddress, and then switch once again to read mode to read the RDAC2 value. It is not necessary to issue the write mode data byte or the first stop condition for this operation. Users should refer to Figure 4 and Figure 5 for the programming format. SDA SCL D M2 READBACK RDAC VALUE RP RP 00926-024 4. AD5241/AD5242 ADDITIONAL PROGRAMMABLE LOGIC OUTPUT SHUTDOWN FUNCTION The AD5241/AD5242 feature additional programmable logic outputs, O1 and O2, that can be used to drive digital load, analog switches, and logic gates. They can also be used as a self-contained shutdown preset to Logic 0 that is further explained in the Shutdown Function section. O1 and O2 default to Logic 0 during power-up. The logic states of O1 and O2 can be programmed in Frame 2 under the write mode (see Figure 4). Figure 34 shows the output stage of O1, which employs large P-channel and Nchannel MOSFETs in push-pull configuration. As shown in Figure 34, the output is equal to VDD or VSS, and these logic outputs have adequate current driving capability to drive milliamperes of load. Shutdown can be activated by strobing the SHDN pin or programming the SD bit in the write mode instruction byte (see Table 2). If the RDAC Register 1 or RDAC Register 2 (AD5242 only) is placed in shutdown mode by the software, SD bit, the part returns the wiper to its prior position when a new command is received. VDD MP IN 1 2 In addition, shutdown can be implemented with the device digital output, as shown in Figure 35. In this configuration, the device is shutdown during power-up but users are allowed to program the device. Thus, when O1 is programmed high, the device exits shutdown mode and responds to the new setting. This self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, and it does not add extra components. O1 O1 SDA SCL Users can also activate O1 and O2 in the following three different ways without affecting the wiper settings: 1. 2. 3. Start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, stop. Complete the write cycle with stop, then start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, stop. Do not complete the write cycle by not issuing the stop, then start, slave address byte, acknowledge, instruction byte with O1 and O2 specified, acknowledge, stop. Figure 35. Shutdown by Internal Logic Output, O1 340 LOGIC VSS Figure 36. ESD Protection of Digital Pins A,B,W VSS All digital inputs are protected with a series input resistor and the parallel Zener ESD structures shown in Figure 36. This applies to the digital input pins, SDA, SCL, and SHDN. Rev. C | Page 15 of 20 00926-026 Figure 34. Output Stage of Logic Output, O1 00926-027 VSS RPD 00926-028 MN 00926-025 SHDN O1 DATA IN FRAME 2 OF WRITE MODE Figure 37. ESD Protection of Resistor Terminals AD5241/AD5242 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 0.30 0.19 0.75 0.60 0.45 8 0 SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 39. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. C | Page 16 of 20 060606-A 4.00 (0.1575) 3.80 (0.1496) AD5241/AD5242 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC 0.20 0.09 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) Figure 41. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. C | Page 17 of 20 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. AD5241/AD5242 ORDERING GUIDE Model 1, 2 No. of Channels End-to-End RAB Temperature Range Package Description Package Option AD5241BR10 AD5241BR10-REEL7 AD5241BRZ10 AD5241BRZ10-RL7 AD5241BRU10 AD5241BRU10-REEL7 AD5241BRUZ10 AD5241BRUZ10-R7 AD5241BR100 AD5241BR100-REEL7 AD5241BRZ100 AD5241BRZ100-RL7 AD5241BRU100 AD5241BRU100-REEL7 AD5241BRUZ100 AD5241BRUZ100-R7 AD5241BR1M AD5241BRZ1M AD5241BRZ1M-REEL AD5241BRU1M AD5241BRU1M-REEL7 AD5241BRUZ1M AD5241BRUZ1M-R7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 1 M 1 M 1 M 1 M 1 M 1 M 1 M -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 AD5242BR10 AD5242BR10-REEL7 AD5242BRZ10 AD5242BRZ10-REEL7 AD5242BRU10 AD5242BRU10-REEL7 AD5242BRUZ10 AD5242BRUZ10-RL7 AD5242BR100 AD5242BR100-REEL7 AD5242BRZ100 AD5242BRZ100-REEL7 AD5242BRU100 AD5242BRU100-REEL7 AD5242BRUZ100 AD5242BRUZ100-RL7 AD5242BR1M AD5242BRZ1M AD5242BRU1M AD5242BRU1M-REEL7 AD5242BRUZ1M AD5242BRUZ1M-REEL7 EVAL-AD5242EBZ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 1 M 1 M 1 M 1 M 1 M 1 M Evaluation Board -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP R-16 R-16 R-16 R-16 RU-16 RU-16 RU-16 RU-16 R-16 R-16 R-16 R-16 RU-16 RU-16 RU-16 RU-16 R-16 R-16 R-16 RU-16 RU-16 RU-16 1 2 The AD5241/AD5242 die size is 69 mil x 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5,495,245 applies. Z = RoHS Compliant Part. Rev. C | Page 18 of 20 AD5241/AD5242 NOTES Rev. C | Page 19 of 20 AD5241/AD5242 NOTES (c)2001-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00926-0-12/09(C) Rev. C | Page 20 of 20