CONNECTION DIAGRAM
8-Pin Plastic DIP, Cerdip and SOIC
OUT1
–IN1
+IN1
V–
V+
OUT2
–IN2
+IN2
1
2
3
4
8
7
6
5
AD822
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Single Supply, Rail-to-Rail
Low Power FET-Input Op Amp
AD822
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
TRUE SINGLE SUPPLY OPERATION
Output Swings Rail to Rail
Input Voltage Range Extends Below Ground
Single Supply Capability from +3 V to +36 V
Dual Supply Capability from 61.5 V to 618 V
HIGH LOAD DRIVE
Capacitive Load Drive of 350 pF, G = 1
Minimum Output Current of 15 mA
EXCELLENT AC PERFORMANCE FOR LOW POWER
800 mA Max Quiescent Current per Amplifier
Unity Gain Bandwidth: 1.8 MHz
Slew Rate of 3.0 V/ms
GOOD DC PERFORMANCE
800 mV Max Input Offset Voltage
2 mV/8C Typ Offset Voltage Drift
25 pA Max Input Bias Current
LOW NOISE
13 nV/√Hz @ 10 kHz
NO PHASE INVERSION
APPLICATIONS
Battery Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 14-Bit Data Acquisition Systems
Medical Instrumentation
Low Power References and Regulators
PRODUCT DESCRIPTION
The AD822 is a dual precision, low power FET input op
amp that can operate from a single supply of +3.0 V to 36 V,
or dual supplies of ±1.5 V to ±18 V. It has true single supply
capability with an input voltage range extending below the
negative rail, allowing the AD822 to accommodate input signals
below ground in the single supply mode. Output voltage swing
extends to within 10 mV of each rail providing the maximum
output dynamic range.
Offset voltage of 800 µV max, offset voltage drift of 2 µV/°C,
input bias currents below 25 pA and low input voltage noise
provide dc precision with source impedances up to a Gigaohm.
1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz and
3 V/µs slew rate are provided with a low supply current of
800 µA per amplifier. The AD822 drives up to 350 pF of direct
capacitive load as a follower, and provides a minimum output
current of 15 mA. This allows the amplifier to handle a wide
range of load conditions. This combination of ac and dc
performance, plus the outstanding load drive capability, results
in an exceptionally versatile amplifier for the single supply user.
The AD822 is available in four performance grades. The A and
B grades are rated over the industrial temperature range of
–40°C to +85°C. There is also a 3 volt grade—the AD822A-3V,
rated over the industrial temperature range. The mil grade is
rated over the military temperature range of –55°C to +125°C
and is available processed on standard military drawing.
The AD822 is offered in three varieties of 8-pin package: plastic
DIP, hermetic cerdip and surface mount (SOIC) as well as die
form.
10
90
100
0%
1V
1V 20µ
s
1V
5V
V
OUT
0V
(GND)
Gain of +2 Amplifier; V
S
= +5, 0, V
IN
= 2.5 V Sine Centered
at 1.25 Volts, R
L
= 100 k
Ω
Input Voltage Noise vs. Frequency
100
10
110 100 10k1k
INPUT VOLTAGE NOISE – nV/√Hz
FREQUENCY – Hz
REV. A
–2–
AD822–SPECIFICATIONS
(VS = 0, 5 volts @ TA = +258C, VCM = 0 V, VOUT = 0.2 V unless otherwise noted)
AD822A AD822B AD822S
1
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 0.1 0.8 mV
Max Offset over Temperature 0.5 1.2 0.5 0.9 0.5 mV
Offset Drift 2 2 2 µV/°C
Input Bias Current V
CM
= 0 V to 4 V 2 25 2 10 2 25 pA
at T
MAX
0.5 5 0.5 2.5 0.5 nA
Input Offset Current 2 20 2 10 2 20 pA
at T
MAX
0.5 0.5 1.5 nA
Open-Loop Gain V
O
= 0.2 V to 4 V
R
L
= 100 k 500 1000 500 1000 500 1000 V/mV
T
MIN
to T
MAX
400 400 V/mV
R
L
= 10 k 80 150 80 150 80 150 V/mV
T
MIN
to T
MAX
80 80 V/mV
R
L
= 1 k 15 30 15 30 15 30 V/mV
T
MIN
to T
MAX
10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 2 µV p-p
f = 10 Hz 25 25 25 nV/√Hz
f = 100 Hz 21 21 21 nV/√Hz
f = 1 kHz 16 16 16 nV/√Hz
f = 10 kHz 13 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 18 fA p-p
f = 1 kHz 0.8 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 k to 2.5 V
f = 10 kHz V
O
= 0.25 V to 4.75 V –93 –93 –93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.8 1.8 1.8 MHz
Full Power Response V
O
p-p = 4.5 V 210 210 210 kHz
Slew Rate 3 3 3 V/µs
Settling Time
to 0.1% V
O
= 0.2 V to 4.5 V 1.4 1.4 1.4 µs
to 0.01% 1.8 1.8 1.8 µs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 1.6 mV
Max Offset Over Temperature 1.6 1.3 mV
Offset Drift 3 3 µV/°C
Input Bias Current 20 10 20 pA
Crosstalk @ f = 1 kHz R
L
= 5 kΩ–130 –130 –130 dB
f = 100 kHz –93 –93 –93 dB
INPUT CHARACTERISTICS
Common-Mode Voltage Range
2
–0.2 4 –0.2 4 –0.2 4 V
T
MIN
to T
MAX
–0.2 4 –0.2 4 V
CMRR V
CM
= 0 V to +2 V 66 80 69 80 66 80 dB
T
MIN
to T
MAX
66 66 dB
Input Impedance
Differential 10
13
||0.5 10
13
||0.5 10
13
||0.5 Ω||pF
Common Mode 10
13
||2.8 10
13
||2.8 10
13
||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
3
V
OL
–V
EE
I
SINK
= 20 µA 575757mV
T
MIN
to T
MAX
10 10 mV
V
CC
–V
OH
I
SOURCE
= 20 µA 1014 1014 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL
–V
EE
I
SINK
= 2 mA 40 55 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
V
CC
–V
OH
I
SOURCE
= 2 mA 80 110 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
V
OL
–V
EE
I
SINK
= 15 mA 300 500 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC
–V
OH
I
SOURCE
= 15 mA 800 1500 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 15 15 15 mA
T
MIN
to T
MAX
12 12 mA
Capacitive Load Drive 350 350 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
1.24 1.6 1.24 1.6 1.24 mA
Power Supply Rejection V
S
+ = 5 V to 15 V 70 80 66 80 70 80 dB
T
MIN
to T
MAX
70 66 dB
(VS = 65 volts @ TA = +258C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
AD822A AD822B AD822S
1
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 0.1 mV
Max Offset over Temperature 0.5 1.5 0.5 1 0.5 mV
Offset Drift 2 2 2 µV/°C
Input Bias Current V
CM
= –5 V to 4 V 2 25 2 10 2 25 pA
at T
MAX
0.5 5 0.5 2.5 0.5 nA
Input Offset Current 2 20 2 10 2 pA
at T
MAX
0.5 0.5 1.5 nA
Open-Loop Gain V
O
= –4 V to 4 V
R
L
= 100 k 400 1000 400 1000 400 1000 V/mV
T
MIN
to T
MAX
400 400 V/mV
R
L
= 10 k 80 150 80 150 80 150 V/mV
T
MIN
to T
MAX
80 80 V/mV
R
L
= 1 k 20 30 20 30 20 30 V/mV
T
MIN
to T
MAX
10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 2 µV p-p
f = 10 Hz 25 25 25 nV/√Hz
f = 100 Hz 21 21 21 nV/√Hz
f = 1 kHz 16 16 16 nV/√Hz
f = 10 kHz 13 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 18 fA p-p
f = 1 kHz 0.8 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 k
f = 10 kHz V
O
= ±4.5 V –93 –93 –93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 1.9 MHz
Full Power Response V
O
p-p = 9 V 105 105 105 kHz
Slew Rate 3 3 3 V/µs
Settling Time
to 0.1% V
O
= 0 V to ±4.5 V 1.4 1.4 1.4 µs
to 0.01% 1.8 1.8 1.8 µs
MATCHING CHARACTERISTICS
Initial Offset 1.0 0.5 1.6 mV
Max Offset Over Temperature 3 2 2 mV
Offset Drift 3 3 µV/°C
Input Bias Current 25 10 25 pA
Crosstalk @ f = 1 kHz R
L
= 5 kΩ–130 –130 –130 dB
f = 100 kHz –93 –93 –93 dB
INPUT CHARACTERISTICS
Common-Mode Voltage Range
2
–5.2 4 –5.2 4 –5.2 4 V
T
MIN
to T
MAX
–5.2 4 –5.2 4 V
CMRR V
CM
= –5 V to +2 V 66 80 69 80 66 80 dB
T
MIN
to T
MAX
66 66 dB
Input Impedance
Differential 10
13
||0.5 10
13
||0.5 10
13
||0.5 Ω||pF
Common Mode 10
13
||2.8 10
13
||2.8 10
13
||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
3
V
OL
–V
EE
I
SINK
= 20 µA 575757mV
T
MIN
to T
MAX
10 10 mV
V
CC
–V
OH
I
SOURCE
= 20 µA 1014 1014 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL
–V
EE
I
SINK
= 2 mA 40 55 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
V
CC
–V
OH
I
SOURCE
= 2 mA 80 110 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
V
OL
–V
EE
I
SINK
= 15 mA 300 500 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC
–V
OH
I
SOURCE
= 15 mA 800 1500 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 15 15 15 mA
T
MIN
to T
MAX
12 12 mA
Capacitive Load Drive 350 350 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
1.3 1.6 1.3 1.6 1.3 mA
Power Supply Rejection V
S
+ = 5 V to 15 V 70 80 66 80 70 80 dB
T
MIN
to T
MAX
70 66 dB
AD822
REV. A –3–
AD822A AD822B AD822S
1
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
DC PERFORMANCE
Initial Offset 0.4 2 0.3 1.5 0.4 2.0 mV
Max Offset over Temperature 0.5 3 0.5 2.5 0.5 mV
Offset Drift 2 2 2 µV/°C
Input Bias Current V
CM
= 0 V 2 25 2 12 2 25 pA
V
CM
= –10 V 40 40 40 pA
at T
MAX
V
CM
= 0 V 0.5 5 0.5 2.5 0.5 nA
Input Offset Current 2 20 2 12 2 20 pA
at T
MAX
0.5 0.5 1.5 nA
Open-Loop Gain V
O
= +10 V to –10 V
R
L
= 100 k 500 2000 500 2000 500 2000 V/mV
T
MIN
to T
MAX
500 500 V/mV
R
L
= 10 k 100 500 100 500 150 400 V/mV
T
MIN
to T
MAX
100 100 V/mV
R
L
= 1 k 30 45 30 45 30 45 V/mV
T
MIN
to T
MAX
20 20 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 2 µV p-p
f = 10 Hz 25 25 25 nV/√Hz
f = 100 Hz 21 21 21 nV/√Hz
f = 1 kHz 16 16 16 nV/√Hz
f = 10 kHz 13 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 18 fA p-p
f = 1 kHz 0.8 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 k
f = 10 kHz V
O
= ±10 V –85 –85 –85 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 1.9 MHz
Full Power Response V
O
p-p = 20 V 45 45 45 kHz
Slew Rate 3 3 3 V/µs
Settling Time
to 0.1% V
O
= 0 V to ±10 V 4.1 4.1 4.1 µs
to 0.01% 4.5 4.5 4.5 µs
MATCHING CHARACTERISTICS
Initial Offset 3 2 0.8 mV
Max Offset Over Temperature 4 2.5 1.0 mV
Offset Drift 3 3 µV/°C
Input Bias Current 25 12 25 pA
Crosstalk @ f = 1 kHz R
L
= 5 kΩ–130 –130 –130 dB
f = 100 kHz –93 –93 –93 dB
INPUT CHARACTERISTICS
Common-Mode Voltage Range
2
–15.2 14 –15.2 14 –15.2 14 V
T
MIN
to T
MAX
–15.2 14 –15.2 14 V
CMRR V
CM
= –15 V to 12 V 70 80 74 90 70 90 dB
T
MIN
to T
MAX
70 74 dB
Input Impedance
Differential 10
13
||0.5 10
13
||0.5 10
13
||0.5 Ω||pF
Common Mode 10
13
||2.8 10
13
||2.8 10
13
||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
3
V
OL
–V
EE
I
SINK
= 20 µA 575757mV
T
MIN
to T
MAX
10 10 mV
V
CC
–V
OH
I
SOURCE
= 20 µA 1014 1014 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL
–V
EE
I
SINK
= 2 mA 40 55 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
V
CC
–V
OH
I
SOURCE
= 2 mA 80 110 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
V
OL
–V
EE
I
SINK
= 15 mA 300 500 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC
–V
OH
I
SOURCE
= 15 mA 800 1500 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 20 20 20 mA
T
MIN
to T
MAX
15 15 mA
Capacitive Load Drive 350 350 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
1.4 1.8 1.4 1.8 1.4 mA
Power Supply Rejection V
S
+ = 5 V to 15 V 70 80 70 80 70 80 dB
T
MIN
to T
MAX
70 70 dB
AD822–SPECIFICATIONS
(VS = 615 volts @ TA = +258C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
REV. A
–4–
AD822
REV. A –5–
(VS = 0, 3 volts @ TA = +258C, VCM = 0 V, VOUT = 0.2 V unless otherwise noted)
AD822A-3 V
Parameter Conditions Min Typ Max Units
DC PERFORMANCE
Initial Offset 0.2 1 mV
Max Offset over Temperature 0.5 1.5 mV
Offset Drift 1 µV/°C
Input Bias Current V
CM
= 0 V to +2 V 2 25 pA
at T
MAX
0.5 5 nA
Input Offset Current 220 pA
at T
MAX
0.5 nA
Open-Loop Gain V
O
= 0.2 V to 2 V
R
L
= 100 k 300 1000 V/mV
T
MIN
to T
MAX
300 V/mV
R
L
= 10 k 60 150 V/mV
T
MIN
to T
MAX
60 V/mV
R
L
= 1 k 10 30 V/mV
T
MIN
to T
MAX
8 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 µV p-p
f = 10 Hz 25 nV/√Hz
f = 100 Hz 21 nV/√Hz
f = 1 kHz 16 nV/√Hz
f = 10 kHz 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 fA p-p
f = 1 kHz 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 k to 1.5 V
f = 10 kHz V
O
= ±1.25 V –92 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.5 MHz
Full Power Response V
O
p-p = 2.5 V 240 kHz
Slew Rate 3V/µs
Settling Time
to 0.1% V
O
= 0.2 V to 2.5 V 1 µs
to 0.01% 1.4 µs
MATCHING CHARACTERISTICS
Initial Offset 1mV
Max Offset Over Temperature 2mV
Offset Drift 2 µV/°C
Input Bias Current 10 pA
Crosstalk @ f = 1 kHz R
L
= 5 kΩ–130 dB
f = 100 kHz –93 dB
INPUT CHARACTERISTICS
Common-Mode Voltage Range
2
–0.2 2 V
T
MIN
to T
MAX
–0.2 2 V
CMRR V
CM
= 0 V to +1 V 60 74 dB
T
MIN
to T
MAX
60 dB
Input Impedance
Differential 10
13
||0.5 Ω||pF
Common Mode 10
13
||2.8 Ω||pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
3
V
OL
–V
EE
I
SINK
= 20 µA57mV
T
MIN
to T
MAX
10 mV
V
CC
–V
OH
I
SOURCE
= 20 µA1014mV
T
MIN
to T
MAX
20 mV
V
OL
–V
EE
I
SINK
= 2 mA 40 55 mV
T
MIN
to T
MAX
80 mV
V
CC
–V
OH
I
SOURCE
= 2 mA 80 110 mV
T
MIN
to T
MAX
160 mV
V
OL
–V
EE
I
SINK
= 10 mA 200 400 mV
T
MIN
to T
MAX
400 mV
V
CC
–V
OH
I
SOURCE
= 10 mA 500 1000 mV
T
MIN
to T
MAX
1000 mV
Operating Output Current 15 mA
T
MIN
to T
MAX
12 mA
Capacitive Load Drive 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
1.24 1.6 mA
Power Supply Rejection V
S
+ = 3 V to 15 V 70 80 dB
T
MIN
to T
MAX
70 dB
–6–
AD822
REV. A
NOTES
1
See standard military drawing for 883B specifications.
2
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+V
S
– 1 V) to +V
S
.
Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply.
3
V
OL
–V
EE
is defined as the difference between the lowest possible output voltage (V
OL
) and the minus voltage supply rail (V
EE
).
V
CC
–V
OH
is defined as the difference between the highest possible output voltage (V
OH
) and the positive supply voltage (V
CC
).
Specifications subject to change without notice.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD822 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
Plastic DIP (N) . . . . . . . . . . . . . . Observe Derating Curves
Cerdip (Q) . . . . . . . . . . . . . . . . . . Observe Derating Curves
SOIC (R) . . . . . . . . . . . . . . . . . . . Observe Derating Curves
Input Voltage . . . . . . . . . . . . . . (+V
S
+ 0.2 V) to –(20 V + V
S
)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (R) . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD822A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD822S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +260°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-Pin Plastic DIP Package: θ
JA
= 90°C/Watt
8-Pin Cerdip Package: θ
JA
= 110°C/Watt
8-Pin SOIC Package: θ
JA
= 160°C/Watt
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD822 is
limited by the associated rise in junction temperature. For plastic
packages, the maximum safe junction temperature is 145°C. For
the cerdip packages, the maximum junction temperature is 175°C.
If these maximums are exceeded momentarily, proper circuit
operation will be restored as soon as the die temperature is
reduced. Leaving the device in the “overheated” condition for
an extended period can result in device burnout. To ensure
proper operation, it is important to observe the derating curves
shown in Figure 24.
While the AD822 is internally short circuit protected, this may not
be sufficient to guarantee that the maximum junction temperature
is not exceeded under all conditions. With power supplies ±12
volts (or less) at an ambient temperature of +25°C or less, if the
output node is shorted to a supply rail, then the amplifier will not
be destroyed, even if this condition persists for an extended period.
ORDERING GUIDE
Temperature Package Package
M
odel
1
Range Description Option
AD822AN –40°C to +85°C 8-Pin Plastic N-8
Mini-DIP
AD822BN –40°C to +85°C 8-Pin Plastic N-8
Mini-DIP
AD822AR –40°C to +85°C 8-Pin SOIC R-8
AD822BR –40°C to +85°C 8-Pin SOIC R-8
AD822AR-3V –40°C to +85°C 8-Pin SOIC R-8
AD822AN-3V –40°C to +85°C 8-Pin Plastic N-8
Mini-DIP
AD822A Chips –40°C to +85°CDie
Standard Military
Drawing
2
–55°C
to +125°C 8-Pin Cerdip Q-8
NOTES
1
Spice model is available on ADI Model Disc.
2
Contact factory for availability.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm ).
AD822–SPECIFICATIONS
0.5
50
00
30
10
–0.4
20
–0.5
40
0.40.30.20.1–0.1–0.2–0.3 OFFSET VOLTAGE – mV
NUMBER OF UNITS
V
S
= 0V, 5V
60
70
Figure 1. Typical Distribution of Offset Voltage (390 Units)
OFFSET VOLTAGE DRIFT – µV/°C
% IN BIN
16
010
4
2
–10–12
8
6
10
12
14
86420–2–4–6–8
VS = ±5V
VS = ±15V
Figure 2. Typical Distribution of Offset Voltage Drift
(100 Units)
50
010
15
5
1
10
0
30
20
25
35
40
45
98765432 INPUT BIAS CURRENT – pA
NUMBER OF UNITS
Figure 3. Typical Distribution of Input Bias Current
(213 Units)
Typical Characteristics–AD822
REV. A –7–
INPUT BIAS CURRENT – pA
5
0
–5 –5 –4 543210–1–2–3 COMMON-MODE VOLTAGE – V
V
S
= ±5V
V
S
= 0V, +5V AND ±5V
Figure 4. Input Bias Current vs. Common-Mode Voltage;
V
S
= +5 V, 0 V and V
S
=
±
5V
INPUT BIAS CURRENT – pA
COMMON-MODE VOLTAGE – V
1k
10
0.1–16 –12 1612840–4–8
100
1
Figure 5. Input Bias Current vs. Common-Mode Voltage;
V
S
=
±
15 V
100k
100
0.1 20 40 1401201008060
1k
10k
1
10
TEMPERATURE – °C
INPUT BIAS CURRENT – pA
Figure 6. Input Bias Current vs. Temperature; V
S
= 5 V,
V
CM
= 0
10M
100k
10k100 1k 100k10k
1M
LOAD RESISTANCE – Ω
OPEN-LOOP GAIN – V/V
VS = ±15V
VS = 0V, 5V
VS = 0V, 3V
Figure 7. Open-Loop Gain vs. Load Resistance
140
10M
100k
10k
1M
–60 –40 120100806040200–20 TEMPERATURE – °C
OPEN-LOOP GAIN – V/V
V
S
= ±15V
V
S
= 0V, 5V
V
S
= ±15V
V
S
= 0V, 5V
V
S
= ±15V
V
S
= 0V, 5V
R
L
= 100kΩ
R
L
= 10kΩ
R
L
= 600Ω
Figure 8. Open-Loop Gain vs. Temperature
300
–300 16
0
–200
–12
–100
–16
200
100
1240–4 8–8 OUTPUT VOLTAGE – V
INPUT VOLTAGE – µV
RL = 100kΩ
RL = 10kΩ
RL = 600Ω
Figure 9. Input Error Voltage vs. Output Voltage for
Resistive Loads
AD822–Typical Characteristics
REV. A
–8–
40
–40 0300
20
–20
60
0
180 240120
POS
RAIL
OUTPUT VOLTAGE FROM SUPPLY RAILS – mV
INPUT VOLTAGE – µV
R
L
= 2kΩ
R
L
= 20kΩ
R
L
= 100kΩ
POS RAIL
NEG RAIL
NEG RAIL
NEG RAIL
POS RAIL
Figure 10. Input Error Voltage with Output Voltage within
300 mV of Either Supply Rail for Various Resistive Loads;
V
S
=
±
5V
1k
100
110 10k1k100
1FREQUENCY – Hz
10
INPUT VOLTAGE NOISE – nV/
√
Hz
Figure 11. Input Voltage Noise vs. Frequency
–40
–90
–110100 1k 100k10k
–60
–100
–80
–70
–50
FREQUENCY – Hz
THD – dB
R
L
= 10kΩ
A
CL
= –1
V
S
= ±15V; V
OUT
= 20V
p-p
V
S
= ±5V; V
OUT
= 9V
p-p
V
S
= 0V, 5V; V
OUT
= 4.5V
p-p
V
S
= 0V, 3V; V
OUT
= 2.5V
p-p
Figure 12. Total Harmonic Distortion vs. Frequency
AD822
REV. A –9–
50
010 100 10M1M100k10k1k
60
70
80
90
10
20
30
40
FREQUENCY – Hz
COMMON-MODE REJECTION – dB
V
S
= ±15V
V
S
= 0V, 5V
V
S
= 0V, 3V
Figure 16. Common-Mode Rejection vs. Frequency
–55°C
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – Volts
COMMON-MODE ERROR VOLTAGE – mV
5
03
3
1
2
–1
4
210
NEGATIVE
RAIL POSITIVE
RAIL
–55°C
+125°C
+25°C
+125°C
Figure 17. Absolute Common-Mode Error vs. Common-
Mode Voltage from Supply Rails (V
S
– V
CM
)
1000
100
0
0.001 0.01 1001010.1
10
LOAD CURRENT – mA
OUTPUT SATURATION VOLTAGE – mV
V
S
– V
OH
V
OL
– V
S
Figure 18. Output Saturation Voltage vs. Load Current
100
40
–20 10 100 10M1M100k10k1k
60
80
0
20
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
R
L
= 2kΩ
C
L
= 100pF
100
40
–20
60
80
0
20
PHASE MARGIN IN DEGREES
GAIN
PHASE
Figure 13. Open-Loop Gain and Phase Margin vs.
Frequency
1k
100
0.01100 1k 10M1M100k10k
10
1
0.1
FREQUENCY – Hz
OUTPUT IMPEDANCE – Ω
ACL = +1
VS = ±15V
Figure 14. Output Impedance vs. Frequency
+16
–16 5.0
–8
–12
1.00.0
0
–4
+4
+8
+12
4.03.02.0
SETTLING TIME – µs
OUTPUT SWING FROM 0 TO ±Volts
1%
1%
0.01%0.1% ERROR
Figure 15. Output Swing and Error vs. Settling Time
1000
100
1–60 –40 140120100806040200–20
10
TEMPERATURE – °C
OUTPUT SATURATION VOLTAGE – mV
I
SOURCE
= 10mA
I
SINK
= 10mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SOURCE
= 10µA
I
SINK
= 10µA
Figure 19. Output Saturation Voltage vs. Temperature
TEMPERATURE – °C
SHORT CIRCUIT CURRENT LIMIT – mA
80
0140
20
10
–40–60
40
30
50
60
70
120100806040200–20
VS = ±15V
VS = ±15V
VS = 0V, 5V
VS = 0V, 3V
VS = 0V, 5V VS = 0V, 3V
–OUT
+
–
–
+
+
Figure 20. Short Circuit Current Limit vs. Temperature
TOTAL SUPPLY VOLTAGE – Volts
QUIESCENT CURRENT – µA
1600
036
400
200
40
800
600
1000
1200
1400
3028242016128
T = +125°C
T = +25°C
T = –55°C
Figure 21. Quiescent Current vs. Supply Voltage vs.
Temperature
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
60
010 100 10M1M100k10k1k
30
90
80
20
50
70
10
40
100
–PSRR
+PSRR
Figure 22. Power Supply Rejection vs. Frequency
FREQUENCY – Hz
OUTPUT VOLTAGE – V
30
15
010k 100k 10M1M
10
5
20
25
VS = ±15V
VS = 0V, 5V
VS = 0V ,3V
RL = 2k
Figure 23. Large Signal Frequency Response
2.4
0.4
1.0
0.6
–40
0.8
–60
1.6
1.2
1.4
1.8
2.0
2.2
1401201008060400–20
TOTAL POWER DISSIPATION – Watts
20
AMBIENT TEMPERATURE –
°
C
8-PIN CERDIP
(HERMETIC)
8-PIN MINI-DIP
(PLASTIC)
8-PIN SOIC
(PLASTIC)
(PLASTIC) T
JMAX
= 145
°
C
(HERMETIC) T
JMAX
= 175
°
C
Figure 24. Maximum Power Dissipation vs. Temperature
for Plastic and Hermetic Packages
AD822–Typical Characteristics
REV. A–10–
AD822
REV. A –11–
FREQUENCY – Hz
CROSSTALK – dB
–70
–140 1M
–110
–130
1k
–120
300
–80
–100
–90
300k100k30k10k3k
Figure 25. Crosstalk vs. Frequency
–V
S
+V
S
V
IN
R
L
100pF V
OUT
4
0.01µF
0.01µF
1/2
AD822
8
Figure 26. Unity-Gain Follower
10
90
100
0%
10µs5V
Figure 27. 20 V p-p, 25 kHz Sine Wave Input; Unity Gain
Follower; R
L
= 600
Ω
, V
S
=
±
15 V
+V
S
2
3
81
0.1µF
1/2
AD822
1µF
20V p-p
V
IN
1/2
AD822
5kΩ5kΩ
6
5
7
20kΩ
V
OUT
2.2kΩ
0.1µF1µF
–V
S
CROSSTALK = 20 LOG V
OUT
10V
IN
Figure 28. Crosstalk Test Circuit
10
90
100
0%
5µs5V
Figure 29. Large Signal Response Unity Gain Follower;
V
S
=
±
15 V, R
L
= 10 k
Ω
10
90
100
0%
500ns10mV
Figure 30. Small Signal Response Unity Gain Follower;
V
S
=
±
15 V, R
L
= 10 k
Ω
–12–
AD822
REV. A
10
90
100
0%
2µs1V
GND
Figure 31. V
S
= +5 V, 0 V; Unity Gain Follower Response
to 0 V to 4 V Step
+V
S
V
IN
R
L
100pF V
OUT
8
4
0.01µF
1/2
AD822
Figure 32. Unity Gain Follower
10k 20k
+V
S
V
IN
R
L
100pF
V
OUT
8
4
0.01µF
1/2
AD822
Figure 33. Gain of Two Inverter
10
90
100
0%
2µs1V
GND
Figure 34. V
S
= +5 V, 0 V; Unity Gain Follower Response
to 0 V to 5 V Step
10
90
100
0%
2µs10mV
GND
Figure 35. V
S
= +5 V, 0 V; Unity Gain Follower Response,
to 40 mV Step Centered 40 mV Above Ground, R
L
= 10 k
Ω
10
90
100
0%
2µs
10mV
GND
Figure 36. V
S
= +5 V, 0 V; Gain of Two Inverter Response
to 20 mV Step, Centered 20 mV Below Ground, R
L
= 10 k
Ω
AD822
REV. A –13–
10
90
100
0%
1V
GND
2µs
Figure 37. V
S
= +5 V, 0 V; Gain of Two Inverter Response
to 2.5 V Step Centered –1.25 V Below Ground, R
L
= 10 k
Ω
10
90
100
0%
10µs500mV
GND
Figure 38. V
S
= 3 V, 0 V; Gain of Two Inverter, V
IN
= 1.25 V,
25 kHz, Sine Wave Centered at –0.75 V, R
L
= 600
Ω
90
100
10
0%
1V
1V 2µs
10
90
100
0%
1V
1V 10µs
1V
+V
S
GND
GND
+5V
V
IN
R
P
V
OUT
Figure 39. (a) Response with R
P
= 0; V
IN
from 0 to +V
S
(b) V
IN
= 0 to +V
S
+ 200 mV
V
OUT
= 0 to +V
S
R
P
= 49.9 k
Ω
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD822, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –V
S
to 1 V
less than +V
S
. Driving the input voltage closer to the positive
rail will cause a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figures 31 and
34) and increased common-mode voltage error as illustrated in
Figure 17.
The AD822 does not exhibit phase reversal for input voltages
up to and including +V
S
. Figure 39a shows the response of an
AD822 voltage follower to a 0 V to +5 V (+V
S
) square wave
input. The input and output arc superimposed. The output
tracks the input up to +V
S
without phase reversal. The reduced
bandwidth above a 4 V input causes the rounding of the output
wave form. For input voltages greater than +V
S
, a resistor in
series with the AD822’s noninverting input will prevent phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 39b.
Since the input stage uses n-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +V
S
– 0.4 V, the input current will reverse direction as
internal device junctions become forward biased. This is
illustrated in Figure 4.
A current limiting resistor should be used in series with the
input of the AD822 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD822 when ±V
S
= 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
Input voltages less than –V
S
are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In
addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
a
b.
–14–
AD822
REV. A
The AD822 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 11). This noise performance, along with the
AD822’s low input current and current noise means that the
AD822 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 40.
100k
0.1 10G
100
1
100k
10
10k
10k
1k
1G100M10M1M
SOURCE IMPEDANCE – Ω
INPUT VOLTAGE NOISE – µV
RMS
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
RESISTOR JOHNSON
NOISE
AMPLIFIER GENERATED
NOISE
1kHz
10Hz
Figure 40. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD822 s unique bipolar rail-to-rail output stage swings
within 5 mV of the minus supply and 10 mV of the positive
supply with no external resistive load. The AD822’s
approximate output saturation resistance is 40 Ω sourcing and
20 Ω sinking. This can be used to estimate output saturation
voltage when driving heavier current loads. For instance, when
sourcing 5 mA, the saturation voltage to the positive supply rail
will be 200 mV, when sinking 5 mA, the saturation voltage to
the minus rail will be 100 mV.
The amplifier’s open-loop gain characteristic will change as a
function of resistive load, as shown in Figures 7 through 10. For
load resistances over 20 kΩ, the AD822’s input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
If the AD822’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 µs of its
input returning to the amplifier’s linear operating region.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 41 shows the AD822’s
pulse response as a unity gain follower driving 350 pF. This
amount of overshoot indicates approximately 20 degrees of
phase margin—the system is stable, but is nearing the edge.
Configurations with less loop gain, and as a result less loop
bandwidth, will be much less sensitive to capacitance load
effects. Figure 42 is a plot of capacitive load that will result in a
20 degree phase margin versus noise gain for the AD822. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
10
0%
20mV 2µs
90
100
Figure 41. Small Signal Response of AD822 as Unity Gain
Follower Driving 350 pF Capacitive Load
5
1300 30k
4
2
1k
3
3k 10k
CAPACITIVE LOAD FOR 20
°
PHASE MARGIN – pF
NOISE GAIN – 1+ –––
R
F
R
I
R
F
R
I
C
L
Figure 42. Capacitive Load Tolerance vs. Noise Gain
Figure 43 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component
values, the circuit will drive 5,000 pF with a 10% overshoot.
8
4
0.01µF
20pF
20kΩ
100Ω
VOUT
VIN
+VS
–VS
0.01µF
CL
1/2
AD822
Figure 43. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
AD822
REV. A –15–
APPLICATIONS
Single Supply Voltage-to-Frequency Converter
The circuit shown in Figure 44 uses the AD822 to drive a low
power timer, which produces a stable pulse of width t
1
. The
positive going output pulse is integrated by R1-C1 and used as
one input to the AD822, which is connected as a differential
integrator. The other input (nonloading) is the unknown
voltage, V
IN
. The AD822 output drives the timer trigger input,
closing the overall feedback loop.
26
53
4
+10V
0.1µF
C5
RSCALE **
10k
R1
499k, 1%
VIN
R2
499k, 1%
0V TO 2.5V
FULL SCALE
C1
0.01µF, 2%
C2
0.01µF, 2%
U4
REF-02
U1
43
U3B 21
U3A
C6
390pF
5%
C3
0.1µF
THR
TR
DIS
RV+
OUT
CV
GND
48
6
2
7
1
3
5
(NPO) C4
0.01µF
R3*
116k
U2
CMOS 555
OUT2
OUT1
NOTES:
fOUT = VIN /(VREF*t1), t1 = 1.1*R3*C6
* = 1% METAL FILM, <50ppm/°C TC
** = 10%, 20T FILM, <100ppm/°C TC
t1 = 33µs FOR fOUT = 20kHz @ VIN = 2.0V
= 25kHz fS AS SHOWN.
VREF = 5V
CMOS
74HCO4
1/2
AD822B
Figure 44. Single Supply Voltage-to-Frequency Converter
Typical AD822 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 volt single supply which
delivers less than 1 mA to the entire circuit.
Single Supply Programmable Gain Instrumentation Amplifier
The AD822 can be configured as a single supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V, or dual supplies up to ±15 V. Using only one AD822
rather than three separate op amps, this circuit is cost and power
efficient. AD822 FET inputs’ 2 pA bias currents minimize offset
errors caused by high unbalanced source impedances.
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01%, and have a maximum differential TC of
5 ppm/°C.
Table I. AD822 In Amp Performance
Parameters V
S
= 3 V, 0 V V
S
= 65 V
CMRR 74 dB 80 dB
Common-Mode
Voltage Range –0.2 V to +2 V –5.2 V to +4 V
3 dB BW, G = 10 180 kHz 180 kHz
G = 100 18 kHz 18 kHz
t
SETTLING
2 V Step (V
S
= 0 V, 3 V) 2 µs
5 V (V
S
= ±5 V) 5 µs
Noise @ f = 1 kHz, G = 10 270 nV/√Hz 270 nV/√Hz
G = 100 2.2 µV/√Hz 2.2 µV/√Hz
I
SUPPLY
(Total) 1.10 mA 1.15 mA
10
90
100
0%
5µs
1V
Figure 45a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; V
S
= +5 V, 0 V; Gain = 10
(G =10) V
OUT
= (V
IN1
–V
IN2
) (1+ ) +V
REF
R6
R4 + R5
(G =100) V
OUT
= (V
IN1
–V
IN2
) (1+ ) +V
REF
FOR R1 = R6, R2 = R5, AND R3 = R4
R5 + R6
R4
R1 R2 R3 R4 R5 R6
90k9k1k1k9k90k
V
OUT
V
IN1
0.1µF
8
1/2
AD822
1/2
AD822
V
IN2
R
P
1kΩ
1
2
3
6
54
7
OHMTEK
PART # 1043
V
REF
G =10 G =100
R
P
1kΩ
G =100 G =10
+V
S
Figure 45b. A Single Supply Programmable
Instrumentation Amplifier
–16–
AD822
REV. A
MYLAR
1µF
1/2
AD822
L
R
HEADPHONES
32Ω IMPEDANCE
4.99k
MYLAR
1µF
4.99k
1/2
AD822
10k
10k
47.5k
95.3k
47.5k 500µF
500µF
11
3
+3V
2
4
7
5
6
95.3k
8
0.1µF0.1µF
CHANNEL 1
CHANNEL 2
Low Dropout Bipolar Bridge Driver
The AD822 can be used for driving a 350 ohm Wheatstone
bridge. Figure 47 shows one half of the AD822 being used to
buffer the AD589—a 1.235 V low power reference. The output
of +4.5 V can be used to drive an A/D converter front end. The
other half of the AD822 is configured as a unity-gain inverter,
and generates the other bridge input of –4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor R
G
, and determined
by:
G=49.4 kΩ
R
G
+1
350Ω350Ω
350Ω350Ω
V
REF
–V
S
+V
S
AD620
4
2
6
5
7
3
R
G
R2
20Ω
–4.5V
10k
10k
10k 26.4k, 1%
R1
20ΩTO A/D CONVERTER
REFERENCE INPUT
AD589
49.9k
+1.235V
0.1µF 1µF+5V
1µF
GND
1%
1%
1%
1/2
AD822 11
3
2
8
1/2
AD822
4
7
6
5
+V
S
+V
S
+V
S
–V
S
0.1µF –5V
Figure 47. Low Dropout Bipolar Bridge Driver
Figure 46. 3 Volt Single Supply Stereo Headphone Driver
3 Volt, Single Supply Stereo Headphone Driver
The AD822 exhibits good current drive and THD+N perfor-
mance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps which consume more power and cannot run on
3 V power supplies.
In Figure 46, each channel s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the non-
inverting inputs so that the output voltage is midway between
the power supplies (+1.5 V). The gain is 1.5. Each half of the
AD822 can then be used to drive a headphone channel. A 5 Hz
high-pass filter is realized by the 500 µF capacitors and the head-
phones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz–20 kHz) are delivered to the headphones.
C1821a–10–9/94
PRINTED IN U.S.A.
Cerdip (Q) Package
0.005 (0.13) MIN 0.055 (1.35) MAX
0.405 (10.29) MAX
0.150
(3.81)
MIN
0.200
(5.08)
MAX
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
41
5
8
0.310 (7.87)
0.220 (5.59)
0.320 (8.13)
0.290 (7.37)
0°-15°
0.015 (0.38)
0.008 (0.20)
SOIC (R) Package
0.019 (0.48)
0.014 (0.36)
0.050
(1.27)
BSC
0.102 (2.59)
0.094 (2.39)
0.197 (5.01)
0.189 (4.80)
0.010 (0.25)
0.004 (0.10)
0.098 (0.2482)
0.075 (0.1905)
0.190 (4.82)
0.170 (4.32)
0.030 (0.76)
0.018 (0.46)
10
°
0
°
0.090
(2.29)
8
°
0
°
0.020 (0.051) x 45
°
CHAMF
1
85
4
PIN 1
0.157 (3.99
)
0.150 (3.81
)
0.244 (6.20)
0.228 (5.79)
0.150 (3.81)
Mini-DIP (N) Package
0.011±0.003
(0.28±0.08)
0.30 (7.62)
REF
15
°
0
°
PIN 1
4
5
8
1
0.25
(6.35) 0.31
(7.87)
0.10
(2.54)
BSC
SEATING
PLANE
0.035±0.01
(0.89±0.25)
0.18±0.03
(4.57±0.76)
0.033
(0.84)
NOM
0.018±0.003
(0.46±0.08)
0.125
(3.18)
MIN
0.165±0.01
(4.19±0.25)
0.39 (9.91) MAX
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).