CLC428
Dual Wideband, Low Noise, Voltage Feedback Op Amp
General Description
The National CLC428 is a very high speed dual op amp that
offers a traditional voltage-feedback topology featuring unity
gain stability and slew enhanced circuitry. The CLC428’s
ultra low noise and very low harmonic distortion combine to
form a very wide dynamic range op amp that operates from
a single (5 to 12V) or dual (±5V) power supply.
Each of the CLC428’s closely matched channels provides a
160MHz unity gain bandwidth with an ultra low input voltage
noise density (2nV/ ). Very low 2nd/3rd harmonic distor-
tion (-62dB) make the CLC428 a perfect wide dynamic range
amplifier for matched I/Q channels.
With its fast and accurate settling (16ns to 0.1%), the
CLC428 is also an excellent choice for wide dynamic range,
anti-aliasing filters to buffer the inputs of hi-resolution
analog-to-digital converters. Combining the CLC428’s two
tightly matched amplifiers in a single eight-pin SOIC reduces
cost and board space for many composite amplifier applica-
tions such as active filters, differential line drivers/receivers,
fast peak detectors and instrumentation amplifiers.
To reduce design times and assist in board layout, the
CLC428 is supported by an evaluation board and a SPICE
simulation model available from National.
Features
nWide unity gain bandwidth: 160MHz
nUltra low noise: 2.0nV/
nLow Distortion: −78dBc 2nd (2MHz)
nLow Distortion: −62/−72dBc (10MHz)
nSettling time: 16ns to 0.1%
nSupply voltage range: ±2.5 to ±5 or single supply
nHigh output current: ±70mA
Applications
nGeneral purpose dual op amp
nLow noise integrators
nLow noise active filters
nDiff-in/diff-out instrumentation amp
nDriver/receiver for transmission systems
nHigh speed detectors I/Q channel amplifiers
Typical Application
Channel Matching
DS012710-1
Frequency & Phase Response
DS012710-3
5-Decade Integrator
DS012710-2
September 2001
CLC428 Dual Wideband, Low Noise, Voltage Feedback Op Amp
© 2001 National Semiconductor Corporation DS012710 www.national.com
Connection Diagram
Ordering Information
Package Temperature Range
Industrial Part Number Package Marking NSC Drawing
8-pin plastic DIP −40˚C to +85˚C CLC428AJP CLC428AJP N08E
8-pin plastic SOIC −40˚C to +85˚C CLC428AJE CLC428AJE M08A
DS012710-35
Pinout
DIP & SOIC
CLC428
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage ±7V
Short Circuit Current (see note 6)
Common-Mode Input Voltage ±V
CC
Differential Input Voltage ±10V
Maximum Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature (soldering 10 sec) +300˚C
Operating Ratings
Thermal Resistance
Package (θ
JC
)(θ
JA
)
MDIP 60˚C/W 115˚C/W
SOIC 40˚C/W 115˚C/W
Electrical Characteristics
V
CC
=±5V,A
V
= +2V/V, R
f
=100Ω,R
g
= 100Ω,R
L
= 100Ω; unless specified.
Symbol Parameter Conditions Typ Min/Max Ratings
(Note 2) Units
Ambient Temperature CLC428AJ +25˚C +25˚C 0 to
+70˚C −40 to
+85˚C
Frequency Domain Response
Gain Bandwidth Product V
OUT
<0.5V
PP
135 100 80 70 MHz
-3dB Bandwidth, A
V
=+1 V
OUT
<0.5V
PP
160 120 90 80 MHz
A
V
=+2 V
OUT
<0.5V
PP
80 50 40 35 MHz
V
OUT
<5.0V
PP
40 25 22 20 MHz
Gain Flatness V
OUT
<0.5V
PP
Peaking DC to 200MHz 0.0 0.6 0.8 1.0 dB
Rolloff DC to 20MHz 0.05 0.5 0.7 0.7 dB
Linear Phase Deviation DC to 20MHz 0.2 1.0 1.5 1.5 deg
Time Domain Response
Rise and Fall Time 1V Step 5.5 7.5 9.0 10.0 ns
Settling Time 2V Step to 0.1% 16 20 24 24 ns
Overshoot 1V Step 1 5 10 10 %
Slew Rate 5V Step 500 300 275 250 V/µs
Distortion And Noise Response
2nd Harmonic Distortion 1V
PP
, 10MHz −62 −50 −45 −43 dBc
3rd Harmonic Distortion 1V
PP
, 10MHz −72 −60 −56 −56 dBc
Equivalent Input Noise
Voltage 1MHz to 100MHz 2.0 2.5 2.8 2.8 nV/
Current 1MHz to 100MHz 2.0 3.0 3.6 4.6 pA/
Crosstalk Input Referred, 10MHz −62 −58 −58 −58 dB
Static, DC Performance
Open-Loop Gain 60 56 50 50 dB
Input Offset Voltage (Note 3) 1.0 2.0 3.0 3.5 mV
Average Drift 5 - 15 20 µV/˚C
Input Bias Current (Note 3) 1.5 25 40 65 µA
Average Drift 150 - 600 700 nA/˚C
Input Offset Current 0.3 3 5 5 µA
Average Drift 5 - 25 50 nA/˚C
Power Supply Rejection Ratio
(Note 4) 66 60 55 55 dB
Common-Mode Rejection Ratio 63 57 52 52 dB
Supply Current (Note 3) Per Channel, R
L
=∞11 12 13 15 mA
CLC428
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Electrical Characteristics (Continued)
V
CC
=±5V,A
V
= +2V/V, R
f
=100Ω,R
g
= 100Ω,R
L
= 100Ω; unless specified.
Symbol Parameter Conditions Typ Min/Max Ratings
(Note 2) Units
Miscellaneous Performance
Input Resistance Common-Mode 500 250 125 125 kΩ
Differential-Mode 200 50 25 25 kΩ
Input Capacitance Common-Mode 2.0 3.0 3.0 3.0 pF
Differential-Mode 2.0 3.0 3.0 3.0 pF
Output Resistance Closed-Loop 0.05 0.1 0.2 0.2 Ω
Output Voltage Range R
L
=∞±3.8 ±3.5 ±3.3 ±3.3 V
R
L
= 100Ω±3.5 ±3.2 ±2.6 ±1.3 V
Input Voltage Range Common- Mode ±3.7 ±3.5 ±3.3 ±3.3 V
Output Current ±70 ±50 ±40 ±20 mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level: spec. is 100% tested at +25˚C, sample tested at +85˚C.
Note 4: J-level: spec. is 100% tested at +25˚C.
Note 5: Specifications guaranteed using 0.5VPP but tested at 0.1 VPP.
Note 6: Output is short circuit protected to ground, however maximum reliability is obtained if output current does not exceed 160mA.
Typical Performance Characteristics (T
A
= +25˚, A
V
= +2, V
CC
=±5V, R
f
=100Ω,R
L
= 100Ω, un-
less specified)
Non-Inverting Frequency Response
DS012710-4
Inverting Frequency Response
DS012710-5
Frequency Response vs. Load Resistance
DS012710-6
Frequency Response vs. Output Amplitude
DS012710-7
CLC428
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Typical Performance Characteristics (T
A
= +25˚, A
V
= +2, V
CC
=±5V, R
f
=100Ω,R
L
= 100Ω,
unless specified) (Continued)
Frequency Response vs. Capacitive Load
DS012710-8
Gain Flatness & Linear Phase Deviation
DS012710-9
Maximum Output Voltage vs. Load
DS012710-10
Channel-to-Channel Crosstalk
DS012710-11
Open-Loop Gain & Phase
DS012710-12
2nd and 3rd Harmonic Distortion
DS012710-13
CLC428
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Typical Performance Characteristics (T
A
= +25˚, A
V
= +2, V
CC
=±5V, R
f
=100Ω,R
L
= 100Ω,
unless specified) (Continued)
2nd Harmonic Distortion vs. Output Voltage
DS012710-14
3rd Harmonic Distortion vs. Output Voltage
DS012710-15
Closed-Loop Output Resistance
DS012710-16
Equivalent Input Noise
DS012710-17
2-Tone, 3rd Order Intermodulation Intercept
DS012710-18
Pulse Response (V
OUT
= 100V)
DS012710-19
CLC428
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Typical Performance Characteristics (T
A
= +25˚, A
V
= +2, V
CC
=±5V, R
f
=100Ω,R
L
= 100Ω,
unless specified) (Continued)
Pulse Response (V
OUT
= 2V)
DS012710-20
Settling Time vs. Capacitive Load
DS012710-21
Short-Term Settling Time
DS012710-22
CMRR and PSRR
DS012710-23
Typical DC Errors vs. Temperature
DS012710-24
CLC428
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Application Division
Low Noise Design
Ultimate low noise performance from circuit designs using
the CLC428 requires the proper selection of external resis-
tors. By selecting appropriate low valued resistors for R
f
and
R
g
, amplifier circuits using the CLC428 can achieve output
noise that is approximately the equivalent voltage input
noise of 2.0 nV/ multiplied by the desired gain (A
V
).
Each amplifier in the CLC428 has an equivalent input noise
resistance which is optimum for matching source imped-
ances of approximately 1k. Using a transformer, any source
can be matched to achieve the lowest noise design.
For even lower noise performance than the CLC428, con-
sider the CLC425 or CLC426 at 1.05 and 1.6nV/ , re-
spectively.
DC Bias Currents and Offset Voltages
Cancellation of the output offset voltage due to input bias
currents is possible with the CLC428. This is done by making
the resistance seen from the inverting and non-inverting
inputs equal. Once done, the residual output offset voltage
will be the input offset voltage (Vos) multiplied by the desired
gain (Av). Comlinear Application Note OA-7 offers several
solutions to further reduce the output offset.
Output and Supply Considerations
With ±5V supplies, the CLC428 is capable of a typical output
swing of ±3.8V under a no-load condition. Additional output
swing is possible with slightly higher supply voltages. For
loads of less than 50Ω, the output swing will be limited by the
CLC428’s output current capability, typically 80mA.
Output settling time when driving capacitive loads can be
improved by the use of a series output resistor. See the plot
labeled ’Settling Time vs. Capacitive Load’ in the Typical
Performance section.
Layout
Proper power supply bypassing is critical to insure good high
frequency performance and low noise. De-coupling capaci-
tors of 0.1µF should be placed as close as possible to the
power supply pins. The use of surface mounted capacitors is
recommended due to their low series inductance.
A good high frequency layout will keep power supply and
ground traces away from the inverting input and output pins.
Parasitic capacitance from these nodes to ground causes
frequency response peaking and possible circuit oscillation.
See OA-15 for more information. National suggests the
730038 (through-hole) or the 730036 (SOIC) dual op amp
evaluation board as a guide for high frequency layout and as
an aid in device evaluation.
Analog Delay Circuit (All-Pass Network)
The circuit in
Figure 1
implements an all-pass network using
the CLC428. A wide bandwidth buffer (CLC111) drives the
circuit and provides a high input impedance for the source.
As shown in
Figure 2
, the circuit provides a 13.1ns delay
(with R = 40.2Ω, C = 47pF). R
f
and R
g
should be of equal
and low value for parasitic insensitive operation.
The circuit gain is +1 and the delay is determined by the
following equations.
(1)
Td
df
d=1
360 φ;
(2)
where T
d
is the delay of the op amp at A
V
=+1.
The CLC428 provides a typical delay of 2.8ns at its −3dB
point.
Full Duplex Digital or Analog Transmission
Simultaneous transmission and reception of analog or digital
signals over a single coaxial cable or twisted-pair line can
reduce cabling requirements. The CLC428’s wide bandwidth
and high common-mode rejection in a differential amplifier
configuration allows full duplex transmission of video, tele-
phone, control and audio signals.
In the circuit shown in
Figure 3
, one of the CLC428’s amps is
used as a ’driver’ and the other as a difference ’receiver’
amplifier. The output impedance of the ’driver’ is essentially
zero. The two R’s are chosen to match the characteristic
impedance of the transmission line. The ’driver’ op amp gain
can be selected for unity or greater.
Receiver amplifier A
2
(B
2
) is connected across R and forms
differential amplifier for the signals transmitted by driver A
2
(B
2
). If the coax cable is lossless and R
f
equals R
g
, receiver
A
2
(B
1
) will then reject the signals from driver A
1
(B
1
) and
pass the signals from driver B
1
(A
1
).
DS012710-25
FIGURE 1.
DS012710-26
FIGURE 2. Delay Circuit Response to 0.5V Pulse
CLC428
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Application Division (Continued)
The output of the receiver amplifier will be:
(3)
Care must be given to layout and component placement to
maintain a high frequency common-mode rejection. The plot
of
Figure 4
shows the simultaneous reception of signals
transmitted at 1MHz and 10MHz.
Five Decade Integrator
A composite integrator, as shown in
Figure 5
, uses the
CLC428 dual op amp to increase the circuits’ usable fre-
quency range of operation. The transfer function of this
circuit is:
(4)
A resistive divider made from the 143Ωand 60.4Ωresistors
was chosen to reduce the loop-gain and stabilize the net-
work. The CLC428 composite integrator provides integration
over five decades of operation. R and C set the integrator’s
gain.
Figure 6
shows the frequency and phase response of
the circuit in
Figure 5
with R = 44.2Ωand C = 360pF.
Positive Peak Detector
The CLC428’s dual amplifiers can be used to implement a
unity-gain peak detector circuit as shown in
Figure 7
.
The acquisition speed of this circuit is limited by the dynamic
resistance of the diode when charging C
hold
. A plot of the
circuit’s performance is shown in
Figure 8
with a 1MHz
sinusoidal input.
DS012710-29
FIGURE 3.
DS012710-31
FIGURE 4.
DS012710-33
FIGURE 5.
DS012710-34
FIGURE 6.
Q1
DS012710-36
FIGURE 7.
DS012710-37
FIGURE 8.
CLC428
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Application Division (Continued)
A current source, built around Q1, provides the necessary
bias current for the second amplifier and prevents saturation
when power is applied. The resistor, R, closes the loop while
diode D2 prevents negative saturation when V
in
is less than
V
C
. AMOS-type switch (not shown) can be used to reset the
capacitor’s voltage.
The maximum speed of detection is limited by the delay of
the op amps and the diodes. The use of Schottky diodes will
provide faster response.
Adjustable or Bandpass Equalizer
A ’boost’ equalizer can be made with the CLC428 by sum-
ming a bandpass response with the input signal, as shown in
Figure 9
.
The overall transfer function is shown in Eq. 5.
(5)
To build a boost circuit, use the design equations Eq. 6 and
Eq. 7.
(6)
Select R
2
and C using Eq. 6. Use reasonable values for high
frequency circuits - R
2
between 10Ωand 5kΩ, C between
10pF and 2000pF. Use Eq. 7 to determine the parallel com-
bination of R
a
and R
b
. Select R
a
and R
b
by either the 10Ωto
5kΩcriteria or by other requirements based on the imped-
ance V
in
is capable of driving. Finish the design by determin-
ing the value of K from Eq. 8.
(7)
Figure 10
shows an example of the response of the circuit of
Figure 9, where f
o
is 2.3MHz. The component values are as
follows: R
a
=2.1KΩ,R
2
= 68.5Ω,R
2
= 4.22kΩ,R=500Ω,KR
=50Ω, C = 120pF.
DS012710-38
FIGURE 9.
DS012710-43
FIGURE 10.
CLC428
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
8-Pin MDIP
NS Package Number N08E
CLC428
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Notes
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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CLC428 Dual Wideband, Low Noise, Voltage Feedback Op Amp
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.