2012-2014 Microchip Technology Inc. DS20002298C-page 1
MCP2021A/2A
Features:
• The MCP2021A/2A are compliant with LIN Bus
Specifications Version 1.3, 2.1 and with SAE
J2602-2
• Support Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage: 30V
• Wide LIN-Compliant Supply Voltage: 6.0 – 18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC® MCU EUSART and Standard
USARTs
• Wake-Up on LIN Bus Activity or Local Wake Input
• Local Interconnect Network (LIN) Bus Pin:
- Internal Pull-Up Termination Resistor and
Diode for Slave Node
- Protected Against VBAT Shorts
- Protected Against Loss of Ground
- High-Current Drive
•T
XD and LIN Bus Dominant Time-Out Function
• Two Low-Power Modes:
- Transmitter Off: 90 µA (typical)
- Power Down: 4.5 µA (typical)
• Output Indicating Internal Reset State (POR or
Sleep Wake)
• MCP2021A/2A On-Chip Voltage Regulator:
- Output Voltage of 5.0V or 3.3V
at 70 mA Capability with Tolerances of ±3%
Over the Temperature Range
- Internal Short Circuit Current Limit
- External Components Limited to Filter
Capacitor and Load Capacitor
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low
Electromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design
Requirements, including “OEM Hardware
Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications”, Version
1.2, March 2011
• Multiple Package Options, including Small
4x4 mm DFN Package
Description:
The MCP2021A/2A provide a bidirectional, half-duplex
communication physical interface to meet the LIN bus
specification Revision 2.1 and SAE J2602-2. The
devices incorporate a voltage regulator with 5V or 3.3V
at 70 mA regulated power supply output. The devices
have been designed to meet the stringent quiescent
current requirements of the automotive industry and
will survive +43V load dump transients and double
battery jumps.
Package Types
MCP2021A
PDIP, SOIC
VREG
CS/LWAKE
TXD
1
2
3
4
8
7
6
5
RXD FAULT/TXE
VBB
LBUS
VSS
MCP2021A
4x4 DFN
VREG
CS/LWAKE
TXD
RXD FAULT/TXE
VBB
LBUS
VSS
1
2
3
4
8
7
6
5
EP
9
MCP2022A
PDIP, SOIC, TSSOP
VREG
CS/LWAKE
TXD
1
2
3
4
14
13
12
11
RXD FAULT/TXE
VBB
LBUS
VSS
RESET 510 NC
NC 69
NC 78NC
NC
* Includes Exposed Thermal Pad (EP), see Table 1-2.
LIN Transceiver with Voltage Regulator
MCP2021A/2A
DS20002298C-page 2 2012-2014 Microchip Technology Inc.
MCP2021A/2A Block Diagram
Internal Circuits
VREG
FAULT/TXE
RXD
TXD
CS/LWAKE
Bus Wake-Up
Slope Control
VREG
4.2V
VREG
RESET
(MCP2022A only)
VBB
LBUS
VSS
~ 30 k
Short Circuit
Protection
Thermal
Protection
Voltage
Regulator
Wake-Up Logic
and
Power Control
Ratiometric
Reference
Bus
Dominant
Timer
Thermal and
Short Circuit
Protection
2012-2014 Microchip Technology Inc. DS20002298C-page 3
MCP2021A/2A
1.0 DEVICE OVERVIEW
The MCP2021A/2A devices provide a physical
interface between a microcontroller and a LIN
half-duplex bus. They are intended for automotive and
industrial applications with serial bus baud rates up to
20 kBaud. These devices will translate the CMOS/TTL
logic levels to LIN logic levels and vice versa.
The MCP2021A/2A offer optimum EMI and ESD
performance and can withstand high voltage on the LIN
bus. The devices support two low-power modes to
meet automotive industry power consumption
requirements. The MCP2021A/2A also provide a +5V
or 3.3V regulated power output at 70 mA.
1.1 Modes of Operation
The MCP2021A/2A work in five modes: Power-On
Reset, Power-Down, Ready, Operation and
Transmitter Off. For an overview of all operational
modes, please refer to Ta b l e 1 - 1 . For the operational
mode transition, please refer to Figure 1-1.
FIGURE 1-1: STATE DIAGR AM
Note 1: VREG_OK: Regulator Output Voltage > 0.8VREG_NOM.
2: If the voltage on pin VBB falls below VOFF, the device will enter Power-On Reset mode from all other
modes, which is not shown in the figure.
3: FAULT/TXE =1 represents input high and no fault conditions. FAULT/TXE =0 represents input low or a
fault condition. Refer to Table 1-5.
POR(2)
VREG OFF
RX OFF
TX OFF
READY
VREG ON
RX ON
TX OFF
TX OFF
VREG ON
RX ON
TX OFF
POWER-DOWN
VREG OFF
RX OFF
TX OFF
OPERATION
VREG ON
RX ON
TX ON
VBB >VON
CS/LWAKE = 1&
FAULT/TXE =0&
CS/LWAKE = 0
CS/LWAKE = 1 &
FAULT/TXE =1(3) &
TXD =1&
VREG_OK = 1(1)
CS/LWAKE = 1&
FAULT/TXE =1(3)&
TXD =1
CS/LWAKE = 1&
FAULT/TXE =0
CS/LWAKE = 0
CS/LWAKE = 1 OR
Voltage Rising Edge on LBUS
CS/LWAKE = 0
MCP2021A/2A
DS20002298C-page 4 2012-2014 Microchip Technology Inc.
1.1.1 POWER-ON RESET MODE
Upon application of VBB or whenever the voltage on
VBB is below the threshold of regulator turn-off voltage
VOFF (typically 4.50V), the device enters Power-On
Reset (POR) mode. During this mode, the device
maintains the digital section in a Reset mode and waits
until the voltage on the VBB pin rises above the
threshold of regulator turn-on voltage VON (typically
5.75V) to enter Ready mode. In Power-On Reset
mode, the LIN physical layer and voltage regulator are
disabled and the RESET output (MCP2022A only) is
forced to low.
1.1.2 READY MODE
The device enters Ready mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn-on voltage VON or from Power-Down
mode when a remote or local wake-up event happens.
Upon entering Ready mode, the voltage regulator and
the receiver section of the transceiver are powered up.
The transmitter remains in an off state. The device is
ready to receive data but not to transmit. In order to
minimize the power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The device stays in Ready mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is high (‘1’).
1.1.3 OPERATION MODE
If VREG is OK (VREG >0.8VREG_NORM) and the
CS/LWAKE, FAULT/TXE and TXD pins are high, the
part enters Operation mode from either Ready or
Transmitter Off mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is
connected only in this mode.
The device goes into Power-Down mode at the falling
edge on CS/LWAKE or into Transmitter Off mode at the
falling edge on FAULT/TXE while CS/LWAKE stays
high.
1.1.4 TRANSMITTER OFF MODE
In Transmitter Off mode, the receiver is enabled but the
LBUS transmitter is off. It is a lower power mode.
In order to minimize power consumption, the regulator
operates in a reduced-power mode. It has a lower
GBW product and it is thus slower. However, the 70 mA
drive capability is unchanged.
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, by removing the
internal fault condition and by driving FAULT/TXE high.
The transmitter will not be enabled even if the
FAULT/TXE pin is brought high externally, when the
internal fault is still present. However, externally forcing
the FAULT/TXE high while the internal fault is still
present should be avoided, since this will induce high
current and power dissipation in the FAULT/TXE pin.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.1.5 POWER-DOWN MODE
In Power-Down mode, the transceiver and the voltage
regulator are both off. Only the bus wake-up section
and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g., a Break character) occurs
during Power-Down mode, the device will immediately
enter Ready mode and enable the voltage regulator.
Then, once the regulator output has stabilized
(approximately 0.3 ms to 1.2 ms), it goes into
Operation mode. Refer to Section 1.1.6 “Remote
Wake-Up”.
The part will also enter Ready mode from Power-Down
mode, followed by the Operation mode, if the
CS/LWAKE pin becomes active high (‘1’).
1.1.6 REMOTE WAKE-UP
The Remote Wake-Up sub-module observes the LBUS
in order to detect bus activity. In Power-Down mode,
normal LIN recessive/dominant threshold is disabled
and the LIN bus wake-up voltage threshold VWK(LBUS)
is used to detect bus activities. Bus activity is detected
when the voltage on the LBUS falls below the LIN bus
wake-up voltage threshold VWK(LBUS) (approximately
3.5V) for at least tBDB (a typical duration of 80 µs)
followed by a rising edge. Such a condition causes the
device to leave Power-Down mode.
2012-2014 Microchip Technology Inc. DS20002298C-page 5
MCP2021A/2A
TABLE 1-1: OVERVIEW OF OPERATIONAL MODES
State Transmitter Receiver Internal
Wake
Module
Voltage
Regulator Operation Comments
POR OFF OFF OFF OFF Proceed to Ready mode after
VBB >VON
Ready OFF ON OFF ON If CS/LWAKE is high, then proceed to
Operation or Transmitter Off mode.
Bus Off
state
Operation ON ON OFF ON If CS/LWAKE is low, then proceed to
Power-Down mode.
If FAULT/TXE is low, then proceed to
Transmitter Off mode.
Normal
Operation
mode
Power-Down OFF OFF ON
Activity
Detect
OFF On LIN bus rising edge or CS/LWAKE
high level, go to Ready mode.
Lowest
power mode
Transmitter Off OFF ON OFF ON If CS/LWAKE is low, then proceed to
Power-Down mode.
If FAULT/TXE is high, then proceed to
Operation mode.
Bus Off
state,
lower power
mode
MCP2021A/2A
DS20002298C-page 6 2012-2014 Microchip Technology Inc.
1.2 Pin Descriptions
The descriptions of the pins are listed in Tabl e 1- 2.
1.2.1 RECEIVE DATA OUTPUT (RXD)
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
1.2.2 CHIP SELECT AND LOCAL
WAKE-UP INPUT (CS/LWAKE)
Chip Select and Local Wake-up Input pin (TTL level,
high-voltage tolerant). This pin controls the device state
transition. Refer to Figure 1-1.
If CS/LWAKE = 1, the device can work in Operation
mode (FAULT/TXE =1) or in Transmitter Off mode
(FAULT/TXE =0). If CS/LWAKE = 0, the device can
work in Power-Down mode or in Ready mode.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-On Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 k) is used
to reduce current. When CS/LWAKE is ‘0’, a stronger
pull-down (~300 k) is used to maintain the logic level.
This pin may also be used as a local wake-up input
(see Figure 1-1). The microcontroller will set the I/O pin
to control the CS/LWAKE. An external switch or
another source can then wake up both the transceiver
and the microcontroller.
1.2.3 POWER OUTPUT (VREG)
Positive Supply Voltage Regulator Output pin. An
on-chip LDO gives +5.0 or +3.3V at 70 mA regulated
voltage on this pin.
1.2.4 TRANSMIT DATA INPUT (TXD)
Transmit Data Input pin (TTL level, HV-compliant,
adaptive pull-up). The transmitter reads the data
stream on the TXD pin and sends it to the LIN bus. The
LBUS pin is low (dominant) when TXD is low and high
(recessive) when TXD is high.
TXD is internally pulled up to approximately 4.2V. When
TXD is ‘0’, a weak pull-up (~900 k) is used to reduce
current. When TXD is ‘1’, a stronger pull-up (~300 k)
is used to maintain the logic level. A series
reverse-blocking diode allows applying TXD input
voltages greater than the internally generated 4.2V and
renders the TXD pin HV-compliant up to 30V (see
MCP2021A/2A Block Diagram).
1.2.5 RESET (MCP2022A ONLY)
RESET output pin. This pin is open-drain with ~90 k
pull-up to VREG. It indicates the internal voltage has
reached a valid, stable level. As long as the internal
voltage is valid (above 0.8 VREG), this pin will remain
high (‘1’); otherwise, the RESET pin switches to low
(‘0’).
1.2.6 NO CONNECTION (NC)
No internal connection.
TABLE 1-2: PIN FUNCTION TABLE
Pin Name
Pin Number
Pin Type Description
8-lead
PDIP, SOIC 4x4 DFN 14-lead
PDIP, SOIC, TSSOP
RXD 1 1 1 Output Receive Data Output
CS/LWAKE 2 2 2 TTL Input,
HV-tolerant
Chip Select and Local Wake-up
Input
VREG 3 3 3 Output Voltage Regulator Output
TXD 4 4 4 Input, HV-tolerant Transmit Data Input
RESET — — 5 Output Reset Output
NC — — 6–10 — No Connection
VSS 5 5 11 Power Ground
LBUS 6 6 12 I/O, HV LIN Bus
VBB 7 7 13 Power Battery
FAULT/TXE 8 8 14 I/O, HV-tolerant Fault Detect Output/Transmitter
Enable Input
EP — 9 — — Exposed Thermal Pad
Note: CS/LWAKE should NOT be tied directly to
the VREG pin as this could force the
MCP2021A/2A into Operation mode
before the microcontroller is initialized.
2012-2014 Microchip Technology Inc. DS20002298C-page 7
MCP2021A/2A
1.2.7 GROUND (VSS)
Ground pin.
1.2.8 LIN BUS (LBUS)
LIN Bus pin. LBUS is a bidirectional LIN bus interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
electromagnetic emission, the slopes during signal
changes are controlled and the LBUS pin has
corner-rounding control for both falling and rising
edges.
The internal LIN receiver observes the activities on the
LIN bus and generates the output signal RXD that
follows the state of the LBUS. A 1st degree 160 kHz
low-pass input filter optimizes electromagnetic
immunity.
1.2.9 BATTERY POSITIVE SUPPLY
VOLTAGE (VBB)
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to Figure 1-7).
1.2.10 FAULT DETECT
OUTPUT/TRANSMITTER ENABLE
INPUT (FAULT/TXE)
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV-tolerant open-drain (up to 30V).
The input section is identical to the TXD section (TTL
level, HV-compliant, adaptive pull-up). The internal
pull-up resistor may be too weak for some applications.
We recommend adding a 10 k external pull-up
resistor to ensure a logic high level. Its state is defined
as shown in Tab le 1- 5. The device is placed in
Transmitter Off mode whenever this pin is low (‘0’),
either from an internal fault condition or by external
drive.
If CS/LWAKE is high (‘1’), the FAULT/TXE signals a
mismatch between the TXD input and the LBUS level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains low (‘0’)
(refer to Table 1-5).
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
TABLE 1-3: FAULT/TXE TRUTH TABLE
TXD
In RXD
Out LINBUS
I/O Thermal
Override
FAULT/TXE
Definition
External
Input Driven
Output
CS = 1
LH V
BB OFF H L FAULT, TXD driven low, LBUS shorted to VBB (Note 1)
or LBUS/TXD permanent dominant detected and Trans-
mit time-out shutdown.
HH V
BB OFF H H OK
LLGND OFF H HOK
HLGND OFF H HOK, data is being received from LBUS
xx VBB ON H L FAULT, Transceiver in thermal shutdown
xx VBB xLxNO FAULT, the CPU is commanding the transceiver
to turn off the transmitter driver
CS = 0
xx x x x LWake-up from LIN bus activity
xx x x x HWake-up from POR
Legend: x=Don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after the TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
MCP2021A/2A
DS20002298C-page 8 2012-2014 Microchip Technology Inc.
1.3 Fail-Safe Features
1.3.1 GENERAL FAIL-SAFE FEATURES
• An internal pull-down resistor on CS/LWAKE pin
disables the transmitter if the pin is floating.
• An internal pull-up resistor on the TXD pin places
TXD in high and the LBUS in recessive if the TXD
pin is floating.
• High-impedance and low-leakage current on LBUS
during loss of power or ground.
• The current limit on LBUS protects the transceiver
from being damaged if the pin is shorted to VBB.
1.3.2 THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter and voltage regulator.
There are three causes for a thermal overload. A
thermal shutdown can be triggered by any one, or a
combination of, the following thermal overload
conditions:
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
The recovery time from the thermal shutdown is equal
to adequate cooling time.
Driving the TXD and checking the RXD pin make it
possible to determine whether there is a bus contention
(TXD = high, RXD = low) or a thermal overload
condition (TXD =low, RXD = high).
FIGURE 1-2: THERMAL SHUTDOWN
STATE DIAGRAMS
1.3.3 TXD/LBUS TIME-OUT TIMER
The LIN bus can be driven to a dominant level either
from the TXD pin or externally. An internal timer
deactivates the LBUS transmitter if a dominant status
(low) on the LIN bus lasts longer than Bus Dominant
Time-out Time, tTO(LIN) (approximately
20 milliseconds). At the same time, the RXD output is
put in recessive (high), FAULT/TXE is also driven to low
and the internal LIN pull-up resistor is disconnected.
The timer is reset on any recessive LBUS status or POR
mode. The recessive status on LBUS can be caused
either by the bus being externally pulled up or by the
TXD pin being returned high.
1.4 Internal Voltage Regulator
The MCP2021A/2A have a positive regulator capable
of supplying +5.00 or +3.30 VDC ±3% at up to 70 mA of
load current over the entire operating temperature
range of -40°C to +125°C. The regulator uses a LDO
design, is short-circuit-protected and will turn the
regulator output off if its output falls below the shutdown
voltage threshold, VSD.
With a load current of 70 mA, the minimum input to
output voltage differential required for the output to
remain in regulation is typically +0.5V (+1V maximum
over the full operating temperature range). Quiescent
current is less than 100 µA with a full 70 mA load
current when the input to output voltage differential is
greater than +3.00V.
Regarding the correlation between VBB, VREG and IDD,
please refer to Figures 1-4 and 1-5. When the input
voltage (VBB) drops below the differential needed to
provide stable regulation, the voltage regulator output,
VREG, will track the input down to approximately VOFF,
at which point the regulator will turn off the output. This
will allow PIC® microcontrollers with internal POR
circuits to generate a clean arming of the POR trip
point. The MCP2021A/2A will then monitor VBB and
turn on the regulator when VBB is above the threshold
of regulator turn-on voltage, VON.
In Power-Down mode, the VBB monitor is turned off.
Under specific ambient temperature and battery
voltage range, the voltage regulator can output as high
as 150 mA current. For current load capability of the
voltage regulator, refer to Figures 2-8 and 2-9.
Voltage
Regulator
Shutdown
Operation
Mode
Transmitter
Shutdown
Output
Overload
LIN Bus
Shorted to
VBB
Temp < SHUTDOWNTEMP Temp < SHUTDOWNTEMP
Note: The regulator has an overload current limit
of approximately 250 mA. The regulator
output voltage, VREG, is monitored. If
output voltage VREG is lower than VSD, the
voltage regulator will turn off. After a
recovery time of about 3 ms, the VREG will
be checked again. If there is no short
circuit (VREG >VSD), then the voltage
regulator remains on.
2012-2014 Microchip Technology Inc. DS20002298C-page 9
MCP2021A/2A
The regulator requires an external output bypass
capacitor for stability. See Figure 2-1 for correct
capacity and ESR for stable operation.
In worst-case scenarios, the ceramic capacitor may
derate by 50%, based on tolerance, voltage and
temperature. Therefore, in order to ensure stability,
ceramic capacitors smaller than 10 µF may require a
small series resistance to meet the ESR requirements,
as shown in Tabl e 1-4 .
FIGURE 1-3: VOLTAGE REGULATOR BLOCK DIAGRAM
Note: A ceramic capacitor of at least 10 µF or a
tantalum capacitor of at least 2.2 µF is
recommended for stability.
TABLE 1-4: RECOMMENDED SERIES
RESISTANCE FOR CERAMIC
CAPACITORS
Resistance Capacitor
11µF
0.472.2 µF
0.224.7 µF
0.16.8 µF
Pass
Element
Sampling
Network
Buffer
VREG VBB
VSS
Fast
Transient
Loop
VREF
MCP2021A/2A
DS20002298C-page 10 2012-2014 Microchip Technology Inc.
FIGURE 1-4: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET
FIGURE 1-5: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT PROTECTION
Note 1: Start-up, VBB <VON, regulator off.
2: VBB >VON, regulator on.
3: VBB Minimum VBB to maintain regulation.
4: VBB <VOFF, regulator will turn off.
5
3
2
0
(1) (2) (3)
t
0t
6
2
8
4
VBB
V
VREG
V
1
4
VON
VOFF
Minimum VBB to maintain regulation
VREG-NOM
(4)
Note 1: IREG less than lLIM, regulator on.
2: After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached.
VSD
0
(1) (2)
t
0t
lLIM
IREG
mA
VREG
V
VREG-NOM
1
2
3
4
5
6
2012-2014 Microchip Technology Inc. DS20002298C-page 11
MCP2021A/2A
1.5 Optional External Protection
1.5.1 REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-7).
1.5.2 TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a transient protection
resistor (RTP) in series with the battery supply and the
VBB pin, protects the device from power transients and
ESD events greater than 43V (see Figure 1-7). The
maximum value for the RTP protection resistor depends
upon two parameters: the minimum voltage the part will
start at and the impacts of this RTP resistor on the VBB
value, thus on the bus recessive level and slopes.
This leads to a set of three equations to fulfill.
Equation 1-1 provides a maximum RTP value
according to the minimum battery voltage the user
wants.
Equation 1-2 provides a maximum RTP value
according to the maximum error on the recessive level,
thus VBB, since the part uses VBB as the reference
value for the recessive level.
Equation 1-3 provides a maximum RTP value
according to the maximum relative variation the user
can accept on the slope when IREG varies.
Since both Equations 1-1 and 1-2 must be fulfilled, the
maximum allowed value for RTP is thus the smaller of
the two values found when solving Equations 1-1
and 1-2.
Usually Equation 1-1 gives the higher constraint
(smaller value) for RTP, as shown in the following
example where VBATmin is 8V.
However, the user needs to check that the value found
with Equation 1-1 fulfills Equations 1-2 and 1-3.
While this protection is optional, it should be
considered as good engineering practice.
EQUATION 1-1:
Assume VBATmin =8V. Equation 1-1 shows 10
EQUATION 1-2:
Assume VRECESSIVE = 1V and IREGMAX =50mA.
Equation 1-2 shows 20.
EQUATION 1-3:
Assume Slope = 15%, VBATMIN =8V and
IREGMAX =50mA. Equation 1-2 shows 20.
1.5.3 CBAT CAPACITOR
Selecting CBAT =10xCREG is recommended.
However, this leads to a high value capacitor. Lower
values for CBAT capacitor can be used with respect to
some rules. In any case, the voltage at the VBB pin
should remain above VOFF when the device is turned
on.
The current peak at start-up (due to the fast charge of
the CREG and CBAT capacitors) may induce a
significant drop on the VBB pin. This drop is
proportional to the impedance of the VBAT connection
(see Figure 1-7).
The VBAT connection is mainly inductive and resistive.
Therefore, it can be modeled as a resistor (RTOT) in
series with an inductor (L). RTOT and L can be
measured.
The following formula gives an indication of the
minimum value of CBAT using RTOT and L:
EQUATION 1-4:
RTP VBATmin 5.5V–
250 mA
--------------------------------------
5.5V VOFF 1.0V+=
Where:
250 mA = Peak current at power-on when
VBB =5.5V
RTP VRECESSIVE
IREGMAX
----------------------------------
Where:
VRECESSIVE = Maximum variation tolerated on
the recessive level
RTP Slope
VBATmin 1V–
IREGMAX
---------------------------------------------------------------
Where:
Slope = Maximum variation tolerated on the
slope level
IREGMAX = Maximum current the current will
provide to the load
VBATmin >VOFF +1.0V
CBAT
CREG
--------------100L2RTOT
2
+
1L
2RTOT
2
100
-------------++
------------------------------------=
Where:
L = Inductor (measured in mH)
RTOT =RLINE +RTP (measured in )
MCP2021A/2A
DS20002298C-page 12 2012-2014 Microchip Technology Inc.
Equation 1-4 allows lower CBAT/CREG values than the
10x ratio we recommend.
Assume that we have a good quality VBAT connection
with RTOT =0.1 and L = 0.1 mH.
Solving the equation gives CBAT/CREG =1.
If we increase RTOT up to 1 the result becomes
CBAT/CREG = 1.4. However, if the connection is highly
resistive or highly inductive (poor connection), the
CBAT/CREG ratio greatly increases.
Figure 1-6 shows the minimum recommended
CBAT/CREG ratio as a function of the impedance of the
VBAT connection.
FIGURE 1-6: MINIMUM
RECOMMENDED
CBAT/CREG RATIO
TABLE 1-5: CBAT/CREG RATIO BY VBAT
CONNECTION TYPE
Connection
Type RTOT LCBAT/CREG
Ratio
Good 0.10.1 mH 1
Typical 10.1 mH 1.4
Highly inductive 0.11mH 7
Highly resistive 100.1 mH 7
10
CBAT/CREG
RBAT=0.1
RBAT=0.3
R
BAT
=1
1
10
0.1 1
CBAT/CREG
VBAT Line Inductance [mH]
RBAT=0.1
RBAT=0.3
BAT
R=1
RBAT=2
RBAT=4
RBAT=10
2012-2014 Microchip Technology Inc. DS20002298C-page 13
MCP2021A/2A
1.6 Typical Applicat ions
FIGURE 1-7: TYPICAL APPLICATION CIRCUIT
FIGURE 1-8: TYPICAL LIN NETWORK CONFIGURATION
LIN bus
MCP202XA
1k
VBB
40m
+ Return
LIN bus
LIN bus
MCP205X LIN bus
MCP202XA LIN bus
MCP2003
Slave 1
(MCU)
Slave 2
(MCU)
Slave n <16
(MCU)
Master
(MCU)
MCP2021A/2A
DS20002298C-page 14 2012-2014 Microchip Technology Inc.
1.7 ICSP™ Considerations
The following should be considered when the
MCP2021A/2A are connected to pins supporting
in-circuit programming:
• Power used for programming the microcontroller
can be supplied from the programmer or from the
MCP2021A/2A.
• The voltage on the VREG pin should not exceed
the maximum value of VREG in DC Specifications.
2012-2014 Microchip Technology Inc. DS20002298C-page 15
MCP2021A/2A
2.0 ELECTRICAL CHARACTERISTICS
2.1 Absolute Maximum Ratings†
VIN DC Voltage on RXD and RESET ................................................................................................. -0.3V to VREG +0.3
VIN DC Voltage on TXD, CS/LWAKE, FAULT/TXE ..........................................................................................-0.3 to +40V
VBB Battery Voltage, continuous, non-operating (Note 1)..............................................................................-0.3 to +40V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) (Note 2) .......................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-100V
VBB Battery Voltage, transient ISO 7637 Test 2a .....................................................................................................+75V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-150V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+100V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 3)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2) (Note 4).......................................................................................... ±15 kV
ESD protection on LIN, VBB (Human Body Model) (Note 5).................................................................................... ±8 kV
ESD protection on all other pins (Human Body Model) (Note 5) ............................................................................. ±4 kV
ESD protection on all pins (Charge Device Model) (Note 6) ................................................................................±1500V
ESD protection on all pins (Machine Model) (Note 7).............................................................................................±200V
Maximum Junction Temperature............................................................................................................................. 150C
Storage Temperature .................................................................................................................................. -65 to +150C
Note 1: LIN 2.x compliant specification.
2: SAE J2602-2 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330, 150 pF and Transceiver EMC Test Specifications [2] to [4].
5: According to AEC-Q100-002/JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003/JESD22-A115.
2.2 Nomenclature Used in This Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
† Not ice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
LIN 2.1 Name Term used in the following tables Definition
VBAT not used ECU operating voltage
VSUP VBB Supply voltage at device pin
VBUS_LIM ISC Current limit of driver
VBUSREC VIH(LBUS) Recessive state
VBUSDOM VIL(LBUS) Dominant state
MCP2021A/2A
DS20002298C-page 16 2012-2014 Microchip Technology Inc.
2.3 DC Specifications
DC Specifications Electrical Characteristics : Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA= -40°C to +125°C, CREG =10µF.
Parameter Sym Min Typ Max Units Conditions
Power
VBB Quiescent Operating
Current
IBBQ ——200µAIOUT =0mA
LBUS recessive
VREG =5.0V
——200µAIOUT =0mA
LBUS recessive
VREG =3.3V
VBB Ready Current IBBRD ——100µAIOUT =0mA
LBUS recessive
VREG =5.0V
——100µAIOUT =0mA
LBUS recessive
VREG =3.3V
VBB Transmitter-Off Current IBBTO — — 100 µA With voltage regulator on,
transmitter off, receiver
on, FAULT/TXE =VIL,
CS = VIH, VREG =5.0V
— — 100 µA With voltage regulator on,
transmitter off, receiver
on, FAULT/TXE =VIL,
CS = VIH, VREG =3.3V
VBB Power-Down Current IBBPD — 4.5 8 µA With voltage regulator off,
receiver on and
transmitter off,
FAULT/TXE =VIH,
TXD =VIH, CS = VIL
VBB Current with VSS
Floating
IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB,
VLIN =0–18V
Microcontroller Interface
High-Level Input Voltage
(TXD, FAULT/TXE)
VIH 2.0 — VREG
+0.3
V
Low-Level Input Voltage
(TXD, FAULT/TXE)
VIL -0.3 — 0.8 V
High-Level Input Current
(TXD, FAULT/TXE)
IIH -2.5 — 0.4 µA Input voltage = 4.0V
~800 k internal adaptive
pull-up
Low-Level Input Current
(TXD, FAULT/TXE)
IIL -10 — — µA Input voltage = 0.5V
~800 k internal adaptive
pull-up
High-Level Input Voltage
(CS/LWAKE)
VIH 2.0 — VBB V Through a current-limiting
resistor
Low-Level Input Voltage
(CS/LWAKE)
VIL -0.3 — 0.8 V
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS =0W, TX=0, VLBUS =VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled. VWK(LBUS) is used to detect
bus activities.
2012-2014 Microchip Technology Inc. DS20002298C-page 17
MCP2021A/2A
High-Level Input Current
(CS/LWAKE)
IIH — — 8.0 µA Input voltage = 0.8VREG
~1.3 M internal
pull-down to VSS
Low-Level Input Current
(CS/LWAKE)
IIL — — 5.0 µA Input voltage = 0.2VREG
~1.3 M internal
pull-down to VSS
Low-Level Output Voltage
(RXD)
VOLRXD — — 0.2VREG VIOL =2mA
High-Level Output Voltage
(RXD)
VOHRXD 0.8VREG —— VIOH =2mA
Low-Level Output Voltage
(FAULT/TXE)
VOLOD ——1.0VIOL =4mA
Low-Level Output Voltage
(RESET)
VOLRST ——1.0VIOL =4mA
Bus Interface
High-Level Input Voltage VIH(LBUS) 0.6 VBB — — V Recessive state
Low-Level Input Voltage VIL(LBUS)-8—0.4 VBB V Dominant state
Input Hysteresis VHYS — — 0.175 VBB VVIH(LBUS)–VIL(LBUS)
Low-Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB,
VBB = 12V
Pull-Up Current on Input IPU(LBUS)-180—-72µA~30k internal pull-up
@ VIH(LBUS)=0.7VBB,
VBB = 12V
Short Circuit Current Limit ISC 50 — 200 mA Note 1
High-Level Output Voltage VOH(LBUS)0.8VBB —VBB V
Driver Dominant Voltage V_LOSUP ——1.1VVBB =7.3V
RLOAD = 1000
V_HISUP ——1.2VVBB = 18V
RLOAD = 1000
Input Leakage Current
(at the receiver during
dominant bus level)
IBUS_PAS_DOM -1 — — mA Driver off
VBUS =0V
VBB = 12V
Input Leakage Current
(at the receiver during
recessive bus level)
IBUS_PAS_REC -20 — 20 µA Driver off
8V < VBB < 18V
8V < VBUS <18V
VBUS VBB
Leakage Current
(disconnected from ground)
IBUS_NO_GND -10 — +10 µA GNDDEVICE =VBB
0V < VBUS <18V
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_PWR -10 — +10 µA VBB =GND
0<V
BUS < 18V
Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5
VBB
0.525 VBB VVBUS_CNT =(VIL(LBUS)+
VIH(LBUS))/2
Slave Termination RSLAVE 20 30 47 kNote 2
2.3 DC Specifications (Continued)
DC Specifications Electrical Characteristics : Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA= -40°C to +125°C, CREG =10µF.
Parameter Sym Min Typ Max Units Conditions
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS =0W, TX=0, VLBUS =VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled. VWK(LBUS) is used to detect
bus activities.
MCP2021A/2A
DS20002298C-page 18 2012-2014 Microchip Technology Inc.
Capacitance of Slave Node CSLAVE ——50pFNote 2
Wake-Up Voltage
Threshold on LIN Bus
VWK(LBUS) — — 3.4 V Wake-up from
Power-Down mode
(Note 3)
Volta ge Regula tor – 5.0V
Output Voltage Range VREG 4.85 5.00 5.15 V 0 mA < IOUT <70mA
Line Regulation VOUT1—1050mVIOUT =1mA
6.0V < VBB <18V
Load Regulation VOUT2—1050mV5mA<IOUT <70mA
6.0V < VBB <12V
Power Supply Ripple Reject PSRR — — 50 dB 1 VPP @ 10–20kHz
ILOAD =20mA
Output Noise Voltage eN — — 100 µVRM
S
10Hz–40MHz
CFILTER =10µf
CBP =0.1µf
ILOAD =20mA
Shutdown Voltage
Threshold
VSD 3.5 — 4.0 V See Figure 1-5 (Note 2)
Input Voltage to
Turn-Off Output
VOFF 3.9 — 4.5 V
Input Voltage to
Turn-On Output
VON 5.25 — 6.0 V
Volta ge Regula tor – 3.3V
Output Voltage VREG 3.20 3.30 3.40 V 0 mA < IOUT <70mA
Line Regulation VOUT1—1050mVIOUT =1mA
6.0V < VBB <18V
Load Regulation VOUT2—1050mV5mA<IOUT <70mA
6.0V < VBB <12V
Power Supply Ripple Reject PSRR — — 50 dB 1 VPP @ 10–20kHz
ILOAD =20mA
Output Noise Voltage eN — — 100 µVRM
S/Hz
10Hz–40MHz
CFILTER =10µf
CBP =0.1µf
ILOAD =20mA
Shutdown Voltage
Threshold
VSD 2.5 — 2.7 V See Figure 1-5 (Note 2)
Input Voltage to
Turn-Off Output
VOFF 3.9 — 4.5 V
Input Voltage to
Turn-On Output
VON 5.25 — 6 V
2.3 DC Specifications (Continued)
DC Specifications Electrical Characteristics : Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V, TA= -40°C to +125°C, CREG =10µF.
Parameter Sym Min Typ Max Units Conditions
Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS =0W, TX=0, VLBUS =VBB).
2: Characterized, not 100% tested.
3: In Power-Down mode, normal LIN recessive/dominant threshold is disabled. VWK(LBUS) is used to detect
bus activities.
2012-2014 Microchip Technology Inc. DS20002298C-page 19
MCP2021A/2A
FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION
Load Capacitor [uF]
ESR Curves
ESR [ohm]
10
1
0.1
0.01
0.001
10 100 1000
10.1
Instable
Instable
Instable
Stable only
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Unstable
U
nstable
Unstable
Load Capacitance [uF]
Note 1: The graph shows the minimum required capacitance after derating due to tolerance, temperature and
voltage.
MCP2021A/2A
DS20002298C-page 20 2012-2014 Microchip Technology Inc.
2.4 AC Specifications
AC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V; TA= -40°C to +125°C.
Parameter Sym Min Typ Max Units Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling
Edges
tSLOPE 3.5 — 22.5 µs 7.3V VBB 18V
Propagation Delay of
Transmitter
tTRANSPD ——5.0µstTRANSPD =max.
(tTRANSPDR or tTRANSPDF)
Propagation Delay of
Receiver
tRECPD ——6.0µstRECPD =max.
(tRECPDR or tRECPDF)
Symmetry of Propagation
Delay of Receiver Rising
Edge w.r.t. Falling Edge
tRECSYM -2.0 — 2.0 µs tRECSYM =max.
(tRECPDF –tRECPDR)
RRXD =2.4kto VCC
CRXD =20pF
Symmetry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
tTRANSSYM -2.0 — 2.0 µs tTRANSSYM =max.
(tTRANSPDF –tTRANSPDR)
Bus Dominant Time-Out
Time
tTO(LIN)— 25 —ms
Time to Sample FAULT/TXE
for Bus Conflict Reporting
tFAULT ——32.5µstFAULT =max.
(tTRANSPD +tSLOPE +tRECPD)
Duty Cycle 1 @ 20.0 kbps 0.396 — — %tBIT CBUS; RBUS conditions:
1nF; 1k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.744 x VBB,
THDOM(MAX)=0.581xVBB,
VBB =7.0V–18V;
tBIT =50µs.
D1 = tBUS_REC(MIN)/2 x tBIT
Duty Cycle 2 @ 20.0 kbps — — 0.581 %tBIT CBUS; RBUS conditions:
1nF; 1k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.284 x VBB,
THDOM(MAX)=0.422xVBB,
VBB =7.6V–18V;
tBIT =50µs.
D2 = tBUS_REC(MAX)/2 x tBIT
Duty Cycle 3 @ 10.4 kbps 0.417 — — %tBIT CBUS; RBUS conditions:
1nF; 1k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.778 x VBB,
THDOM(MAX)=0.616xVBB,
VBB =7.0V–18V;
tBIT =96µs.
D3 = tBUS_REC(MIN)/2 x tBIT
Note 1: Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load.
2: Characterized, not 100% tested.
2012-2014 Microchip Technology Inc. DS20002298C-page 21
MCP2021A/2A
Duty Cycle 4 @ 10.4 kbps — — 0.590 %tBIT CBUS; RBUS conditions:
1nF; 1k | 6.8 nF;
660 | 10 nF; 500
THREC(MAX) = 0.251 x VBB,
THDOM(MAX)=0.389xVBB,
VBB =7.6V–18V;
tBIT =96µs.
D4 = tBUS_REC(MAX)/2 x tBIT
Volta ge Regula tor
Bus Activity Debounce time tBDB 30 80 250 µs
Bus Activity to Voltage
Regulator Enabled
tBACTIVE 35 — 200 µs
Voltage Regulator Enabled
to Ready
tVEVR 300 — 1200 µs Note 1
Chip Select to Ready Mode tCSR — — 230 µs
Chip Select to Power-Down tCSPD — — 330 µs Note 2
Short Circuit to Shutdown tSHUTDOWN 20 — 100 µs
RESET Timing
VREG OK Detect to RESET
Inactive
tRPU ——60µs
VREG Not OK Detect to
RESET Active
tRPD ——60µs
2.5 Thermal S pecifications
Parameter Sym Min Typ Max Units Test Conditions
Specified Temperature Range TA-40 — +125 C
Maximum Junction Temperature TJ——+150C
Storage Temperature Range TA-65 — +150 C
Recovery Temperature RECOVERY —+140— C
Shutdown Temperature SHUTDOWN —+150— C
Short Circuit Recovery Time tTHERM —1.55.0ms
Thermal Package Resistances
Thermal Resistance, 8L-PDIP JA —89.3 —C/W
Thermal Resistance, 8L-SOIC JA —149.5 —C/W
Thermal Resistance, 8L-DFN JA —48 —C/W
Thermal Resistance, 14L-PDIP JA —70 —C/W
Thermal Resistance, 14L-SOIC JA —90.8 —C/W
Thermal Resistance, 14L-TSSOP JA —100 —C/W
Note 1: The maximum power dissipation is a function of TJMAX, JA, and ambient temperature, TA. The maximum
allowable power dissipation at an ambient temperature is PD=(TJMAX –TA) JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the MCP2021A/2A will go into thermal shutdown.
2.4 AC Specifications (Continued)
AC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 6.0V to 18.0V; TA= -40°C to +125°C.
Parameter Sym Min Typ Max Units Conditions
Note 1: Time depends on external capacitance and load. Test condition: CREG = 4.7 µF, no resistor load.
2: Characterized, not 100% tested.
MCP2021A/2A
DS20002298C-page 22 2012-2014 Microchip Technology Inc.
2.6 Typical Performance Curves
Note: Unless otherwise indicated, VBB = 6.0V to 18.0V; TA= -40°C to +125°C.
FIGURE 2-2: Typical IBBQ vs .
Temperature – 5.0V.
FIGURE 2-3: Typical IBBTO vs.
Temperature – 5.0V.
FIGURE 2-4: Typical IPD vs. Temperature
– 5.0V.
FIGURE 2-5: Typical IBBQ vs.
Temperature – 3.3V.
FIGURE 2-6: Typical IBBTO vs.
Temperature – 3.3V.
FIGURE 2-7: Typical IPD vs. Temperature
– 3.3V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
80
100
120
140
160
180
200
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBQ (μA)
Temperature (ͼ
ͼ
C)
VBB = 6V
VBB = 12V
VBB = 18V
50
60
70
80
90
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBTQ (μA)
Temperature (ͼC)
VBB = 6V
VBB = 12V
VBB = 18V
4
4.2
4.4
4.6
4.8
5
5.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
IPD (μA)
Temperature (ͼC)
VBB = 6V VBB = 12V
VBB = 18V
80
100
120
140
160
180
200
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBQ (μA)
Temperature (ͼC)
VBB = 6V
VBB = 18V
VBB = 12V
50
60
70
80
90
100
-40 -25 -10 5 20 35 50 65 80 95 110 125
IBBTO (μA)
Temperature (ͼC)
VBB = 6V
VBB = 18V
VBB = 12V
4
4.2
4.4
4.6
4.8
5
5.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (ͼC)
IPD (μA)
VBB = 6V
VBB = 18V
VBB = 12V
2012-2014 Microchip Technology Inc. DS20002298C-page 23
MCP2021A/2A
FIGURE 2-8: 5.0V VREG vs. IREG at
VBB =12V.
FIGURE 2-9: 3.3V VREG vs. IREG at
VBB =12V.
0
1
2
3
4
5
6
0 100 200 300
VREG (V)
IREG (mA)
-40°C
+125°C
+90°C +25°C
0
0.5
1
1.5
2
2.5
3
3.5
0 100 200 300
IREG (mA)
VREG (V)
-40°C
+125°C
+90°C +25°C
MCP2021A/2A
DS20002298C-page 24 2012-2014 Microchip Technology Inc.
2.7 Timing Diagrams and Specifications
FIGURE 2-10: BUS TIMING DIAGRAM
FIGURE 2-11 : REGULATOR CS/LWAKE TIMING DIAGRAM
0.95 VLBUS
0.05 VLBUS
tTRANSPDR
tRECPDR
tTRANSPDF
tRECPDF
TXD
LBUS
RXD
Internal TXD/RXD
Compare
FAULT Sampling
tFAULT tFAULT
FAULT/TXE Output Stable Stable
Stable
Match Match
Match Match Match
Hold
Value
Hold
Value
50%
50%
0.50 VBB
50%
50%
0.0V
VREG
LBUS
VWK(LBUS)
tVEVR
VREG-NOM
tBDB tBACTIVE
2012-2014 Microchip Technology Inc. DS20002298C-page 25
MCP2021A/2A
FIGURE 2-12: CS/LWAKE, REGULATOR AND RESET TIMING DIAGRAM
tCSPD
tCSR
CS/LWAKE
VREG
VREG-NOM
RESET
tRPU
tVEVR
tRPD
MCP2021A/2A
DS20002298C-page 26 2012-2014 Microchip Technology Inc.
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
NNN
8-Lead SOIC (150 mil) (MCP2021A) Example
2021A50E
SN ^^1409
256
3
e
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) (MCP2021A) Example
YYWW
NNN
XXXXXX
XXXXXX
PIN 1 PIN 1
2021A
500EMD
1409
256
8-Lead
DFN (4x4x0.9 mm)
(MCP2021A) Example
2021A500
E/P ^^256
1409
3
e
2012-2014 Microchip Technology Inc. DS20002298C-page 27
MCP2021A/2A
Package Marking Information (Continued)
14-Lead SOIC (.150”) (MC2022A) Example
14-Lead TSSOP (MCP2022A)
MCP2022A
500E/SL ^^
1409256
3
e
YYWW
NNN
XXXXXXXX
2022A500
1409
256
14-Lead PDIP (300 mil) (MCP2022A) Example
Example
MCP2022A
500E/P ^^
1409256
3
e
MCP2021A/2A
DS20002298C-page 28 2012-2014 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
2012-2014 Microchip Technology Inc. DS20002298C-page 29
MCP2021A/2A
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
MCP2021A/2A
DS20002298C-page 30 2012-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc. DS20002298C-page 31
MCP2021A/2A
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
MCP2021A/2A
DS20002298C-page 32 2012-2014 Microchip Technology Inc.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
2012-2014 Microchip Technology Inc. DS20002298C-page 33
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS20002298C-page 34 2012-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc. DS20002298C-page 35
MCP2021A/2A
 !"#$%
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MCP2021A/2A
DS20002298C-page 36 2012-2014 Microchip Technology Inc.
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N
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E
c
eB
A2
L
A
A1 b1
be
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2012-2014 Microchip Technology Inc. DS20002298C-page 37
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS20002298C-page 38 2012-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc. DS20002298C-page 39
MCP2021A/2A
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MCP2021A/2A
DS20002298C-page 40 2012-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc. DS20002298C-page 41
MCP2021A/2A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2021A/2A
DS20002298C-page 42 2012-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2014 Microchip Technology Inc. DS20002298C-page 43
MCP2021A/2A
APPENDIX A: REVISI ON HISTORY
Revision C (July 2014)
The following is the list of modifications:
1. Updated Section 1.6 “Typical Applications”
with values used during ESD tests.
2. Minor typographical corrections.
3. Updated 8-Lead PDIP Package.
Revision B (December 2013)
The following is the list of modifications:
1. Removed two notes in AC Specifications.
2. Updated Figure 1-3.
3. Added pull-up to FAULT/TXE pin in the pin
description and typical applications.
4. Revised product identification examples for
SOIC package.
Revision A (March 2012)
• Original Release of this Document.
MCP2021A/2A
DS20002298C-page 44 2012-2014 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP2021A: LIN Transceiver with Voltage Regulator
MCP2021AT: LIN Transceiver with Voltage Regulator
(Tape and Reel)
MCP2022A: LIN Transceiver with Voltage Regulator
MCP2022AT: LIN Transceiver with Voltage Regulator
(Tape and Reel)
Voltage: 330 = 3.3V
500 = 5.0V
Temperature Range: E = -40°C to +125°C
Package: MD = 8LD Plastic Dual Flat, No Lead – 4x4x0.8 mm
Body
P = 8LD/14LD Plastic Dual In-Line – 300 mil Body
SN = 8LD Plastic Small Outline – Narrow, 3.90 mm
Body
SL = 14LD Plastic Small Outline – Narrow, 3.90 mm
Body
ST = 14LD Plastic Thin Shrink Small Outline – 4.4 mm
Body
PART NO. –X /XX
PackageVoltage
Device
Examples:
a) MCP2021A-330E/MD: 3.3V, 8-lead DFN package
b) MCP2021A-500E/MD: 5.0V, 8-lead DFN package
c) MCP2021AT-330E/MD: 3.3V, 8-lead DFN package,
Tape and Reel
d) MCP2021AT-500E/MD: 5.0V, 8-lead DFN package,
Tape and Reel
e) MCP2021A-330E/P: 3.3V, 8-lead PDIP package
f) MCP2021A-500E/P: 5.0V, 8-lead PDIP package
g) MCP2021A-330E/SN: 3.3V, 8-lead SOIC package
h) MCP2021AT-330E/SN: 3.3V, 8-lead SOIC package,
Tape and Reel
i) MCP2021A-500E/SN: 5.0V, 8-lead SOIC package
j) MCP2021AT-500E/SN: 5.0V, 8-lead SOIC package,
Tape and Reel
a) MCP2022A-330E/P: 3.3V, 14-lead PDIP package
b) MCP2022A-500E/P: 5.0V, 14-lead PDIP package
c) MCP2022A-330E/SL: 3.3V, 14-lead SOIC package
d) MCP2022AT-330E/SL: 3.3V, 14-lead SOIC package,
Tape and Reel
e) MCP2022A-500E/SL: 5.0V, 14-lead SOIC package
f) MCP2022AT-500E/SL: 5.0V, 14-lead SOIC package,
Tape and Reel
g) MCP2022A-330E/ST: 3.3V, 14-lead TSSOP package
h) MCP2022AT-330E/ST: 3.3V, 14-lead TSSOP package,
Tape and Reel
i) MCP2022A-500E/ST: 5.0V, 14-lead TSSOP package
j) MCP2022AT-500E/ST: 5.0V, 14-lead TSSOP package,
Tape and Reel
–X
Temperature
Range
2012-2014 Microchip Technology Inc. DS20002298C-page 45
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-403-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hoppin g
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20002298C-page 46 2012-2014 Microchip Technology Inc.
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Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Ka ohs iung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
03/25/14