DAC8802
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FEATURES DESCRIPTION
APPLICATIONS
14
DAC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
EN
A
B
Decode
SDI
CLK
DGND MSB
R A
FB
V A B
REF
R B
FB
I A
OUT
A A
GND
A B
GND
I B
OUT
Input
Register
Input
Register
DAC A
Register
DACB
Register
R
R
Power-On
Reset
R
R
DAC A
DACB
CS
RS LDAC
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
Dual, Serial Input 14-Bit Multiplying Digital-to-Analog Converter
•Relative Accuracy: 1 LSB Max
The DAC8802 is a dual, 14-bit, current-outputdigital-to-analog converter (DAC) designed to•Differential Nonlinearity: 1 LSB Max
operate from a single 2.7 V to 5.5 V supply.•2-mA Full-Scale Current ±20%,with V
REF
=±10 V
The applied external reference input voltage V
REFdetermines the full-scale output current. An internal•0.5 µs Settling Time
feedback resistor (R
FB
) provides temperature•Midscale or Zero-Scale Reset
tracking for the full-scale output when combined with•Separate 4Q Multiplying Reference Inputs
an external I-to-V precision amplifier.•Reference Bandwidth: 10 MHz
A doubled-buffered, serial data interface offers•Reference Dynamics: –105 dB THD
high-speed, 3-wire, SPI and microcontrollercompatible inputs using serial data in (SDI), clock•SPI™-Compatible 3-Wire Interface:
(CLK), and a chip-select ( CS). A common50 MHz
level-sensitive load DAC strobe ( LDAC) input allows•Double Buffered Registers to Enable
simultaneous update of all DAC outputs fromSimultaneous Multichannel Update
previously loaded input registers. Additionally, aninternal power-on reset forces the output voltage to•Internal Power-On Reset
zero at system turn-on. An MSB pin allows system•Industry-Standard Pin Configuration
reset assertion ( RS) to force all registers to zerocode when MSB = 0, or to half-scale code whenMSB = 1.•Automatic Test Equipment
The DAC8802 is available in an TSSOP-16 package.•Instrumentation
•Digitally Controlled Calibration
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI is a trademark of Motorola, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
RELATIVE DIFFERENTIAL SPECIFIED TRANSPORTACCURACY NONLINEARITY TEMPERATURE PACKAGE- PACKAGE ORDERING MEDIA,PRODUCT (LSB) (LSB) RANGE LEAD DESIGNATOR NUMBER QUANTITY
DAC8802IPW Tubes, 90DAC8802 ±1±1 –40°C to 85°C TSSOP-16 PW
DAC8802IPWR Tape and Reel, 2500
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, orsee the TI website at www.ti.com .
DAC8802 UNIT
V
DD
to GND –0.3 to 7 VV
REF
X, R
FB
X to GND –18 to 18 VDigital logic inputs to GND – 0.3 to + V
DD
+ 0.3 VV(I
OUT
) to GND – 0.3 to V
DD
+ 0.3 VA
GND
X to DGND –0.3 to +0.3 VInput current to any pin except supplies ±50 mAPackage power dissipation (T
J
max – T
A
)/ θ
JA
WThermal resistance, θ
JA
100 °C/WMaximum junction temperature (T
J
max) 150 °COperating temperature range – 40 to 85 °CStorage temperature range – 65 to 150 °CHBM 4 kVESD
CDM 1 kV
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationis not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
(1)
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unlessotherwise noted.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
(2)
Resolution 14 BitsRelative accuracy INL ±1 LSBDifferential nonlinearity DNL ±1 LSBData = 0000h, T
A
= 25 °C 10 nAOutput leakage current I
OUT
X
Data = 0000h, T
A
= T
A
max 20 nAFull-scale gain error G
FSE
Data = 3FFFh ±0.75 ±4 mVFull-scale tempco
(3)
TCV
FS
1 ppm/ °CFeedback resistor R
FB
X V
DD
= 5 V 5 k Ω
REFERENCE INPUT
(3)
V
REF
X Range V
REF
X –15 15 VInput resistance R
REF
X 4 5 6 k ΩInput resistance match R
REF
X Channel-to-channel 1 %Input capacitance C
REF
X 5 pF
ANALOG OUTPUT
(3)
Output current I
OUT
X Data = 3FFFh 1.6 2.5 mAOutput capacitance C
OUT
X Code-dependent 50 pF
LOGIC INPUTS
(3)
V
DD
= 2.7 V 0.6 VInput low voltage V
IL
V
DD
= 5 V 0.8 VV
DD
= 2.7 V 2.1 VInput high voltage V
IH
V
DD
= 5 V 2.4 VInput leakage current I
IL
1µAInput capacitance C
IL
10 pF
INTERFACE TIMING
(4)
Clock width high t
CH
10 nsClock width low t
CL
10 nsCS to Clock setup t
CSS
0 nsClock to CS hold t
CSH
10 nsClock to SDO prop delay t
PD
2 20 nsLoad DAC pulsewidth t
LDAC
20 nsData setup t
DS
10 nsData hold t
DH
10 nsLoad setup t
LDS
5 nsLoad hold t
LDH
25 ns
(1) Specifications subject to change without notice.(2) All static performance tests (except I
OUT
) are performed in a closed-loop system using an external precision OPA277 I-to-V converteramplifier. The DAC8802 R
FB
terminal is tied to the amplifier output. Typical values represent average readings measured at +25 °C.(3) These parameters are specified by design and not subject to production testing.(4) All input control signals are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
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PARAMETER MEASUREMENT INFORMATION
SDI
CLK
CS
LDAC
tCS S tds tdh tch tcl
tcsh
Input REG. LD
tlds
tLDAC
tLDH
A1 A0 D13 D12 D11 D10 D1 D0
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)V
DD
= 2.7 V to 5.5 V, I
OUT
X = Virtual GND, A
GND
X = 0 V, V
REF
A, B = 10 V, T
A
= full operating temperature range, unlessotherwise noted.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
Power supply range V
DD RANGE
2.7 5.5 VLogic inputs = 0 V, V
DD
= 4.5 V to 5.5 V 2 5 µAPositive supply current I
DD
Logic inputs = 0 V, V
DD
= 2.7 V to 3.6 V 1 2.5 µAPower dissipation P
DISS
Logic inputs = 0 V 0.0275 mWPower supply sensitivity P
SS
∆V
DD
=±5% 0.006 %
AC CHARACTERISTICS
(5) (6)
To ±0.1% of full-scale, µs0.3Data = 0000h to 3FFFh to 0000hOutput voltage settling time t
s
To ±0.006% of full-scale, µs0.5Data = 0000h to 3FFFh to 0000hReference multiplying BW BW –3 dB V
REF
X = 100 mV
RMS
, Data = 3FFFh, C
FB
= 3 pF 10 MHzDAC glitch impulse Q V
REF
X = 10 V, Data = 1FFFh to 2000h to 1FFFh 5 nV/sFeedthrough error V
OUT
X/V
REF
X Data = 0000h, V
REF
X = 100 mV
RMS
, f = 100 kHz –70 dBData = 0000h, V
REF
B = 100 mV
RMS
, dBCrosstalk error V
OUT
A/V
REF
B –100Adjacent channel, f = 100 kHzDigital feedthrough Q CS = 1 and f
CLK
= 1 MHz 1 nV/sTotal harmonic distortion THD V
REF
= 5 V
PP
, Data = 3FFFh, f = 1 kHz –105 dBOutput spot noise voltage e
n
f = 1 kHz, BW = 1 Hz 12 nV/ √Hz
(5) These parameters are specified by design and not subject to production testing.(6) All ac characteristic tests are performed in a closed-loop system using an THS4011 I-to-V converter amplifier.
Figure 1. DAC8802 Timing Diagram
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PIN CONFIGURATIONS
1
2
3
4
5
6
7
89
10
11
12
13
14
16
15
DGND
DAC8802
(TOP VIEW)
AGNDA
IOUTA
VREFA
RFBA
RFBB
VREFB
IOUTB
AGNDB
LDAC
MSB
RS
VDD
CS
CLK
SDI
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
PIN DESCRIPTION
PIN NAME DESCRIPTION
1 R
FB
A Establish voltage output for DAC A by connecting to external amplifier output.2 V
REF
A DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage. Can be tied to V
DD
pin.3 I
OUT
A DAC A Current output.4 A
GND
A DAC A Analog ground.5 A
GND
B DAC B Analog ground.6 I
OUT
B DAC B Current output.7 V
REF
B DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage. Can be tied to V
DD
pin.8 R
FB
B Establish voltage output for DAC B by connecting to external amplifier output.9 SDI Serial data input; data loads directly into the shift register.Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale. Register data =10 RS
0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for DAC8802.Chip-select; active low input. Disables shift register loading when high. Transfers serial register data to input11 CS
register when CS goes high. Does not affect LDAC operation.12 DGND Digital ground.13 V
DD
Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.MSB bit sets output to either 0 or midscale during a RESET pulse ( RS) or at system power-on. Output equals14 MSB
zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or V
DD
.Load DAC register strobe; level sensitive active low. Transfers all input register data to the DAC registers.15 LDAC
Asynchronous active low input. See Table 2 for operation.16 CLK Clock input. Positive edge clocks data into shift register.
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TYPICAL CHARACTERISTICS: V
DD
= 5 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA= 40°C-
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+85°C
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
At T
A
= 25°C, +V
DD
= 5 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 2. Figure 3.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 4. Figure 5.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 6. Figure 7.
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Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+85°C
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)At T
A
= 25°C, +V
DD
= 5 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 8. Figure 9.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 10. Figure 11.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 12. Figure 13.
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6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
10 100 1k 10k 100k 1M 10M 100M
Attenuation(dB)
Bandwidth(Hz)
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
0x0080
0x0100
0x0200
0x0400
0x0800
0x1000
0x2000
0x3FFF
0x0000
Time(0.2 s/div)m
OutputVoltage(50mV/div)
LDACPulse
Code:1FFFhto2000h
Time(0.1 s/div)m
OutputVoltage(5V/div)
TriggerPulse
VoltageOutputSettling
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: V
DD
= 5 V (continued)At T
A
= 25°C, +V
DD
= 5 V, unless otherwise noted.
SUPPLY CURRENTvs LOGIC INPUT VOLTAGE REFERENCE MULTIPLYING BANDWIDTH
Figure 14. Figure 15.
DAC GLITCH DAC SETTLING TIME
Figure 16. Figure 17.
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TYPICAL CHARACTERISTICS: V
DD
= 2.7 V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+85°C
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
At T
A
= 25°C, +V
DD
= 2.7 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 18. Figure 19.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 20. Figure 21.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 22. Figure 23.
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Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
INL(LSB)
Code
TA=+85°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 2048 4096 6144 8192 10240 12288 14336 16383
DNL(LSB)
Code
TA=+85°C
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS: V
DD
= 2.7 V (continued)At T
A
= 25°C, +V
DD
= 2.7 V, unless otherwise noted.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 24. Figure 25.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 26. Figure 27.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 28. Figure 29.
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THEORY OF OPERATION
CIRCUIT OPERATION
Digital-to-Analog Converters
R R R
2R 2R 2R R 5 kΩ
S2 S1
DGND
VREFX
VDD
RFBX
IOUTX
AGNDX
Digitalinterface onnectionsareomittedforclarity.
SwitchesS1andS2areclosed;V mustbepowered.
DD
c
VOUT + *VREF D
16384
(1)
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
The DAC8802 contains two 14-bit, current-output, digital-to-analog converters (DACs). Each DAC has its ownindependent multiplying reference input. The DAC8802 uses a 3-wire, SPI-compatible serial data interface, witha configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, anLDAC strobe enables two-channel simultaneous updates for hardware-synchronized output voltage changes.
The DAC8802 contains two current-steering R-2R ladder DACs. Figure 30 shows a typical equivalent DAC.Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R
FB
Xpin is connected to the output of the external amplifier. The I
OUT
X terminal is connected to the inverting input ofthe external amplifier. The A
GND
X pin should be Kelvin-connected to the load point in the circuit requiring the full14-bit accuracy.
Figure 30. Typical Equivalent DAC Channel
The DAC is designed to operate with both negative or positive reference voltages. The V
DD
power pin is onlyused by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with theinternal 5 k Ωfeedback resistor. If users are attempting to measure the value of R
FB
, power must be applied toV
DD
in order to achieve continuity. The DAC output voltage is determined by V
REF
and the digital data (D)according to Equation 1 :
Note that the output polarity is opposite of the V
REF
polarity for dc reference voltages.
The DAC is also designed to accommodate ac reference input signals. The DAC8802 accommodates inputreference voltages in the range of -15 V to 15 V. The reference voltage inputs exhibit a constant nominal inputresistance of 5 k Ω, ±20%. On the other hand, DAC outputs I
OUT
A and B are code-dependent and producevarious output resistances and capacitances.
The choice of external amplifier should take into account the variation in impedance generated by the DAC8802on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,dominates output voltage noise. For multiplying mode applications, an external feedback compensationcapacitor, C
FB
(4 pF to 20 pF typical), may be needed to provide a critically damped output response for stepchanges in reference input voltages.
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IOUTX
+
+
DGND
VDD
RFBX
AGNDX
Analog
Power
Supply
Load
15 V
2R
5 V
R
15 V
VEE
VCC
VOUT
A1
DGND
VREFX
RRR
2R 2R 2R R 5 kΩ
S2 S1
Digitalinterface onnectionsareomittedforclarity.
SwitchesS1andS2areclosed;V mustbepowered.
DD
c
14
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
A
B
DAC
Decode
Input
Register
Input
Register
DACA
Register
DACB
Register
R
R
R
R
DACA
DACB
Set
MSB
Set
MSB
Power-On
Reset
DGND MSB LDAC RS
VDD
V AB
REF
R A
FB
I A
OUT
A A
GND
A B
GND
I B
OUT
R B
FB
CS
CLK
SDI
EN
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
Figure 15 shows the gain vs frequency performance at various attenuation settings using a 3 pF externalfeedback capacitor connected across the I
OUT
X and R
FB
X terminals. In order to maintain good analogperformance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under theseconditions, a clean power supply with low ripple voltage capability should be used. Switching power supplies isusually not suitable for this application due to the higher ripple voltage and P
SS
frequency-dependentcharacteristics. It is best to derive the DAC8802 5-V supply from the system analog supply voltages (do not usethe digital 5-V supply); see Figure 31 .
Figure 31. Recommended Kelvin-Sensed Hookup
Figure 32. System Level Digital Interfacing
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SERIAL DATA INTERFACE
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
The DAC8802 uses a 3-wire ( CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8802 isclocked into the serial input register in an 16-bit data-word format. MSB bits are loaded first. Table 1 defines the16 data-word bits for the DAC8802.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the datasetup and data hold time requirements specified in the Interface Timing specifications of the ElectricalCharacteristics . Data can only be clocked in while the CS chip select pin is active low. For the DAC8802, onlythe last 16 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to theDAC8802. Keeping the CS line low between the first and second byte transfer will result in a successful serialregister update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of newdata to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8802,Table 1 ,Table 2 ,Table 3 , and Figure 1 define the characteristics of the software serial interface.
Table 1. Serial Input Register Data Format, Data Loaded MSB First
(1)
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB)
Data A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(1) Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns tologic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D13-D0) to the decodedDAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8802 shift register are ignored; only thelast 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 2. Control Logic Truth Table
(1)
CS CLK LDAC RS MSB SERIAL SHIFT REGISTER INPUT REGISTER DAC REGISTER
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L↑+ H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
↑+ L H H X No effect Selected DAC updated with current SR contents Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X ↑+ H X No effect Latched Latched
H X H L 0 No effect Latched data = 0000h Latched data = 0000h
H X H L H No effect Latched data = 2000h Latched data = 2000h
(1) ↑+= Positive logic transition; X= Do not care
Table 3. Address DecodeA1 A0 DAC DECODE
0 0 None
0 1 DAC A
1 0 DAC B
1 1 DAC A and DAC B
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A
B
Address
Decoder
Shift Register
EN
To Input Register
CS
CLK
SDI
POWER ON RESET
ESD Protection Circuits
VDD
250 W
DGND
DIGITAL
INPUTS
PCB LAYOUT
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
Figure 33 shows the equivalent logic interface for the key digital control pins for the DAC8802.
Figure 33. DAC8802 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. Ifthese functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces allinput and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
When the V
DD
power supply is turned on, an internal reset strobe forces all the Input and DAC registers to thezero-code state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smoothpositive ramp without drooping, in order to have consistent results, especially in the region of V
DD
= 1.5 V to2.3 V. The DAC register data stays at the zero or half-scale setting until a valid serial register data load takesplace.
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V
DD
, asshown in Figure 34 .
Figure 34. Equivalent ESD Protection Circuits
The DAC8802 is a high-accuracy DAC that can have its performance compromised by grounding and printedcircuit board (PCB) lead trace resistance. The 14-bit DAC8802 with a 10-V full-scale range has an LSB value of610 µV. The ladder and associated reference and analog ground currents for a given channel can be as high as2 mA. With this 2 mA current level, a series wiring and connector resistance of only 305 m Ωwill cause 1 LSB ofvoltage drop. The preferred PCB layout for the DAC8802 is to have all A
GND
X pins connected directly to ananalog ground plane at the unit. The noninverting input of each channel I/V converter should also either connectdirectly to the analog ground plane or have an individual sense trace back to the A
GND
X pin connection. Thefeedback resistor trace to the I/V converter should also be kept short and low resistance to prevent IR dropsfrom contributing to gain error. This attention to wiring ensures the optimal performance of the DAC8802.
14
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APPLICATION INFORMATION
VOUT +ǒD
8192 *1Ǔ VREF
(2)
DAC8802
(SeeNote A)
Cross-Reference
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
The DAC8802, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of thefull-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing, as shown in Figure 35 .An additional external op amp (A2) is added as a summing amp. In this circuit, the first and second amps (A1and A2) provide a gain of 2X that widens the output span to 20 V. A 4-quadrant multiplying circuit isimplemented by using a 10-V offset of the reference voltage to bias A2. According to the following circuit transferequation (Equation 2 ), input data (D) from code 0 to full scale produces output voltages of V
OUT
= –10 V toV
OUT
= 10 V.
A. This figure represents one channel only. X is channel A or B (i.e. V
REF
x = V
REF
A or V
REF
B)
Figure 35. Four-Quadrant Multiplying Application Circuit
The DAC8802 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIEDINL DNL TEMPERATURE PACKAGE PACKAGE CROSS-REFERENCEPRODUCT (LSB) (LSB) RANGE DESCRIPTION OPTION PART NUMBER
16-Lead Thin ShrinkDAC8802IPW ±1±1 -40 °C to 85 °C TSSOP-16 AD5555CRUSmall-Outline Package
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PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC8802IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8802IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8802IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8802IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC8802IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC8802IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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