SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269O - DECEMBER 1995 - REVISED JULY 2003 D SN54AHCT541 . . . J OR W PACKAGE SN74AHCT541 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND description/ordering information The 'AHCT541 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54AHCT541 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 VCC The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state. A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE2 D D ORDERING INFORMATION PDIP - N SN74AHCT541N Tube SN74AHCT541DW Tape and reel SN74AHCT541DWR SOP - NS Tape and reel SN74AHCT541NSR AHCT541 SSOP - DB Tape and reel SN74AHCT541DBR HB541 Tube SN74AHCT541PW Tape and reel SN74AHCT541PWR TVSOP - DGV Tape and reel SN74AHCT541DGVR HB541 CDIP - J Tube SNJ54AHCT541J SNJ54AHCT541J CFP - W Tube SNJ54AHCT541W SNJ54AHCT541W LCCC - FK Tube SNJ54AHCT541FK SNJ54AHCT541FK TSSOP - PW -55C to 125C TOP-SIDE MARKING Tube SOIC - DW 40C to 85C -40C ORDERABLE PART NUMBER PACKAGE TA SN74AHCT541N AHCT541 HB541 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269O - DECEMBER 1995 - REVISED JULY 2003 FUNCTION TABLE (each buffer/driver) INPUTS A OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269O - DECEMBER 1995 - REVISED JULY 2003 recommended operating conditions (see Note 3) SN54AHCT541 SN74AHCT541 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC -8 V High-level output current VCC -8 mA IOL t/v Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall rate V V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = -50 mA IOH = -8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II IOZ VI = 5.5 V or GND VO = VCC or GND ICC VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND ICC Ci VI = VCC or GND VO = VCC or GND MIN 4.4 TA = 25C TYP MAX 4.5 3.94 SN54AHCT541 MIN MAX SN74AHCT541 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 V 0 V to 5.5 V 0.1 1* 1 mA 5.5 V 0.25 2.5 2.5 mA 5.5 V 4 40 40 mA 5.5 V 1.35 1.5 1.5 mA 10 pF 5V 2 10 Co 5V 4 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 pF 3 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269O - DECEMBER 1995 - REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25C TYP MAX SN54AHCT541 SN74AHCT541 MIN MAX MIN MAX 4.1* 6* 1* 6.5* 1 6.5 3.7* 5.5* 1* 6.5* 1 6.5 5* 7* 1* 8* 1 8 5* 7* 1* 8* 1 8 4.5* 7* 1* 8* 1 8 4.5* 7* 1* 8* 1 8 6.2 8.5 1 9.5 1 9.5 6 8.5 1 9.5 1 9.5 7.5 10 1 12 1 12 7.5 10 1 12 1 12 7 10 1 12 1 12 7 10 1 12 1 12 tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. 1** 1 UNIT ns ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 f = 1 MHz TYP 12 UNIT pF SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269O - DECEMBER 1995 - REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 k From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) 5962-9685801Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-9685801QRA ACTIVE CDIP J 20 1 TBD Call TI Call TI 1 TBD Call TI Call TI TBD Call TI Call TI 5962-9685801QSA ACTIVE CFP W 20 SN74AHCT541DBLE OBSOLETE SSOP DB 20 SN74AHCT541DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type SN74AHCT541NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) SN74AHCT541NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541NSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541PWLE OBSOLETE TSSOP PW 20 SN74AHCT541PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT541PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54AHCT541FK ACTIVE LCCC FK 20 1 TBD SNJ54AHCT541J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type SNJ54AHCT541W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type Call TI Samples (Requires Login) SN74AHCT541PWE4 TBD (3) Call TI POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54AHCT541, SN74AHCT541 : * Catalog: SN74AHCT541 * Enhanced Product: SN74AHCT541-EP, SN74AHCT541-EP * Military: SN54AHCT541 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHCT541DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74AHCT541DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74AHCT541NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74AHCT541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74AHCT541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74AHCT541PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT541DBR SN74AHCT541DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74AHCT541NSR SO NS 20 2000 367.0 367.0 45.0 SN74AHCT541PWR TSSOP PW 20 2000 364.0 364.0 27.0 SN74AHCT541PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74AHCT541PWRG4 TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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