56F8345 Technical Data, Rev. 16.0
6 Freescale Semiconductor
Preliminary
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . .7
1.1. 56F834 5/56F8145 Features . . . . . . . . . . . . . . .7
1.2. Device Description . . . . . . . . . . . . . . . . . . . . . .9
1.3. Award-Winni ng Development Environment . .11
1.4. Architecture Block Diagram . . . . . . . . . . . . . .12
1.5. Product Documentation . . . . . . . . . . . . . . . . .16
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . .16
Part 2: Signal/Connection Descriptions . . .17
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Part 3: On-Chip Clock Synthesis (OCCS) . .35
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.2. External Clock Operation . . . . . . . . . . . . . . . .35
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Part 4: Memory Map . . . . . . . . . . . . . . . . . . .37
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . . .3 8
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . . .40
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . . .43
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . . .45
4.7. Peripheral Memory Ma pped Registers . . . . . .46
4.8. Factory Programmed Memory . . . . . . . . . . . .72
Part 5: Interrupt Controller (ITCN) . . . . . . . .72
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.3. Functional Description . . . . . . . . . . . . . . . . . .72
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .7 4
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . .74
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . .75
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Part 6: System Integration Module (SIM) .102
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . .103
6.4. Operating Mode Register . . . . . . . . . . . . . . .103
6.5. Register Descriptions . . . . . . . . . . . . . . . . . .104
6.6. Clock Generatio n Overview . . . . . . . . . . . . .117
6.7. Power-Down Modes Ove r view . . . . . . . . . . .118
6.8. Stop and Wait Mode Disable Function . . . . .118
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Part 7: Security Features . . . . . . . . . . . . . .119
7.1. Operation with Security Enabled . . . . . . . . .119
7.2. Flash Access Blocking Mechanisms . . . . . .120
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 122
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . .122
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 122
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 123
Part 9: Joint Test Action Group (JTAG) . 128
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . . 128
Part 10: Specifications . . . . . . . . . . . . . . . 129
10.1. General Characteristics . . . . . . . . . . . . . . . 129
10.2. DC Electrical Characteristics . . . . . . . . . . .1 33
10.3. AC Electrical Characteristics . . . . . . . . . . . 137
10.4. Flash Memory Characteristics . . . . . . . . . .137
10.5. External Clock Operation Timing . . . . . . . . 138
10.6. Phase Locked Loop Timing . . . . . . . . . . . . 138
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . .139
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . .139
10.9. Serial Peripheral Interface (SPI) Timi ng . . . 141
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .144
10.11. Quadrature Decoder Timing . . . . . . . . . . . 145
10.12. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . .1 46
10.13. Controller Area Network (CAN) Timing . . 146
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 147
10.15. Analog-to-Digital Conver ter (ADC)
Parameters . . . . . . . . . . . . . . . . . .148
10.16. Equivalent Circuit for ADC Inputs . . . . . . .1 51
10.17. Power Consumption . . . . . . . . . . . . . . . . .151
Part 11: Packaging . . . . . . . . . . . . . . . . . . 153
11.1. 56F8345 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 153
11.2. 56F8145 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 156
Part 12: Design Considerations . . . . . . . . 160
12.1. Thermal Design Considerations . . . . . . . . . 160
12.2. Electrical Design Considerations . . . . . . . .1 61
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . . 162
Part 13: Ordering Information . . . . . . . . . 163
Table of Contents