© Freescale Semiconductor, Inc., 2004. All rights reserved.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
This hardware spec ification contai ns de tailed information on
power considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC875/MPC870. The CPU on the
MPC875/MPC870 is a 32-bit PowerPC™ core that incorporates
memory management units (MMUs) and instruction and data
caches and that implements the PowerPC instruction set. This
hardware specification covers the following topics:
1Overview
The MPC875/MPC870 is a versatile single-chip integrated
microprocessor and peripheral combination that can be used in a
variety of controller applications and communications and
networking systems. The MPC875/MPC870 provides enhanced
ATM functionality over that of other ATM-enabled members of
the MP C860 family.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 7
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7. Thermal Calculation and Measurement . . . . . . . . . . 11
8. Power Supply and Power Seque nc in g . . . . . . . . . . . 13
9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 14
10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12. IEEE 1149.1 E lectrical Specificat ions . . . . . . . . . . . 44
13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
14. USB Electrical Characteristics . . . . . . . . . . . . . . . . . 67
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 67
16. Mechanical Da t a and Ordering Informati on . . . . . . . 71
17. Document Revision History . . . . . . . . . . . . . . . . . . . 82
MPC875/MPC870
Hardware Specifications
MPC875EC
Rev. 3.0, 07/ 2004
MPC875/MPC870 Hardware Specifications, Rev. 3.0
2PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Features
Table 1 shows the functionality supported by the members of the MPC875/MPC870.
2Features
The MPC875/870 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM).
The following list summarizes the key MPC875/870 features:
• Embedded MPC8xx core up to 133 MHz
• Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode)
— The 133-MHz core frequency supports 2:1 mode only.
— The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes.
• Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional execution.
— 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1)
– Instruction cache is two-way, set-associative with 256 sets in 2 blocks
– Data cache is two-way, set-associative with 256 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches are physi cally addresse d, implement a least recently used (LRU) r eplacement algo rithm, and
are locka ble on a cach e blo ck ba sis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
and 16 protection groups
— Advanced on-chip emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
Table 1. MPC875/ 870 Devi ces
Part Cache Ethernet SCC SMC USB Security
Engine
I Cache D Cache 10BaseT 10/100
MPC875 8 Kbyt e 8 Kbyte 1 2 1 1 1 Yes
MPC870 8 Kbyt e 8 Kbyte — 2 — 1 1 No
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 3
Features
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
• Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that
interface through MII and/or RMII interfaces
• System integration unit (SIU)
— Bus monitor
— Software watchd og
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rinjdael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256-bit key lengths
— Message digest execution unit (MDEU)
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Ma ster/slave logic, with DMA
– 32-bit address/32- bit data
– Operation at 8xx bus frequency
— Crypto-channel supporting multi-command descriptors
– Integrated controller managing crypto-execution units
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
• Interrupts
— Six external interr upt re quest (IRQ) line s
MPC875/MPC870 Hardware Specifications, Rev. 3.0
4PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Features
— 12 port pins with interrupt capability
— 23 internal interrupt sources
— Programmable priority between SCCs
— Programmable highest priority request
• Communications processor module (CPM)
— RIS C controller
— Communicati on-specifi c commands (for ex ample, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— 8-Kbytes of dual-port RAM
— Several serial DMA (SDMA) channels to support the CPM
— Three parallel I/O registers with open-drain capability
•On-chip 16 × 16 multiply accumulate controller (MAC)
— One operation per clock (two-clock latency, one-clock blockage)
— MAC operates concurrently with other instructions
— FIR loop—Four clocks per four multiplies
• Four baud-rate generators
— Independent (can be connected to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
• SC C (serial commun ication controller)
— Ethernet/IEEE 802.3 optional on the SCC, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
—AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Tot ally tr ansp arent ( bit st reams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• SMC (serial management channel)
— UART (low-spee d opera ti on)
— Transparent
• Universal serial bus (USB)—Supports operation as a USB function endpoint, a USB host controller , or both
for testi ng purposes (loopbac k diagn ost ic s)
— USB 2.0 full-/low-speed compatible
— The USB function mode has the following features:
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 5
Features
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible dat a buffers with multiple bu ffers pe r frame
– Automatic retransmission upon transmit error
— The USB host controller has the following features:
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data
rate configuration). Note that low-speed operation requires an external hub.
– Flexible dat a buffers with multiple bu ffers pe r frame
– Supports local loopback mode for diagnostics (12 Mbps only)
• Serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
• Inter-integrated cir cuit (I2C) port
— Supports master and slave modes
— Supports a multiple-master environment
• The MPC875 has a time-slot assigner (TSA) that supports one TDM bus (TDMb).
— Allows SCC and SMC to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resoluti on
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— Can be internally connected to two serial channels (one SCC and one SMC)
• PCMCIA interface
— Ma ster (socket) interface , release 2.1-compliant
— Supports one independent PCMCIA socket on the MPC875/MPC870
— 8 memory or I/O windows supported
• De bug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally.
• Normal high and normal low power modes to conserve power
• 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility
• The MPC875/870 comes in a 256-pin ball grid array (PBGA) package.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
6PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Features
The MPC875 block diagram is shown in Figure 1.
Figure 1. MPC875 Block Diagram
Bus
System Interface Unit (SIU)
Embedded
Parallel I/O
Memory Controller
4
Timers Interrupt
Controllers 8-Kbyte
Dual-Port RAM
System Functions
8-Kbyte
Instruction Cache
32-Entry ITLB
Instruction MMU
8-Kbyte
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
4 Baud Rate
Generators
Parallel Interface Port
Internal
Bus Interface
Unit
External
Bus Interface
Unit
Timers
32-Bit RISC Controller
and Program
ROM
Serial Interface
SPISMC1
MPC8xx
Processor
Core
SCC4
Serial Interface
PCMCIA-ATA Interface
Virtual IDMA
and
Serial DMAs
Security Engine
AESU DEU MDEU
Controller
Channel
DMAs
DMAs
FIFOs
10/100
MIII/RMII
BaseT
Media Access
Control
Fast Ethernet
Controller
USB
Slave/Master IF
DMAs
I2C
Time Slot Assigner
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 7
Maximum Tole rated Ratings
The MPC870 block diagram is shown in Figure 2.
Figure 2. MPC870 Block Diagram
3 Maximum Tolerated Ratings
This se ction provides the maximum t olerate d voltage and temper ature r anges for the MPC87 5/870. Table 2
displays the maximum tolerated ratings, and Table 3 displays the operating temperatures.
Bus
System Interface Unit (SIU)
Embedded
Parallel I/O
Memory Controller
4
Timers Interrupt
Controllers 8-Kbyte
Dual-Port RAM
System Functions
8-Kbyte
Instruction Cache
32-Entry ITLB
Instruction MMU
8-Kbyte
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
4 Baud Rate
Generators
Parallel Interface Port
Internal
Bus Interface
Unit
External
Bus Interface
Unit
Timers
32-Bit RISC Controller
and Program
ROM
Serial Interface
SPISMC1
MPC8xx
Processor
Core
Serial Interface
PCMCIA-ATA Interface
Virtual IDMA and
Serial DMAs
DMAs
FIFOs
10/100
MIII / RMII
BaseT
Media Access
Control
Fast Ethernet
Controller
USB
Slave/Master IF
DMAs
I2C
MPC875/MPC870 Hardware Specifications, Rev. 3.0
8PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Maximum Tolerated Ratings
This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it
is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages
to thi s high-impedance circ uit. Reliab ility of operation i s enhanced if unused in put s a re t ied to an a ppropriate logic
voltage level (for example, either GND or VDDH).
Table 2. Maximum Tolerated Ratings
Rating Symbol Value Unit
Supply voltage 1
1 The power supply of the device must start its ramp from 0.0 V.
VDDL (core
voltage) –0.3 to 3.4 V
VDDH (I/O
voltage) –0.3 to 4 V
VDDSYN –0.3 to 3.4 V
Difference
between
VDDL and
VDDSYN
<100 mV
Input voltage 2
2 Func tio na l o pe rating conditions a r e prov id ed w ith t he D C e lec tric al s pe ci fic ati ons i n Table 6. Absolute maximum
ratings are stress rat ings only; fu nctional op eration at the maxima is not guaran teed. S tress bey ond those li sted may
affect device reliability or cause permanent damage to the device.
Caution: All inputs t hat tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power
up and norm al operatio n (that is, if the MPC875/870 is unpowered, a v oltage greater than 2.5 V must not be appli ed
to its inputs).
Vin GND – 0.3 to
VDDH
V
Storage temperature range Tstg –55 to +150 °C
Table 3. Operating Temperatures
Rating Symbol Value Unit
Temperature 1 (standard)
1 Minim um tempera ture s are guar anteed a s ambient te mperatu re, TA. Maximum tem peratu res are guaran tee d as
junction temperature, Tj.
TA(min) 0°C
Tj(max) 95 °C
Temperature (extended) TA(min) –40 °C
Tj(max) 100 °C
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 9
Thermal Characterist ics
4 Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC875/870.
5 Power Dissipation
Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are
equal, and 2:1, where CPU frequency is twice bus speed.
Table 4. MPC875/870 Thermal Resistance Data
Rating Environment Symbol Value Unit
Junction-to-ambient 1
1 Juncti on tempe ratur e is a function of on-chip power dis sipa tion , pac kage ther mal res istan ce, mountin g site (boa rd)
temperat ure, ambi ent tem peratu re, airfl ow, powe r diss ip ati on of o ther co mpone nt s on th e b oard, a nd boa rd therm al
resistance.
Natural convection Single-layer board (1s) RθJA 2
2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
43 °C/W
Four-layer board (2s2p) RθJMA 3
3 Per JEDEC JESD51-6 with the board horizontal.
29
Airflow (200 ft/min) Single-layer board (1s) RθJMA336
Four-layer board (2s2p) RθJMA326
Junction-to-board 4
4 Therm al resis t ance betw ee n t he di e a nd the pr inte d cir cui t b oard per JED EC J ESD51 -8. Board temp era ture is
measured on the top surface of the board near the package.
RθJB 20
Junction-to-case 5
5 Indic ate s the av erag e t herm al res is tance between the di e a nd the case top s urfac e as measured by th e c ol d pl ate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packag es whe re the p ad wo uld be ex pec ted to be s old ere d, jun ction-to-cas e the r ma l res istance is a simulated
value from the junction to the exposed pad without contact resistance.
RθJC 10
Junction-to-package top 6
6 Therm al characterization p aram et er indicati ng the te mperature diff eren ce b etwee n the pack ag e top and the junctio n
temperat ure per JED EC JESD51 -2.
Natural convection ΨJT 2
Airflow (200 ft/min) ΨJT 2
Table 5. Power Dissipation (PD)
Die Revision Bus
Mode Frequency Typical 1
1 Typical power dissipation is measured at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V.
Maximum 2 Unit
01:1 66 MHz 310 390 mW
80 MHz 350 430 mW
2:1 133 MHz 430 495 mW
MPC875/MPC870 Hardware Specifications, Rev. 3.0
10 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
DC Characteristics
6 DC Characteristics
Table 6 provides the DC electrical characteristics for the MPC875/870.
2 Maximum power dissipation at VDDL = VDDSYN = 1.9 V, and VDDH is at 3.5 V.
NOTE
The values in Table 5 represent VDDL-based p ower diss ipati on an d d o not
include I/O power dissipation over VDDH. I/O power dissipat ion varies
widely by application due to buffer current, depending on external
circuitry.
The VDDSYN power dissipation is negligible.
Table 6. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operati ng voltag e VDDH (I/O) 3.135 3.465 V
VDDL (Core) 1.7 1.9 V
VDDSYN 1
1 The difference between VDDL and VDDSYN cannot be more than 100 mV.
1.7 1.9 V
Difference
between
VDDL and
VDDSYN
— 100 mV
Input high voltage (all inputs except EXTAL and EXTCLK) 2
2 The signals P A[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST , TMS, MII1_TXEN, MII_MDIO
are 5-V tolerant. The minimum voltage is stil l 2.0 V.
VIH 2.0 3.465 V
Input low voltage 3
3 VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.
VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7 × VDDH VDDH V
Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and
DSDI pins) for 5-V toler ant pins 1Iin — 100 µA
Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and
DSDI) IIn —10µA
Input lea kage current, Vin = 0 V (excep t TMS, TRST, DSCK and DSDI
pins) IIn —10µA
Input capacitance 4 Cin —20pF
Output high voltage, IOH = –2.0 mA, VDDH = 3.0 V
except XTAL and open-drain pins VOH 2.4 — V
Output low vol t ag e
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA 5
IOL = 5.3 mA 6
IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)
VOL —0.5V
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 11
Thermal Calculation and Measurement
7 Thermal Calculation and Measurement
For the follow ing di scuss ions, PD = (VDDL × IDDL) + PI/O, where PI/O is the power dissipation of the I/O
drivers.
NOTE
The VDDSYN power dissipation is negligible.
7.1 Estimation with Junction-to-Ambient Thermal Resist ance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature ºC
RθJA = packa ge jun ction -to-ambi ent th ermal resis t ance (ºC/W)
PD = power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimat ion of t her mal performan ce. However, the an swer i s only an es timate; te st c ases have de mo nst ra ted
that errors of a factor of two (in the quantity TJ–TA) are possible.
7.2 Estim ation with Junction-to-Case Thermal Resistance
Historically, thermal resist ance has frequently been expresse d as the sum of a juncti on-to -case thermal
resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (ºC/W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to
affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the airflow around
the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the he at flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
4 Input capacitance is pe riodically sampled.
5 A(0: 31), TSI Z0/REG, TSIZ1, D(0:31), IRQ(2: 4), IRQ6, RD/WR, BURST, IP_B(0:1), P A(0: 4), P A(6:7), PA(10:1 1), PA15,
PB19, PB(23:31), PC(6:7), PC(10:13), PC15, PD8, PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL.
6 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3 ), BS_A(0:3 ), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
OP(0:3) BADDR(28:30
MPC875/MPC870 Hardware Specifications, Rev. 3.0
12 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Thermal Calcula tion and Me asurement
7.3 Estimation with Junction-to-Board Thermal Resistan ce
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model
consist ing of a junc tion- to-boa rd and a ju nctio n-to- case t herma l res ista nce. The j unc tion- to-ca se the rmal re sist ance
covers the si tu ation where a heat sink i s u sed or where a subst antia l am ount of heat is di ssipa ted from t he top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages
and especi ally PBGA packa ges is st rongl y depende nt on the bo ard tempe ratur e. If the boa rd temper atur e is known,
an estimate of the junction temperature in the environment can be made using the following equation:
TJ = TB + (RθJB ×PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature ºC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor
model can be use d with the therma l simula tion of t he app licatio n [2] , or a more accur ate and co mple x model of the
package can be used in the thermal simulation.
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
characterization parameter (ΨJT) can be used to dete rmine the j uncti on tempera ture w ith a measurement of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT ×PD)
where:
ΨJT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization paramete r is measured per th e JESD51-2 specif ication publis hed by JEDEC using a 40
gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
juncti on and over a bout 1 mm of wir e extendi ng from the junc tion. The t hermocou ple wire is pl aced fla t against the
package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 13
Power Supply and Power Sequencing
7.6 References
Semiconductor Equipment and Materials International (415) 964-5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. J oiner and V. Adams, “Mea surement and Si mulation of Junct ion to Board Th ermal Resist ance a nd Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
8 Power Supply and Power Sequencing
This section provides design considerations for the MPC875/870 power supply. The MPC875/870 has a
core voltage (VDDL) and PLL volta ge (VDDSYN), which both operate at a lower voltage than the I/O voltage
VDDH. The I/O section of the MPC875/870 is supplied with 3.3 V across VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,
TDO, TCK, TRST, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. No input can be more than 2.5 V
greater than VDDH. In addition, 5 V-tolerant pins cannot exceed 5.5 V, and remaining input pins cannot
exceed 3.465 V. This restriction applies to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
•V
DDL must not exceed VDDH during power up and power down.
•V
DDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic
dischar ge (ESD) protection diodes are forward-biased, and excessive current can flow through t hese diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 3
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
dif fer ence betwe en the ext ern al bus and core power supplie s on power up, and th e 1N5820 di odes reg ulate
the maximum potential difference on power down.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
14 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mandatory Reset Configurations
Figure 3. Example Voltage Sequencing Circuit
9 Mandatory Reset Configurations
The MPC875/870 requires a mandatory configuration during reset.
If hardwa re reset c onfigurat ion word (HRCW) is e nabled, the HRCW[DBGC] value needs t o be set to bin ary X1 in
the HRCW and the SIUMCR[DBGC] shoul d be pr ogram med with t he same va lue in the boo t code a fter reset . This
can be done by asserting the RSTCONF during HRESET assertion.
If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by
negating the RSTCONF during the HRESET assertion.
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR need to be configured with the
mandato ry values in Table 7 in the boot code after the reset is negated.
Table 7. Mandatory Reset Configuration of MPC875/870
Register/Configuration Field Value
(binary)
HRCW
(Hardware reset configuration word) HRCW[DBGC] X1
SIUMCR
(SIU modul e conf igu ration register ) SIUMCR[DBGC] X1
MBMR
(Machine B mode register) MBMR[GPLB4DIS} 0
PAPAR
(Port A pin assignment register) PAPAR[5:9]
PAPAR[12:13] 0
PADIR
(Port A data direction register) PADIR[5:9]
PADIR[12:13] 0
PBPAR
(Port B pin assignment register) PBPAR[14:18]
PBPAR[20:22] 0
PBDIR
(Port B data direction register) PBDIR[14:8]
PBDIR[20:22] 0
PCPAR
(Port C pin assignment register) PCPAR[4:5]
PCPAR[8:9]
PCPAR[14]
0
VDDH VDDL
1N5820
MUR420
MPC875/MPC870 Hardware Specifications, Rev. 3.0
15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Layout Practices
10 Layout Practices
Each VDD pin on the MPC875/870 shoul d be provide d with a low-impe dance path t o the board’s supply. Each GND
pin should likewise be pro vided with a low- impedance pat h to ground. The power su pply pins dri ve distinc t groups
of logic on chip. The VDD powe r s uppl y sh oul d be bypassed to g rou nd us ing at least fou r 0.1-µF bypass capa cit or s
located as close as possible to the four sides of the package. Each board designed should be characterized and
additi onal appropria te decoupling capacitors should be used if required. The c apacitor l eads and associated pr int ed
circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommend ed. Capacitance calcu lations should consider all device loads as well as parasi tic capacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN,
VSSSYN, VSSSYN1),” of the MPC885 PowerQUICC Family User’s Manual.
11 Bus Signal Timing
The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus). Table 8
shows the fr equenc y ranges f or stand ard part frequ encies in 1:1 bus mode , and Table 9 shows t he frequ ency rang es
for standard part frequencies in 2:1 bus mode.
PCDIR
(Por t C data direction register) PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]
0
PDPAR
(Port D pin assignment register) PDPAR[3:7]
PDPAR[9:5] 0
PDDIR
(Por t D data direction register) PDDIR[3:7]
PDDIR[9:15] 0
Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency 66 MHz 80 MHz
Min Max Min Max
Core frequency 40 66.67 40 80
Bus frequency 40 66.67 40 80
Table 7. Mandatory Reset Configuration of MPC875/870 (continued)
Register/Configuration Field Value
(binary)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
16 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 10 provides the bus operation timing for the MPC875/870 at 33, 40, 66, and 80 MHz.
The timing for the MPC875/870 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay
Table 9. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency 66 MHz 80 MHz 133 MHz
Min Max Min Max Min Max
Core frequency 40 66.67 40 80 40 133
Bus frequency 20 33.33 20 40 20 66
Table 10. Bus Operation Timings
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
B1 Bus peri od (CLKOUT), see Table 8 ————————ns
B1a EXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
EXTCLK, then the ris ing edge of EXTCLK
is aligned with the rising edge of CLKOUT.
For a non-integer multiple of EXTCLK, this
synchronization is lost, and the rising
edges of EXTCLK and CLKOUT have a
continuously varying phase skew.
–2 +2 –2 +2 –2 +2 –2 +2 ns
B1b CLKOU T freq uen cy jitter pea k-to -pe ak — 1 — 1 — 1 — 1 ns
B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %
B1d CLKOUT phase jitter peak-to-peak
for OSCLK ≥ 15 MHz —4—4—4—4ns
CLKOUT p hase jitter peak-to-peak
for OSCLK < 15 MHz —5—5—5—5ns
B2 CLKOUT pulse width low
(MIN = 0.4 ×B1, MAX = 0.6 ×B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns
B3 CLKOUT pulse width high
(MIN = 0.4 ×B1, MAX = 0.6 ×B1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31) output hold
(MIN = 0.25 ×B1)
7.60 — 6.30 — 3.80 — 3.13 — ns
B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,
PTR output hold (MIN = 0.25 ×B1) 7.60 — 6.30 — 3.80 — 3.13 — ns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS output
hold (MIN = 0.25 ×B1)
7.60 — 6.30 — 3.80 — 3.13 — ns
MPC875/MPC870 Hardware Specifications, Rev. 3.0
17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31) valid
(MAX = 0.25 ×B1 + 6.3)
—13.80—12.50—10.00— 9.43 ns
B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,
PTR valid (MAX = 0.25 ×B1 + 6.3) —13.80—12.50—10.00— 9.43 ns
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1), STS valid 2
(MAX = 0.25 ×B1 + 6.3)
—13.80—12.50—10.00— 9.43 ns
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), TSIZ(0:1), REG ,
RSV, PTR High-Z
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
B11 CLK OUT to TS, BB assertion
(MAX = 0.25 ×B1 + 6.0) 7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns
B11a CLKOUT to TA, BI assertion (when driven
by the memory controller or PCMCIA
interface) (MAX = 0.00 ×B1 + 9.30 1)
2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns
B12 CLKOUT to TS, BB negation
(MAX = 0.25 ×B1 + 4.8) 7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns
B12a CLKOUT to TA, BI negation (when driven
by the memory controller or PCMCIA
interface) (MAX = 0.00 ×B1 + 9.00)
2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns
B13 CLKOUT to TS, BB High-Z
(MIN = 0.25 ×B1) 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns
B13a CLKOUT to T A, BI High-Z (when driven by
the memory controller or PCMCIA
interface) (MIN = 0.00 ×B1 + 2.5)
2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns
B14 CLKOUT to TEA assertion
(MAX = 0.00 ×B1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
B15 CLKOUT to TEA High-Z
(MIN = 0.00 ×B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time)
(MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6 — ns
B16a TEA, KR, RETRY, CR valid to CLKOUT
(setup time) (MIN = 0.00 ×B1 + 4.5) 4.50 — 4.50 — 4.50 — 4.50 — ns
B16b BB, BG, BR, valid to CLKOUT (setup time)
2 (4MIN = 0.00 ×B1 + 0.00) 4.00 — 4.00 — 4.00 — 4.00 — ns
B17 CLKOUT to T A, TE A, BI, BB, BG, BR valid
(hold time) (MIN = 0.00 ×B1 + 1.00 3)1.00 — 1.00 — 2.00 — 2.00 — ns
B17a CLKOUT to KR, RETRY, CR valid (hold
time) (MIN = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
18 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B18 D(0:31) valid to CLKOUT rising edge
(setup time) 4 (MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns
B19 CLKOUT rising edge to D(0:31) valid (hold
time) 4 (MIN = 0.00 ×B1 + 1.00 5)1.00 — 1.00 — 2.00 — 2.00 — ns
B20 D(0:31) valid to CLKOUT falling edge
(setup time) 6(MIN = 0.00 ×B1 + 4.00) 4.00 — 4.00 — 4.00 — 4.00 — ns
B21 CLKOUT falling edge to D(0:31) valid
(hold time) 6 (MI N = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns
B22 CLKOUT rising edge to CS asse rted
GPCM ACS = 00 (MAX = 0.25 ×B1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
B22a CLKOUT falling edge to CS as serted
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 ×B1 + 8.00)
— 8.00 — 8.00 — 8.00 — 8.00 ns
B22b CLKOUT falling edge to CS as serted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns
B22c CLKOUT falling edge to CS assert ed
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 ×B1 + 6.6)
10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns
B23 CLKOUT rising edge to CS negated
GPCM read access, GPCM write access
ACS = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 ×B1 + 8.00)
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
B24 A(0:31) and BADDR(28:30) to CS
asse rted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[0:3] asserted
(MAX = 0.00 ×B1 + 9.00)
— 9.00 9.00 9.00 — 9.00 ns
B26 CLKOUT rising edge to OE negated
(MAX = 0.00 ×B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28:30) to CS
asse rted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 ×B1 – 2.00)
35.90 — 29.30 — 16.90 — 13.60 — ns
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, T RLX = 1
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 20.70 — 16.75 — ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B28 CLKOUT rising edge to
WE(0:3)/BS_B[0:3] negated GPCM write
access CSNT = 0
(MAX = 0.00 ×B1 + 9.00)
— 9.00 — 9.00 — 9.00 — 9.00 ns
B28a CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negated GPCM write
acce ss TR LX = 0, CSNT = 1, EBDF = 0
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns
B28b CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT = 1
ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25 ×B1 + 6.80)
—14.30—13.00—10.50— 9.93 ns
B28c CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negated GPCM write
access TRLX = 0, CSNT = 1 write access
TRLX = 0, C SNT = 1, EBDF = 1
(MAX = 0.375 ×B1 + 6.6)
10.90 18.00 10.90 18.00 5.20 12.30 4.69 11.29 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT = 1,
ACS = 10, or ACS = 11 , EBDF = 1
(MAX = 0.375 ×B1 + 6.6)
— 18.00 — 18.00 — 12.30 — 11.30 ns
B29 WE(0:3)/BS_B[0:3] negated to D(0:31)
High-Z GPCM write access, CSNT = 0,
EBDF = 0 (MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B29a WE(0:3)/BS_B[0:3] negated to D(0:31)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B29b CS negated to D(0:31) High-Z GPCM write
access, ACS = 00, TRLX = 0 & CSNT = 0
(MIN = 0.25 × B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B29c CS negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1, ACS = 10,
or ACS = 11 EBDF = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B29d WE(0:3)/BS_B[0:3] negated to D(0:31)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 20.70 — 16.75 — ns
B29e CS negated to D(0:31) High-Z GPCM write
access, TRLX = 1, CSNT = 1, ACS = 10,
or ACS = 11, EBDF = 0
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 20.70 — 16.75 — ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
20 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B29f WE(0:3/BS_B[0:3]) negated to D(0:31)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1
(MIN = 0.375 ×B1 – 6.30)
5.00 — 3.00 — 0.00 — 0.00 — ns
B29g CS negated to D(0:31) High-Z GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10 or
ACS = 11, EBDF = 1
(MIN = 0.375 ×B1 – 6.30)
5.00 — 3.00 — 0.00 — 0.00 — ns
B29h WE(0:3)/BS_B[0:3] negated to D(0:31)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1
(MIN = 0.375 ×B1 – 3.30)
38.40 — 31.10 — 17.50 — 13.85 — ns
B29i CS negated to D(0:31) (0:3) High-Z GPCM
write access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 ×B1 – 3.30)
38.40 — 31.10 — 17.50 — 13.85 — ns
B30 CS, WE(0:3)/BS_B[0:3] negated to
A(0:31), BADDR(28:30) invalid GPCM
write access 7 (MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B30a WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS negated
to A(0:31) invalid GPCM write access
TRLX = 0, CSNT =1 ACS = 10, or
ACS == 11, EBDF = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B30b WE(0:3)/BS_B[0:3] negated to A(0:31)
Invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1, CSNT = 1.
CS negated t o A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10, or
ACS == 11 EBDF = 0
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 20.70 — 16.75 — ns
B30c WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS negated
to A(0:31) invalid GPCM write access,
TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1
(MIN = 0.375 ×B1 – 3.00)
8.40 — 6.40 — 2.70 — 1.70 — ns
B30d WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM write access
TRLX = 1, CSNT =1, CS negated to
A(0: 31) invalid GPCM write access TRLX
= 1, CSNT = 1, ACS = 10 or 11, EBDF = 1
38.67 — 31.38 — 17.83 — 14.19 — ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B31 CLKOUT falling edge to CS valid, as
requested by control bit CST4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B31a CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
B31b CLKOUT rising edge to CS valid, as
requested by control bit CST2 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B31c CLKOUT rising edge to CS valid, as
requested by control bit CST3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.30)
7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM EBDF = 1
(MAX = 0.375 ×B1 + 6.6)
13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns
B32 CLKOUT falling edge to BS valid, as
requested by control bit BST4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B32a CLKOUT falling edge to BS valid, as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 0
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
B32b CLKOUT rising edge to BS valid, as
requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B32c CLKOUT rising edge to BS valid, as
requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
B32d CLKOUT falling edge to BS valid, as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF = 1
(MAX = 0.375 ×B1 + 6.60)
13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns
B33 CLKOUT falling edge to GPL valid, as
requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
22 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B33a CLKOUT rising edge to GPL valid, as
requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns
B34 A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by control bit CST4
in the corresponding word in the UPM
(MIN = 0.25 ×B1 - 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B34a A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by control bit CST1
in the corresponding word in the UPM
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B34b A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by CST2 in the
corresponding word in UPM
(MIN = 0.75 ×B1 – 2.00)
20.70 — 16.70 — 9.40 — 6.80 — ns
B35 A(0:31), BADDR(28:30) to CS valid, as
requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B35a A(0:31), BADDR(28:30), and D(0:31) to
BS valid, as requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 5.60 — 4.25 — ns
B35b A(0:31), BADDR(28:30), and D(0:31) to
BS valid, as requested by control bi t BST2
in the corresponding word in the UPM
(MIN = 0.75 ×B1 – 2.00)
20.70 — 16.70 — 9.40 — 7.40 — ns
B36 A(0:31), BADDR(28:30), and D(0:31) to
GPL valid, as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 1.80 — 1.13 — ns
B37 UPWAIT valid to CLKOUT falling edge 8
(MIN = 0.00 ×B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns
B38 CLKOUT falling edge to UPWAIT valid 8
(MIN = 0.00 ×B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns
B39 AS valid to CLKOUT rising edge 9
(MIN = 0.00 ×B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns
B40 A(0:31), T SIZ(0:1), RD/WR, BURST, valid
to CLKOUT rising edge
(MIN = 0.00 ×B1 + 7.00)
7.00 — 7.00 — 7.00 — 7.00 — ns
B41 TS valid to CLKOUT rising edge (setup
time) (MIN = 0.00 ×B1 + 7.00) 7.00 — 7.00 — 7.00 — 7.00 — ns
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
B42 CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00 ×B1 + 2.00) 2.00 — 2.00 — 2.00 — 2.00 — ns
B43 AS negation to memory controller signals
negation (MAX = TBD) —TBD—TBD—TBD—TBDns
1 For part speeds above 50 MHz, use 9.80 ns for B11a.
2 The ti mi ng requ ire d fo r BR in put is relev ant w hen the M P C875 /870 is s ele cte d to work wit h the inter nal bu s a rbiter.
The timing for BG input is relevant when the MPC875/870 is selected to work with the external bus arbiter.
3 For part speeds above 50 MHz, use 2 ns for B17.
4 The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the T A input si gnal is asserte d.
5 For part speeds above 50 MHz, use 2 ns for B19.
6 The D(0:31) input ti mi ngs B20 an d B21 refer to the falling edge of the CLKOUT. This tim ing is va li d on ly for r ead
accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controll er, for data beats where DL T3 = 1 in the RAM words. (This is only the case where data is latched on the falling
edge of CLKOUT.)
7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8 The signal UPW AIT is consid ered async hronous t o the CLKO UT and synchroniz ed intern ally. The timin gs specifi ed in
B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19.
9 The AS si gna l is c ons id ered async hro nou s to the CLKOUT. The ti ming B39 is spec ifi ed in order to a llo w th e beh av ior
specified in Figure 22.
Table 10. Bus Operation Timings (continued)
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
24 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 4 provides the control timing diagram.
.
Figure 4. Control Timing
Figure 5 provides the timing for the external clock.
Figure 5. External Clock Timing
C
LKOUT
Outputs
A
B
2.0 V 0.8 V 0.8 V 2.0 V
2.0 V
0.8 V 2.0 V
0.8 V
Outputs 2.0 V
0.8 V 2.0 V
0.8 V
B
A
Inputs 2.0 V
0.8 V 2.0 V
0.8 V
D
C
Inputs 2.0 V
0.8 V 2.0 V
0.8 V
C
D
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
C
LKOUT
B1
B5
B3
B4
B1
B2
MPC875/MPC870 Hardware Specifications, Rev. 3.0
25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 6 provides the timing for the synchronous output signals.
Figure 6. Synchronous Output Signals Timing
Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals.
Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
C
LKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7 B9
B8a
B9B7a
B8b
B7b
C
LKOUT
TS, BB
TA, BI
TEA
B13
B12B11
B11 B12a
B13a
B15
B14
MPC875/MPC870 Hardware Specifications, Rev. 3.0
26 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 8 provides the timing for the synchronous input signals.
Figure 8. Synchronous Input Signals Timing
Figure 9 prov ides nor mal cas e timin g for in put data. I t also applie s to nor mal read access es u nder th e contr ol of t he
user-program mable machine (UPM) in th e memo ry controller.
Figure 9. Input Dat a Timing in Normal Case
CLKOUT
TA, BI
TEA, KR,
R
ETRY, CR
B
B, BG, B R
B16
B17
B16a
B17a
B16b
B17
C
LKOUT
TA
D[0:31]
B16
B17
B19
B18
MPC875/MPC870 Hardware Specifications, Rev. 3.0
27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 10 provides the ti ming for the input da ta controlled b y the UPM for data beats where DLT3 = 1 in t he UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors.
Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00)
C
LKOUT
TA
D[0:31]
B20
B21
C
LKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28
MPC875/MPC870 Hardware Specifications, Rev. 3.0
28 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
C
LKOUT
A[0:31]
CSx
OE
TS
D[0:31]
B11 B12
B8
B22a B23
B26
B19B18
B25B24
C
LKOUT
A[0:31]
CSx
OE
TS
D[0:31]
B11 B12
B22b
B8
B22c B23
B24a B25 B26
B19B18
MPC875/MPC870 Hardware Specifications, Rev. 3.0
29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)
C
LKOUT
A[0:31]
CSx
OE
TS
D[0:31]
B11 B12
B8
B22a
B27
B27a
B22b B22c B19B18
B26
B23
MPC875/MPC870 Hardware Specifications, Rev. 3.0
30 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 15 through Figure 17 provide the ti ming for the external b us write controll ed by vario us GPC M factors.
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
CLKOUT
A[0:31]
CSx
WE[0:3]
OE
TS
D[0:31]
B11
B8
B22 B23
B12
B30
B28B25
B26
B8 B9
B29
B29b
MPC875/MPC870 Hardware Specifications, Rev. 3.0
31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
B23
B30a B30c
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31]
B11
B8
B22
B12
B28b B28d
B25
B26
B8
B28a
B9
B28c
B29c B29g
B29a B29f
MPC875/MPC870 Hardware Specifications, Rev. 3.0
32 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
B23B22
B8
B12B11
C
LKOUT
A[0:31]
CSx
WE[0:3]
TS
OE
D[0:31]
B30dB30b
B28b B28d
B25 B29e B29i
B26 B29d B29h
B28a B28c B9B8
B29b
MPC875/MPC870 Hardware Specifications, Rev. 3.0
33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 18 provides the timing for the external bus controlled by the UPM.
Figure 18. External Bus Timing (UPM Controlled Signals)
CLKOUT
CSx
B31d
B8
B31
B34
B32b
G
PL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
A[0:31]
B31c
B31b
B34a
B32
B32a B32d
B34b
B36
B35b
B35a
B35
B33
B32c
B33a
B31a
MPC875/MPC870 Hardware Specifications, Rev. 3.0
34 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
CLKOUT
CSx
UPWAIT
G
PL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
G
PL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
MPC875/MPC870 Hardware Specifications, Rev. 3.0
35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 21 provides the timing for the synchronous external master access controlled by the GPCM.
Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM.
Figure 22. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 23 provides the timing for the asynchronous external master control signals negation.
Figure 23. Asynchronous External Master—Control Signals Negation Timing
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
MPC875/MPC870 Hardware Specifications, Rev. 3.0
36 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 11 provides the interrupt timing for the MPC875/870.
Figure 24 provides the interrupt detection timing for the external level-sensitive lines.
Figure 24. Interrupt De tection Timing for External Level Sensitive Lines
Figure 25 pro vide s the i nterru pt de tection timing for the e xternal ed ge-se nsitiv e line s.
Figure 25. Inter rupt Detection Timing for External Edge-Sensitive Lines
Table 11. Interrupt Timing
Num Characteristic 1
1 The I3 9 a nd I40 tim ing s des cri be the tes t in g c on diti on s u nde r whi ch the IR Q lines are tested when being defined as
level s ensiti ve. The IRQ lines are synchro nized interna lly and do not have to be assert ed or nega ted wit h reference
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines det ectio n circuitry and have
no direct relation with the total system interrupt latency that the MPC875/870 is able to support.
All Frequencies Unit
Min Max
I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 ns
I40 IRQx hold time after CLKOUT 2.00 ns
I41 IRQx pulse width low 3.00 ns
I42 IRQx pulse width high 3.00 ns
I43 IRQx edge-to-edge time 4xTCLOCKOUT —
C
LKOUT
IRQx
I39
I40
C
LKOUT
IRQx
I41 I42
I43
I43
MPC875/MPC870 Hardware Specifications, Rev. 3.0
37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 12 shows the PCMCIA timing for the MPC875/870.
Table 12. PCMCIA Timing
Num Characteristic 33 MHz 40 MHz 6 6 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
P44 A(0:31), REG valid to PCMCIA
strobe asserted 1
(MIN = 0.75 ×B1 – 2.00)
1 PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These s ynchr onous timing s defi ne when t he WAITA signal s are d etecte d in orde r to freez e (or rel ieve) t he PCMCIA
current cycle. The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.
20.70 — 16.70 — 9.40 — 7.40 — ns
P45 A(0:31), REG valid to ALE
negation1
(MIN = 1.00 ×B1 – 2.00)
28.30 — 23.00 — 13.20 — 10.50 — ns
P46 CLKOUT to REG valid
(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P47 CLKOUT to REG invalid
(MIN = 0.25 ×B1 + 1.00) 8.60 — 7.30 — 4.80 — 4.125 — ns
P48 CLKOUT to CE1, CE2 asserted
(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P49 CLKOUT to CE1, CE2 negated
(MAX = 0.25 ×B1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns
P50 CLKOUT to PCOE, IORD, PCWE,
IOWR assert time (MAX =
0.00 ×B1 + 11.00)
— 11.00 — 11.00 — 11.00 — 11.00 ns
P51 CLKOUT to PCOE, IORD, PCWE,
IOWR negate tim e (MAX =
0.00 ×B1 + 11.00)
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
P52 CLKOUT to ALE assert time (MAX
= 0.25 ×B1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns
P53 CLKOUT to ALE negate time (MAX
= 0.25 ×B1 + 8.00) — 15.60 — 14.30 — 11.80 — 11.13 ns
P54 PCWE, IOWR negated to D(0:31)
invalid1 (MIN – = 0.25 ×B1 – 2.00) 5.60 — 4.30 — 1.80 — 1.125 — ns
P55 WAITA and W AITB valid to
CLKOUT ris ing edge1
(MIN = 0.00 ×B1 + 8.00)
8.00 — 8.00 — 8.00 — 8.00 — ns
P56 CLKOUT rising edge to WAIT A and
WAITB invalid1 (MIN = 0.00 ×B1 +
2.00)
2.00 — 2.00 — 2.00 — 2.00 — ns
MPC875/MPC870 Hardware Specifications, Rev. 3.0
38 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 26 provides the PCMCIA access cycle timing for the external bus read.
Figure 26. PCMCIA Access Cycles Timing External Bus Read
CLKOUT
A[0:31]
REG
CE1/CE2
PCOE, IORD
TS
D[0:31]
ALE
B19B18
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
MPC875/MPC870 Hardware Specifications, Rev. 3.0
39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 27 pro vide s the PCMCIA access cycle timing for th e external b us write.
Figure 27. PCMCIA Access Cycles Timing External Bus Write
Figure 28 provides the PCMCIA WAIT signals detection timing.
Figure 28. PCMCIA WAIT Signals Detection Timing
CLKOUT
A[0:31]
REG
CE1/CE2
PCWE, IOWR
TS
D[0:31]
ALE
B9B8
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
P54
C
LKOUT
WAITA
P55
P56
MPC875/MPC870 Hardware Specifications, Rev. 3.0
40 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 13 shows the PCMCIA port timing for the MPC875/870.
Figure 29 provides the PCMCIA output port timing for the MPC875/870.
Figure 29. PCMCIA Output Port Timing
Figure 30 provides the PCMCIA input port timing for the MPC875/870.
Figure 30. PCMCIA Input Port Timing
Table 13. PCMCIA Port Timing
Num Characteristic 33 MHz 40 MH z 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
P57 CLKOUT to OPx valid
(MAX = 0.00 ×B1 + 19.00) — 19.00 — 19.00 — 19.00 — 19.00 ns
P58 HRESET negated to OPx
drive 1(MIN = 0.75 ×B1 + 3.00)
1 OP2 and OP3 only.
25.70 — 21.70 — 14.40 — 12.40 — ns
P59 IP_Xx valid to CLKOUT rising edge
(MIN = 0.00 ×B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.00 — ns
P60 CLKOUT rising edge to IP_Xx invalid
(MIN = 0.00 ×B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns
CLKOUT
HRESET
Output
Signals
O
P2, OP3
P57
P58
C
LKOUT
Input
Signals
P59
P60
MPC875/MPC870 Hardware Specifications, Rev. 3.0
41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 14 shows the debug port timing for the MPC875/870.
Figure 31 provides the input timing for the debug port clock.
Figure 31. Debug Port Clock Input Timing
Figure 32 provides the timing for the debug port.
Figure 32. Debug Port Timings
Table 14. Debug Port Timin g
Num Characteristic All Frequencies Unit
Min Max
D61 DSCK cycle time 3 ×TCLOCKOUT —
D62 DSCK clock pulse width 1.25 ×TCLOCKOUT —
D63 DSCK rise and fall times 0.00 3.00 ns
D64 DSDI input data setup time 8.00 ns
D65 DSDI data hold time 5.00 ns
D66 DSCK low to DSDO data valid 0.00 15.00 ns
D67 DSCK low to DSDO invalid 0.00 2.00 ns
DSCK
D61
D61
D63
D62
D62
D63
DSCK
DSDI
DSDO
D64
D65
D66
D67
MPC875/MPC870 Hardware Specifications, Rev. 3.0
42 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Table 15 shows the reset timing for the MPC875/870.
Table 15. Re se t Timing
Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Unit
Min Max Min Max Min Max Min Max
R69 CLKOUT to HRESET high
impedance (MAX = 0.00 ×B1 +
20.00)
— 20.00 — 20.00 — 20.00 — 20.00 ns
R70 CLKOUT to SRESET high
impedance (MAX = 0.00 ×B1 +
20.00)
— 20.00 — 20.00 — 20.00 — 20.00 ns
R71 RSTCONF pulse width
(MIN = 17.00 ×B1) 515.20 — 425.00 — 257.60 — 212.50 — ns
R72 — —————————
R73 Configuration data to HRESET
rising edge setup time
(MIN = 15.00 ×B1 + 50.00)
504.50 — 425.00 — 277.30 — 237.50 — ns
R74 Configuration data to RSTCONF
rising edge setup time
(MIN = 0.00 ×B1 + 350.00)
350.00 — 350.00 — 350.00 — 350.00 — ns
R75 Configuration data hold time after
RSTCONF negation
(MIN = 0.00 ×B1 + 0.00)
0.00 — 0.00 — 0.00 — 0.00 — ns
R76 Configuration data hold time after
HRESET negation
(MIN = 0.00 ×B1 + 0.00)
0.00 — 0.00 — 0.00 — 0.00 — ns
R77 HRESET and RSTCONF
asse rted to data out drive
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
R78 RSTCONF negated to data out
high impedance
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
R79
CLKOUT of last rising edge
before chip three-states
HRESET to data out high
impedance
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
R80 DSDI, DSCK setup
(MIN = 3.00 ×B1) 90.90 — 75.00 — 45.50 — 37.50 — ns
R81 DSDI, DSCK hold time
(MIN = 0.00 ×B1 + 0.00) 0.00 — 0.00 — 0.00 — 0.00 — ns
R82 SRESET negated to CLKOUT
rising edge for DSDI and DSCK
sample (MIN = 8.00 ×B1)
242.40 — 200.00 — 121.20 — 100.00 — ns
MPC875/MPC870 Hardware Specifications, Rev. 3.0
43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Bus Signal Timing
Figure 33 shows the reset timing for the data bus configuration.
Figure 33. Reset Timing—Configuration from Data Bus
Figure 34 provides the reset timing for the data bus weak drive during configuration.
Figure 34. Reset Timing—Data Bus Weak Drive During Configuration
HRESET
RSTCONF
D
[0:31] (IN)
R71
R74
R73
R75
R76
CLKOUT
HRESET
D
[0:31] (OUT)
(Weak)
RSTCONF
R69
R79
R77 R78
MPC875/MPC870 Hardware Specifications, Rev. 3.0
44 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
IEEE 1149.1 Electrical Specifications
Figure 35 provides the reset timing for the debug port configuration.
Figure 35. Reset Timing—Debug Port Configuration
12 IEEE 1149.1 Electrical Specifications
Table 16 provides the JTAG timings for the MPC875/870 shown in Figure 36 to Figure 39.
Table 16. JTAG Timing
Num Characteristic
All
Frequencies Unit
Min Max
J82 TCK cycle time 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — ns
J86 TMS, TDI data hold time 25.00 — ns
J87 TCK low to TDO data valid — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 ns
J90 TRST assert time 100.00 — ns
J91 TRST setup time to TCK low 40.00 — ns
J92 TCK falling edge to output valid — 50.00 ns
J93 TCK falling edge to output valid out of high impedance — 50.00 ns
J94 TCK falling edge to output high impedance — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81 R81
MPC875/MPC870 Hardware Specifications, Rev. 3.0
45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
IEEE 1149.1 Electrical Specifications
Figure 36. JTAG Test Clock Input Timing
Figure 37. JTAG Test Access Port Timing Diagram
Figure 38. JTAG TRST Timing Diagram
TCK
J82 J83
J82 J83
J84 J84
TCK
T
MS, TDI
TDO
J85
J86
J87
J88 J89
TCK
TRST
J91
J90
MPC875/MPC870 Hardware Specifications, Rev. 3.0
46 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 39. Boundary Scan (JTAG) Timing Diagram
13 CPM Electrical Characteristics
This section pr ovides the AC and DC e le ctr ical speci f ica tions for the com mun ic at ion s processor m odu le (CPM) of
the MPC875/870.
13.1 Port C Interrupt AC Electrical Specifications
Table 17 provides the timings for port C interrupts.
Figure 40 shows the port C interrupt detection timing.
Figure 40. Port C Interrupt Detection Timing
Table 17. Port C Interrupt Timing
Num Characteristic 33.34 MHz Unit
Min Max
35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns
36 Port C interrupt minimum time between active edges 55 — ns
TCK
Output
Signals
Output
Signals
Output
Signals
J92 J94
J93
J95 J96
Port C
35
36
(Input)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
13.2 IDMA Controller AC Electrical Specifications
Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44.
Figure 41. IDMA External Requests Timing Diagram
Table 18. IDMA Controller Timing
Num Characteristic
All
Frequencies Unit
Min Max
40 DREQ setup time to clock high 7 — ns
41 DREQ hold time from clock high 1
1 Applies to high-to-low mode (EDM=1)
TBD — ns
42 SDACK assertion delay from clock high — 12 ns
43 SDACK negation delay from clock low — 12 ns
44 SDACK negation delay fro m TA low — 20 ns
45 SDACK negation delay from clock high — 15 ns
46 TA assertion to falling edge of the clock setup time (applies to external TA)7—ns
41
40
DREQ
(Input)
CLKO
(Output)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
48 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 42. SDACK Timing Diagram—Peripheral Write, Externally -Ge nerat e d TA
Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
DATA
42
46
43
CLKO
(
Output)
TS
(
Output)
R/W
(
Output)
TA
(Input)
SDACK
DATA
42 44
CLKO
(
Output)
TS
(
Output)
R/W
(
Output)
TA
(
Output)
SDACK
MPC875/MPC870 Hardware Specifications, Rev. 3.0
49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
13.3 Baud Rate Generator AC Electrical Specifications
Table 19 provides the baud rate generator timings as shown in Figure 45.
Figure 45. Baud Rate Generator Timing Diagram
Table 19. Baud Rate Generator Timing
Num Characteristic
All
Frequencies Unit
Min Max
50 BRGO rise and fall time — 10 ns
51 BRGO duty cycle 40 60 %
52 BRGO cycle 40 — ns
DATA
42 45
CLKO
(
Output)
TS
(
Output)
R/W
(
Output)
TA
(
Output)
SDACK
52
50
51
BRGOX
50
51
MPC875/MPC870 Hardware Specifications, Rev. 3.0
50 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
13.4 Timer AC Electrical Specifications
Table 20 provides the general-purpose timer timings as shown in Figure 46.
Figure 46. CPM Gener al-Purpose Timers Timing Diagram
13.5 Serial Interface AC Electrical Specifications
Table 21 provides the serial interface (SI) timings as shown in Figure 47 to Figure 51.
Tab le 20 . Ti mer Tim ing
Num Characteristic
All
Frequencies Unit
Min Max
61 TIN/TGATE rise and fall time 10 — ns
62 TIN/TGATE low time 1 — clk
63 TIN/TGATE high time 2 — clk
64 TIN/TGATE cycle time 3 — clk
65 CLKO low to TOUT valid 3 25 ns
Table 21. SI Timing
Num Characteristic All Frequencies Unit
Min Max
70 L1RCLKB, L1TCLKB frequency (DSC = 0) 1, 2 — SYNCCLK
/2.5 MHz
71 L1RCLKB, L1TCLKB width low (DSC = 0) 2P + 10 — ns
71a L1RCLKB, L1TCLKB width high (DSC = 0) 3 P + 10 — ns
72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time — 15.00 ns
73 L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) 20.00 — ns
CLKO
IN/TGATE
(Input)
TOUT
(Output)
64
65
61
626361
60
MPC875/MPC870 Hardware Specifications, Rev. 3.0
51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns
75 L1RSYNCB, L1TSYNCB rise/fall time — 1 5.00 ns
76 L1RXDB valid to L1CLKB edge (L1RXDB setup time) 17.00 — ns
77 L1CLKB edge to L1RXDB invalid (L1RXDB hold time) 13.00 — ns
78 L1CLKB edge to L1ST1 and L1ST2 valid 4 10.00 45.00 ns
78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns
79 L1CLKB edge to L1ST1 and L1ST2 invalid 10.00 45.00 ns
80 L1CLKB edge t o L1TXDB valid 10.00 55.00 ns
80A L1TSYNCB valid to L1TXDB valid 410.00 55.00 ns
81 L1CLKB edge to L1TXDB high impedance 0.00 42.00 ns
82 L1RCLKB, L1TCLKB frequency (DSC =1) — 16.00 or
SYNCCLK
/2
MHz
83 L1RCLKB, L1TCLKB width low (DSC =1) P + 10 — ns
83a L1RCLKB, L1TCLKB width high (DSC = 1)3P + 10 — ns
84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns
85 L1RQB valid before falling edge of L1TSYNCB41.00 — L1TCLK
86 L1GR B setup time242.00 — ns
87 L1GRB hold time 42.00 — ns
88 L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0) —0.00ns
1 The ratio SyncCLK/ L1RCLKB must be g reater than 2.5/1.
2 These specs are valid for IDL mode only.
3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These s trobes and Tx D on the first bit o f th e fra me be co me valid after the L1C LKB edg e or L1SYNCB, whic he ve r
comes later.
Table 21. SI Timing (continue d)
Num Characteristic All Frequencies Unit
Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
52 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 47. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
L1RXDB
(Input)
L1RCLKB
FE=0, CE=0)
(Input)
L1RCLKB
FE=1, CE=1)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
71
72
70 71a
RFSD=1
75
73
74 77
78
76
79
BIT0
MPC875/MPC870 Hardware Specifications, Rev. 3.0
53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 48. SI Receive Timing with Double-Speed Clocking (DSC = 1)
L1RXDB
(Input)
L1RCLKB
FE=1, CE=1)
(Input)
L1RCLKB
FE=0, CE=0)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
72
RFSD=1
75
73
74 77
78
76
79
83a
82
L1CLKOB
(Output)
84
BIT0
MPC875/MPC870 Hardware Specifications, Rev. 3.0
54 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 49. SI Transmit Timing Diagram (DSC = 0)
L1TXDB
(Output)
L1TCLKB
FE=0, CE=0)
(Input)
L1TCLKB
FE=1, CE=1)
(Input)
L1TSYNCB
(Input)
L1ST(2-1)
(Output)
71 70
72
73
75
74
80a
80
78
TFSD=0
81
79
BIT0
MPC875/MPC870 Hardware Specifications, Rev. 3.0
55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 50. SI Transmit Timing with Double Speed Clocking (DSC = 1)
L1TXDB
(Output)
L1RCLKB
FE=0, CE=0)
(Input)
L1RCLKB
FE=1, CE=1)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
72
TFSD=0
75
73
74
78a
80
79
83a
82
L1CLKOB
(Output)
84
BIT0
78
81
MPC875/MPC870 Hardware Specifications, Rev. 3.0
56 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 51. IDL Timing
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
L1RXDB
(Input)
L1TXDB
(Output)
L1ST(2-1)
(Output)
L1RQB
(Output)
73
77
12345678910 11 12 13 14 15 16 17 18 19 20
74
80
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
71
71
L1GRB
(Input)
78
85
72
76
87
86
L
1RSYNCB
(Input)
L1RCLKB
(Input)
81
MPC875/MPC870 Hardware Specifications, Rev. 3.0
57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
13.6 SCC in NMSI Mode Electrical Specifications
Table 22 provides the NMSI external clock timing.
Table 23 provides the NMSI internal clock timing.
Table 22. NMSI External Clock Timing
Num Characteristic All Frequencies Unit
Min Max
100 RCLK3 and TCLK3 width high 1
1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.
1/SYNCCLK — ns
101 RCLK3 and TCLK3 width low 1/SYNCCLK +5 — ns
102 RCLK3 and TCLK3 rise/fall time — 15.00 ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns
105 CTS3 setup time to TCLK3 rising edge 5.00 — ns
106 RXD3 setup time to RCLK3 rising edge 5.00 — ns
107 RXD3 hold time from RCLK3 rising edge 2
2 Also applies to CD and CTS hold time when they are used as external sync signals.
5.00 — ns
108 CD3 setup time to RCLK3 rising edge 5.00 — ns
Ta ble 23. NMSI Intern al Clock Timing
Num Characteristic All Frequencies Unit
Min Max
100 RCLK3 and TCLK3 frequency 1
1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLK3 and TCLK3 rise/fall time — — ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns
105 CTS3 setup time to TCLK3 rising edge 40.00 — ns
106 RXD3 setup time to RCLK3 rising edge 40.00 — ns
107 RXD3 hold time from RCLK3 rising edge 2
2 Also applies to CD and CTS hold time when they are used as external sync signals
0.00 — ns
108 CD3 setup time to RCLK3 rising edge 40.00 — ns
MPC875/MPC870 Hardware Specifications, Rev. 3.0
58 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 52 through Figure 54 sh ow th e NMSI timings.
Figure 52. SCC NMSI Receive Timing Diagram
Figure 53. SCC NMSI Transmit Timing Diagram
RCLK3
CD3
(Input)
102
100
107
108
107
RxD3
(Input)
CD3
(S
YNC Input)
102 101
106
TCLK3
CTS3
(Input)
102
100
104
107
TxD3
(Output)
CTS3
(SYNC Input)
102 101
RTS3
(Output)
105
103
104
MPC875/MPC870 Hardware Specifications, Rev. 3.0
59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 54. HDLC Bus Timing Diagram
13.7 Ethernet Electrical Specifications
Table 24 provides the Ethernet timings as shown in Figure 55 to Figure 57.
Table 24. Ethernet Timing
Num Characteristic
All
Frequencies Unit
Min Max
120 CLSN width high 40 — ns
121 RCLK3 rise/fall time — 15 ns
122 RCLK3 width low 40 — ns
123 RCLK3 clock period 1 80 120 ns
124 RXD3 setup tim e 20 — ns
125 RXD3 hold time 5 — ns
126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns
127 RENA width low 100 — ns
128 TCLK3 rise/fall time — 15 n s
129 TCLK3 width low 40 — ns
130 TCLK3 clock period199 101 ns
131 TXD3 active delay (from TCLK3 rising edge) — 50 ns
132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns
TCLK3
CTS3
(Echo Input)
102
100
104
TxD3
(Output)
102 101
RTS3
(Output)
103
104107
105
MPC875/MPC870 Hardware Specifications, Rev. 3.0
60 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 55. Ethernet Collision Timing Diagram
Figure 56. Ethernet Receive Timing Diagram
133 TENA active delay (from TCLK3 rising edge) 10 50 ns
134 TENA inactive delay (from TCLK3 ris ing edge) 10 50 ns
138 CLKO1 low to SDACK asserted 2 —20ns
139 CLKO1 low to SDACK negated 2—20ns
1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.
2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 24. Ethernet Timing (continued)
Num Characteristic
All
Frequencies Unit
Min Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124 123
127
126
Last Bit
MPC875/MPC870 Hardware Specifications, Rev. 3.0
61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 57. Ethernet Transmit Timing Diagram
13.8 SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 58.
Table 25. SMC Transparent Timing
Num Characteristic
All
Frequencies Unit
Min Max
150 SMCLK clock period 1
1 SyncCLK must be at least twice as fast as SMCLK.
100 — ns
151 SMCLK width low 50 — ns
151A SMCLK width high 50 — ns
152 SMCLK rise/fall time — 15 ns
153 SMTXD active delay (from SMCLK falling edge) 10 50 ns
154 SMRXD/SMSYNC setup time 20 — ns
155 RXD1/SMSYNC hold time 5 — ns
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
NOTES:
Transmit clock invert (TCI) bi t in GSMR is set.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133 134
132
131 121
129
(NOTE 2)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
62 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 58. SMC Transparent Timing Diagram
13.9 SPI Master AC Electrical Specifications
Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60.
Table 26. SPI Master Timing
Num Characteristic
All
Frequencies Unit
Min Max
160 MASTER cycle time 4 1024 tcyc
161 MASTER clock (SCK) high or low time 2 512 tcyc
162 MASTER data setup time (inputs) 15 — ns
163 Master data hold tim e (inpu t s ) 0 — ns
164 Master data valid (after SCK edge) — 10 ns
165 Master data hold tim e (outp ut s ) 0 — ns
166 Rise time output — 15 ns
167 Fall time output — 15 ns
SMCLK
SMRXD
(Input)
152
150
SMTXD
(Output)
152 151
SMSYNC
151
154 153
155
154
155
NOTE
NOTE:
This delay is equal to an integer number of character-length clocks.1.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 59. SPI Master (CP = 0) Timing Diagram
Figure 60. SPI Master (CP = 1) Timing Diagram
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
162
MPC875/MPC870 Hardware Specifications, Rev. 3.0
64 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
13.10SPI Slave AC Electrical Specifications
Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62.
Figure 61. SPI Slave (CP = 0) Timing Diagram
Table 27. SPI Slave Timing
Num Characteristic
All
Frequencies Unit
Min Max
170 Slave cycle time 2 — tcyc
171 Slave enable lead time 15 — ns
172 Slave enable lag time 15 — ns
173 Slave clock (SPICLK) high or low time 1 — tcyc
174 Slave sequential transfer delay (does not require deselect) 1 — tcyc
175 Slave data setup time (input s) 20 — ns
176 Slave data hold time (inputs) 20 — ns
177 Slave access time — 50 ns
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182173
173 170
msb lsb msb
181
177 182
175 179
SPISEL
(Input)
171172 174
Datamsb lsb msbUndef
181
178
176 182
MPC875/MPC870 Hardware Specifications, Rev. 3.0
65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Figure 62. SPI Slave (CP = 1) Timing Diagram
13.11I2C AC Electrical Specifications
Table 28 provides the I2C (SCL < 100 KHz) timings.
Table 28. I2C Timing (SCL < 100 KHZ)
Num Characteristic
All
Frequencies Unit
Min Max
200 SCL clock frequency (slave) 0 100 KHz
200 SCL clock frequency (master) 1 1.5 100 KHz
202 Bus free time between transmissions 4.7 — µs
203 Low period of SCL 4.7 — µs
204 High period of SCL 4.0 — µs
205 Start condition setup time 4.7 — µs
206 Start condition hold time 4.0 — µs
207 Data hold time 0 — µs
208 Data setup time 250 — ns
209 SDL/SCL rise time — 1 µs
S
PIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
S
PIMISO
(Output)
180
Data
181182
msb lsb
181
177 182
175 179
SPISEL
(Input)
174
Data
msb lsbUndef
178
176 182
msb
msb
172
173
173
171 170
181
MPC875/MPC870 Hardware Specifications, Rev. 3.0
66 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
CPM Electrical Characteristics
Table 29 provides the I2C (SCL > 100 KHz) timings.
210 SDL/SCL fall time — 300 ns
211 Stop condition setup time 4.7 — µs
1 SCL frequency is given by SCL = BR GCLK_f requency / ((BRG register + 3) ×pre_scalar ×2).
The ratio SyncClk/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.
Table 29. I2C Timing (SCL > 100 KHZ)
Num Characteristic Expression All Frequencies Unit
Min Max
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master) 1
1 SCL f requen cy is give n by SCL = BrgClk_freq uency / ((BRG reg ister + 3) ×pre_scalar ×2).
The ratio SyncClk/(Brg_Clk/pre_scalar) must be greater than or equal to 4/1.
fSCL BRGCLK/16512 BRGCLK/48 Hz
202 Bus free time between transmissions — 1/(2.2 ×fSCL) — s
203 Low period of SCL — 1/(2.2 ×fSCL) — s
204 High period of SCL — 1/(2.2 ×fSCL) — s
205 Start condition setup time — 1/(2.2 ×fSCL) — s
206 Start condition hold time — 1/(2.2 ×fSCL) — s
207 Data hold time — 0 — s
208 Data setup time — 1/(40 ×fSCL) — s
209 SDL/SCL rise time — — 1/(10 ×fSCL) s
210 SDL/SCL fall time — — 1/(33 ×fSCL) s
211 Stop condition setup time — 1/2(2.2 ×fSCL) — s
Table 28. I2C Timing (SCL < 100 KHZ) (continued)
Num Characteristic
All
Frequencies Unit
Min Max
MPC875/MPC870 Hardware Specifications, Rev. 3.0
67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
USB Electrical Characteristics
Figure 63 shows the I2C bus timing.
Figure 63. I2C Bus Timing Diagram
14 USB Electrical Characteristics
This section provides the AC timings for the USB interface.
14.1 USB Interface AC Timing Specifications
The USB Port uses the transmit clock on SCC1. Table 30 lists the U SB interfa ce timings.
15 FEC Electrical Characteristics
This section provides the AC electri cal specific ation s for t he fast Ethernet c ontroller (F EC). Note that th e timing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
15.1 MII and Reduced MII Receive Signal Timing
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. The reduced MII
(RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK
frequency – 1%.
Table 30. USB Interface AC Timing Specifications
Name Characteristic All Frequencies Unit
Min Max
US1 USBCLK frequency of operation 1
Low speed
Full speed
1 USBCLK accuracy should be ± 500 ppm or better. USBCLK may be stopped to conserve power.
6
48
MHz
MHz
US4 USBCLK duty cycle (measured at 1.5 V) 45 55 %
SCL
202
205
203
207
204
208
206 209 211210
SDA
MPC875/MPC870 Hardware Specifications, Rev. 3.0
68 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
FEC Electrical Characteris tics
Table 31 provides information on the MII receive signal timing.
Figure 64 sh ows MII receive signal timing.
Figure 64. MII Receive Signal Timing Diagram
15.2 MII and Reduced MII Transmit Signal Timing
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK
frequency – 1%.
Table 32 provides information on the MII transmit signal timing.
Table 31. MII Receive Signal Timing
Num Characteristic Min Max Unit
M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns
M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns
M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period
M4 MI I_RX_CLK pulse width low 35% 6 5% MII_R X_CLK period
M1_R
MII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK
setup 4— ns
M2_R
MII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR
hold 2— ns
Table 32. MII Transmit Signal Timing
Num Characteristic Min Max Unit
M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns
M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 ns
M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period
M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period
M1 M2
MII_RX_CLK (input)
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M3
M4
MPC875/MPC870 Hardware Specifications, Rev. 3.0
69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
FEC Electrical Characteris tics
Figure 65 shows the MII transmit signal timing diagram.
Figure 65. M II Transmit Signal Timing Diagram
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 33 provides information on the MII async inputs signal timing.
Figure 66 shows the MII asynchronous inputs signal timing diagram.
Figure 66. MII Async Inputs Timing Diagram
M20_R
MII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup 4 — ns
M21_R
MII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
edge 2— ns
Table 33. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period
Table 32. MII Transmit Signal Timing (continued)
Num Characteristic Min Max Unit
M6
MII_TX_CLK (input)
MII_TXD[3 :0] (outp ut s )
MII_TX_EN
MII_TX_ER
M5
M7
M8
MII_CRS, MII_COL
M9
MPC875/MPC870 Hardware Specifications, Rev. 3.0
70 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
FEC Electrical Characteris tics
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 34 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Figure 67 shows the MII serial management channel timing diagram.
Figure 67. MII Serial Management Channel Ti ming Diagram
Table 34. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay) 0— ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns
M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns
M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns
M14 MI I_MDC pulse width high 40% 6 0% MII_MDC period
M15 MII_MDC pulse width low 40% 60% MII_MDC period
M11
MII_MDC (output)
MII_MDIO (output)
M12 M13
MII_MDIO (input)
M10
M14
MM15
MPC875/MPC870 Hardware Specifications, Rev. 3.0
71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
16 Mechanical Data and Ordering Information
Table 35 identifies the packages and operating frequencies available for the MPC875/870.
16.1 Pin Assignments
Figure 68 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional
information, see the MPC885 PowerQUICC Family User’s Manual.
NOTE
The pin numbering starts with B2 in order to conform to the JEDEC standard for
23-mm body size using a 16 ×16 array.
Table 35. Available MPC875/870 Packages/Frequen cies
Package Type Temperature (Tj) Frequency (MHz) Order Number
Plastic ball grid array
ZT suffix — Leaded
VR suffix — Lead-Free are available as needed
0°C to 95°C 66 KMPC875ZT66
KMPC870ZT66
MPC875ZT66
MPC870ZT66
80 KMPC875ZT80
KMPC870ZT80
MPC875ZT80
MPC870ZT80
133 KMPC875ZT133
KMPC870ZT133
MPC875ZT133
MPC870ZT133
Plastic ball grid array
CZT suffix — Leaded
CVR suffix — Lead-Free are available as needed
-40°C to 100°C 66 KMPC875CZT66
KMPC870CZT66
MPC875CZT66
MPC870CZT66
133 KMPC875CZT133
KMPC870CZT133
MPC875CZT133
MPC870CZT133
MPC875/MPC870 Hardware Specifications, Rev. 3.0
72 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
NOTE: This is the top view of the device.
Figure 68. Pinout of the PBGA Package—JEDEC Standard
Table 36 contains a list of the MPC875/870 input and output signals and shows multiplexing and pin assignments.
Table 36. Pin Assignments—JEDEC Standard
Name Pin Number Type
A[0:31] R16, N14, M14, P15, P17, P16, N15, N16, M15, N17, L14, M16,
L15, M17, K14, L16 , L 17, K17, G17, K15 , J 16, J15, G16, J 14 , H 17 ,
H16, G15, K16, H1 4, J17, H 15, F17
Bidirectional
Three-state (3.3 V only)
TSIZ0
REG F16 Bidirectional
Three-state (3.3 V only)
MODCK2
IPA7
IPA4
D31
D29
D7
D18
D5
D3
D11
D10
N/C
EXTCLK MODCK1 OP0 ALEA IPB0 BURST IRQ6 BR TEA BI CS0 CS3 CS5 N/C
RSTCONFSRESET BADDR29 OP1
XTAL
IPA2 WAITA PORESET EXTAL BADDR30 IPB1 BG GPLA4 GPLA5 WR CE2A CS7 WE2
IPA5 IPA3 VDDSYN
AS ALEB IRQ2 BB
HRESETBADDR28 IRQ3
D30 IPA6
TS TA BDIP CS2 CE1A GPLAB3 GPLA0
CS1 GPLB4 CS4 GPLAB2 WE0 BSA1 BSA2
B
C
D
E
D28 CLKOUT
D22 D6 D24
D19 D20
D15 D16
D2 D27
D9 D12
D1
D23 D17 PE22
D4 D8 PE25
TSIZ0 A31
A22 A18
A25 A24
A20 A29
G
H
J
F
A27 A17
A15 A16
A11 A13
A7 A9
A5 A4
A0 PB29
K
L
VDDH
M
N
PE26 PD8 PA1 N/C PB30PE27
PE20 PE23 MII-TX-EN
PE17 PE21 PC7 PB19 PB24 TDI TMS PC12
PA14 N/C
PE15
PE29 PE24 PC13 MII-CRS PC10 PB23 PB25 TRST GND
P
R
T
PE16
234567 8910111213141516
IPA1
D26
D25
D14
D0
PE18
IRQ7
IRQ1
PA3
PB31
PA0 PE14 PE31 PC6 PA6 PC11 TDO PA15 A3PA4
PE28 PE30 PA11 MII_COL PA7 TCK PB28 PC15PE19
BSA0 BSA3
TSIZ1 A26
A28 A30
A23 A21
A14 A19
A10 A12
A2 A8
A1 A6
IRQ4
VSSSYN
WE1
PA10
D13
D21
VSSSYN1 CS6 OE
PA2 PB26 PB27
TEXP
17
U
IRQ0
IPA0
MII_MDIO
WE3
VDDH VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDL VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL GND
GND
GND
GND
MPC875/MPC870 Hardware Specifications, Rev. 3.0
73 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
TSIZ1 G14 Bidirectional
Three-state (3.3 V only)
RD/WR D13 Bidirectional
Three-state (3.3 V only)
BURST B9 Bidirectional
Three-state (3.3 V only)
BDIP
GPL_B5 C13 Output
TS C11 Bidirectional
Active p ull-up (3 .3 V o nly )
TA C12 Bidirectional
Active p ull-up (3 .3 V o nly )
TEA B12 Open-drain
BI B13 Bidirectional
Active p ull-up (3 .3 V o nly )
IRQ2
RSV C9 Bidirectional
Three-state (3.3 V only)
IRQ4
KR
RETRY
SPKROUT
E9 Bidirectional
Three-state (3.3 V only)
D[0:31] L5, N3, L3, L2, R2, K2, H3, G2, R3, M3, N2, M2, M4, N4, K5, K3, K4,
P3, J2, J3, J4, J5, H2, P2, H4, H5, G5, L4, G3, F2, F3, E2 Bidirectional
Three-state (3.3 V only)
CR
IRQ3 E10 Input
FRZ
IRQ6 B10 Bidirectional
Three-state (3.3 V only)
BR B11 Bidirectional (3.3 V only)
BG D10 Bidirectional (3.3 V only)
BB C10 Bidirectional
Active p ull-up (3 .3 V o nly )
IRQ0 M6 Input (3.3 V only)
IRQ1 P5 Input (3.3 V only)
IRQ7 N5 Input (3.3 V only)
CS[0:5] B14, E11, C14, B15, E13, B16 Out put
CS6
CE1_B F12 Output
CS7
CE2_B D15 Output
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
74 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
WE0
BS_B0
IORD
E15 Output
WE1
BS_B1
IOWR
D17 Output
WE2
BS_B2
PCOE
D16 Output
WE3
BS_B3
PCWE
G13 Output
BS_A[0:3] F14, E16, E17, F15 Output
GPL_A0
GPL_B0 C17 Output
OE
GPL_A1
GPL_B1
F13 Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
E14, C16 Output
UPWAITA
GPL_A4 D11 Bidirectional (3.3 V only)
UPWAITB
GPL_B4 E12 Bidirectional
GPL_A5 D12 Output
PORESET D5 Input (3.3 V only)
RSTCONF C3 Input (3.3 V only)
HRESET E7 Open-drain
SRESET C4 Open-drain
XTAL D6 Analog output
EXTAL D7 Analog input (3.3 V only)
CLKOUT G4 Output
EXTCLK B4 Input (3.3 V only)
TEXP B3 Output
ALE_A B7 Output
CE1_A C15 Output
CE2_A D14 Output
WAIT_A D4 Input (3.3 V only)
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
75 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
IP_A0 G6 Input (3.3 V only)
IP_A1 F5 Input (3.3 V only)
IP_A2
IOIS16_A D3 Input (3.3 V only)
IP_A3 E4 Input (3.3 V only)
IP_A4 D2 Input (3.3 V only)
IP_A5 E3 Input (3.3 V only)
IP_A6 F4 Input (3.3 V only)
IP_A7 C2 Input (3.3 V only)
ALE_B
DSCK C8 Bidirectional
Three-state (3.3 V only)
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
B8, D9 Bidirectional (3.3 V only)
OP0 B6 Bidirectional (3.3 V only)
OP1 C6 Output
OP2
MODCK1
STS
B5 Bidirectional (3.3 V only)
OP3
MODCK2
DSDO
B2 Bidirectional (3.3 V only)
BADDR[28:29] E8, C5 Output
BADDR30
REG D8 Output
AS C7 Input (3.3 V only)
PA15
USBRXD P14 Bidirectional
PA14
USBOE U16 Bidirectional
(Option al: ope n-dra in)
PA11
RXD4
MII1-TXD0
RMII1-TXD0
R9 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PA10
MII1-TXERR
TIN4
CLK7
R12 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
76 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
PA7
CLK1
BRGO1
TIN1
R11 Bidirectional
PA6
CLK2
TOUT1
P11 Bidirectional
PA4
CTS4
MII1-TXD1
RMII-TXD1
P7 Bidirectional
PA3
MII1-RXER
RMII1-RXER
BRGO3
R5 Bidirectional
(5-V tolerant)
PA2
MII1-RXDV
RMII1-CRS_DV
TXD4
N6 Bidirectional
(5-V tolerant)
PA1
MII1-RXD0
RMII1-RXD0
BRGO4
T4 Bidirectional
(5-V tolerant)
PA0
MII1-RXD1
RMII1-RXD1
TOUT4
P6 Bidirectional
(5-V tolerant)
PB31
SPISEL
MII1 - TXCLK
RMII1-REFCLK
T5 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB30
SPICLK T17 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB29
SPIMOSI R17 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB28
SPIMISO
BRGO4
R14 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB27
I2CSDA
BRGO1
N13 Bidirectional
(Option al: ope n-dra in)
PB26
I2CSCL
BRGO2
N12 Bidirectional
(Option al: ope n-dra in)
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 77
Mechanical Data and Ordering Information
PB25
SMTXD1 U13 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB24
SMRXD1 T12 Bidirectional
(Option al: ope n-dra in)
(5-V tolerant)
PB23
SDACK1
SMSYN1
U12 Bidirectional
(Option al: ope n-dra in)
PB19
MII1-RXD3
RTS4
T11 Bidirectional
(Option al: ope n-dra in)
PC15
DREQ0
L1ST1
R15 Bidirectional
(5-V tolerant)
PC13
MII1-TXD3
SDACK1
U9 Bidirectional
(5-V tolerant)
PC12
MII1-TXD2
TOUT1
T15 Bidirectional
(5-V tolerant)
PC11
USBRXP P12 Bidirectional
PC10
USBRXN
TGATE1
U11 Bidirectional
PC7
CTS4
L1TSYNCB
USBTXP
T10 Bidirectional
(5-V tolerant)
PC6
CD4
L1RSYNCB
USBTXN
P10 Bidirectional
(5-V tolerant)
PD8
RXD4
MII-MDC
RMII-MDC
T3 Bidirectional
(5-V tolerant)
PE31
CLK8
L1TCLKB
MII1-RXCLK
P9 Bidirectional
(Option al: ope n-dra in)
PE30
L1RXDB
MII1-RXD2
R8 Bidirectional
(Option al: ope n-dra in)
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
78 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
PE29
MII2-CRS U7 Bidirectional
(Option al: ope n-dra in)
PE28
TOUT3
MII2-COL
R7 Bidirectional
(Option al: ope n-dra in)
PE27
L1RQB
MII2-RXERR
RMII2-RXERR
T6 Bidirectional
(Option al: ope n-dra in)
PE26
L1CLKOB
MII2-RXDV
RMII2-CRS_DV
T2 Bidirectional
(Option al: ope n-dra in)
PE25
RXD4
MII2-RXD3
L1ST2
R4 Bidirectional
(Option al: ope n-dra in)
PE24
SMRXD1
BRGO1
MII2-RXD2
U8 Bidirectional
(Option al: ope n-dra in)
PE23
TXD4
MII2-RXCLK
L1ST1
U4 Bidirectional
(Option al: ope n-dra in)
PE22
TOUT2
MII2-RXD1
RMII2-RXD1
SDACK1
P4 Bidirectional
(Option al: ope n-dra in)
PE21
TOUT1
MII2-RXD0
RMII2-RXD0
T9 Bidirectional
(Option al: ope n-dra in)
PE20
MII2-TXER U3 Bidirectional
(Option al: ope n-dra in)
PE19
L1TXDB
MII2-TXEN
RMII2-TXEN
R6 Bidirectional
(Option al: ope n-dra in)
PE18
SMTXD1
MII2-TXD3
M5 Bidirectional
(Option al: ope n-dra in)
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
79 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
PE17
TIN3
CLK5
BRGO3
SMSYN1
MII2-TXD2
T8 Bidirectional
(Option al: ope n-dra in)
PE16
L1RCLKB
CLK6
MII2-TXCLK
RMII2-REFCLK
U6 Bidirectional
(Option al: ope n-dra in)
PE15
TGATE1
MII2-TXD1
RMII2-TXD1
T7 Bidirectional
PE14
MII2-TXD0
RMII2-TXD0
P8 Bidirectional
TMS T14 Input
(5-V tolerant)
TDI
DSDI T13 Input
(5-V tolerant)
TCK
DSCK R13 Input
(5-V tolerant)
TRST U14 Input
(5-V tolerant)
TDO
DSDO P13 Output
(5-V tolerant)
MII1_CRS U10 Input
MII_MDIO M13 Bidirectional
(5-V tolerant)
MII1_TX_EN
RMII1_TX_EN U5 Output
(5-V tolerant)
MII1_COL R10 Input
VSSSYN E5 PLL analog GND
VSSSYN1 F6 PLL analog GND
VDDSYN E6 PLL analog VDD
GND H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10,
L11, U15 Power
VDDL F7, F8, F9, F10, F11, H6, H13, J6, J13, K6, K13, L6, L13, N7, N8,
N9, N10, N11 Power
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
80 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Mechani cal Data and Orde ring Informa tion
VDDH G7, G8, G9, G10, G1 1, G12, H7, H12, J7, J12, K7, K12, L7, L12, M7,
M8, M9, M10, M11, M12 Power
N/C B17, T16, U2, U17 No-connect
Table 36. Pin Assignments—JEDEC Standard (continued)
Name Pin Number Type
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 81
Mechanical Data and Ordering Information
16.2 Mechanical Dimensions of the PBGA Package
Figure 69 shows the mechanical dimensions of the PBGA package.
Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/870VRXXX.
Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/870ZTXXX .
1. ALL DIMENSIONS ARE IN MILLIMETE RS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M— 1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEF INE D BY T HE SPHERIC AL CR O W NS O F TH E SO LDER BALLS.
NOTES:
MPC875/MPC870 Hardware Specifications, Rev. 3.0
82 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freesca le Sem ico nd uctor
Document Revision History
17 Document Revision History
Table 37 lists significant changes between revisions of this hardware specification.
Table 37. Document Revision History
Revision
Number Date Changes
0 2/2003 Initial releas e.
0.1 3/2003 Took out the time-slot assigner and changed the SCC for SCC3 to SCC4.
0.2 5/2003 Changed the pa ckage drawin g, removed all refere nces to Data Parity. Changed the SPI
Master T imi ng Specs. 162 and 164. Added the RMII and U SB timing. Adde d the 80-MHz
timing.
0.3 5/2003 Made sure the pin types were correct. Changed the Features list to agree with the
MPC885.
0.4 5/2003 Corrected the signals that had overlines on them. Made corrections on two pins that were
typos.
0.5 5/2003 Changed the pin descriptions for PD8 and PD9.
0.6 5/2003 Changed a few typos. Put ba ck the I2C. Put in the new reset co nfiguration, c orrected the
USB timing.
0.7 6/2003 Changed the pin descriptions per the June 22 spec, removed Utopia from the pin
descriptions, changed PADIR, PBDIR, PCDIR and PDDIR to be 0 in the Mandatory
Reset Config.
0.8 8/2003 Added the reference to USB 2.0 to the Features list and removed 1.1 from USB on the
block dia gram s .
0.9 8/2003 Changed the USB description to full-/low-speed compatible.
1.0 9/2003 Added the DSP info rmati on in t he Fe atures list.
Put a new sentence under Mechanical Dimensions.
Fixed table formatting.
Nontechnical edits.
Released to the external web.
1.1 10/2003 Added TDMb to the MPC875 Features list, the MPC875 Block Diagram, added 13.5
Serial Interface AC Electrical Specifications, and removed TDMa from the pin
descriptions.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Freescale Semicond uc tor PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE 83
Document Revision History
2.0 12/2003 Changed DBGC in the Mandatory Reset Configuration to X1.
Changed the maximum operating frequency to 133 MHz.
Put the timing in the 80 MHz column.
Put in the orde rabl e part numbers.
Rounded the timings to hundredths in the 80 MHz column.
Put the pin numbers in footnotes by the maximum currents in Table 6.
Changed 22 and 41 in the Timing.
Put TBD in the Thermal table.
3.0 1/07/2004
7/19/2004 • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for
Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Added the thermal numbers to Table 4.
• Added RMII1_EN under M1II_EN in Table 36 Pin Assignments
• Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL
Max of the I2C Standard
• Put the new part numbers in the Ordering Information Section
Table 37. Document Revision History (continued)
Revision
Number Date Changes
MPC875EC
Rev. 3.0
07/2004
How to Reach Us:
USA/Europe/Locations Not Listed:
Freescale Semiconductor
Literature Distribution Center
P.O. Box 5405,
Denver, Colorado 80217
1-480-768-2130
(800) 521-6274
Japan:
Freescale Semiconductor Japan Ltd.
Technical Information Center
3-20-1, Minami-Azabu, Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
852-26668334
Home Page:
www.freescale.com
Information in this document is provided solely to enable system and software implementers to use
Freescale Semiconductor products. There are no express or implied copyright licenses granted
hereunder to design or fabricate any integrated circuits or integrated circuits based on the information
in this document.
Freescale Semiconductor reserves the right to make changes without further notice to any products
herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability , including without limita tion consequential or incidental damages. “T ypical” parameters
which may be provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating parameters,
including “T ypicals” must be validated for each customer application by customer’s technical experts.
Freescale Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer purchase or use
Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleg es that Frees cale Semico nductor was
negligent regarding the design or manufacture of the part.
Learn Mo re: For more information about Freescale Semiconductor products, please visit
www.freescale.com
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor , Inc. The described
product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and
used under license. All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2004.