NT5TU32M16DG-AC - Nanya Technology Corporation

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

1

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Feature

CAS Latency Frequency

Speed Bins

-3C/3CI*

(DDR2-667-CL5)

-AC/ACI*

(DDR2-800-CL5)

-BE*

(DDR2-1066-CL7)

-BD*

(DDR2-1066-CL6)

Units

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tCK(Avg.)

Clock Frequency

125

333

125

400

125

533

125

533

MHz

tRCD

15

-

12.5

-

12.5

-

11.25

-

ns

tRP

15

-

12.5

-

12.5

-

11.25

-

ns

tRC

60

-

57.5

-

57.5

-

56.25

-

ns

tRAS

40

70K

40

70K

40

70K

40

70K

ns

tCK(Avg.)@CL3

5

8

5

8

5

8

5

8

ns

tCK(Avg.)@CL4

3.75

8

3.75

8

3.75

8

3.75

8

ns

tCK(Avg.)@CL5

3

8

2.5

8

2.5

8

2.5

8

ns

tCK(Avg.)@CL6

-

2.5

8

2.5

8

1.875

8

ns

tCK(Avg.)@CL7

-

1.875

8

1.875

8

ns

*The timing specification of high speed bin is backward compatible with low speed bin

 1.8V ± 0.1V Power Supply Voltage

 4 internal memory banks

 Programmable CAS Latency:

3, 4, 5 (-3C/-3CI/-AC/-ACI/-BD/-BE)

6 (-AC/-ACI/-BD/-BE)

7 (-BD/-BE)

 Programmable Additive Latency: 0, 1, 2, 3, 4 5

 Write Latency = Read Latency -1

 Programmable Burst Length:

 4 and 8 Programmable Sequential / Interleave Burst

 OCD (Off-Chip Driver Impedance Adjustment)

 ODT (On-Die Termination)

 4 bit prefetch architecture

 Data-Strobes: Bidirectional, Differential

 Support Industrial grade temperature -40℃~95℃

Operating Temperature (-3CI/-ACI)

 1KB page size for x8

2KB page size for x16

 Strong and Weak Strength Data-Output Driver

 Auto-Refresh and Self-Refresh

 Power Saving Power-Down modes

 7.8 µs max. Average Periodic Refresh Interval

 RoHS Compliance and Halogen Free

 Packages:

60-Ball BGA for x8 components

84-Ball BGA for x16 components

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

2

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Description

The 512Mbit Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing

536,870,912 bits. It is internally configured as a quad-bank DRAM.

The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. These synchronous devices

achieve high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write

latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance

adjustment and (5) an ODT (On-Die Termination) function.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended

DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x8 organized components and

A 13 bit address bus for x16 component is used to convey row, column, and bank address devices.

These devices operate with a single 1.8V ± 0.1V power supply and are available in BGA packages.

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

3

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration – 60 balls BGA Package (x8)

< TOP View>

See the balls through the package

A

B

C

D

E

F

G

X 8

1

VDD

DQ4

NU,/RDQS

VSSQ

DQ1

VSSQ

VREF

CKE

A10/ AP

2

VSS

DM/RDQS

VDDQ

DQ3

VSS

WE

BA1

3 7 8 9

A3

VDDQ

VDD

DQS

VSSQ

DQ0

VSSQ

CK

CS

VSSQ

DQS

VDDQ

VSSDL

RAS

CAS

VDD

H

J

K

L

DQ6

VDDQ

VDDL

A7

A12VDD

BA0

A1

A5

A9

NC NC

A11

A6

A2

DQ2

A13

A8

A4

A0

DQ7

VDDQ

DQ5

VSS

NC

VSS

ODT

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

4

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Pin Configuration – 84 balls BGA Package (x16)

< TOP View>

See the balls through the package

A

B

C

D

E

F

G

H

J

K

L

x 16

1

VDD

DQ14

VDDQ

DQ12

VDD

DQ4

NC

VSSQ

DQ9

VSSQ

NC

VSSQ

DQ1

VSSQ

VREF

CKE

A10/ AP

2

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE

BA 1

3 7 8 9

A3

VDDQ

DQ15

VDDQ

DQ13

VDDQ

VDD

UDQS

VSSQ

DQ8

VSSQ

LDQS

VSSQ

DQ0

VSSQ

C

K

CK

CS

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

VSSDL

RAS

CAS

VDD

M

N

P

R

DQ6

VDDQ

VDDL

A7

A12VDD

BA0

A1

A5

A9

NC NC

A11

A6

A2

DQ2

NC

A8

A4

A0

DQ7

VDDQ

DQ5

VSS

NC

VSS

ODT

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

5

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Input / Output Functional Description

Symbol

Type

Function

CK, 

Input

Clock: CK and  are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of . Output (read) data is

referenced to the crossings of CK and  (both directions of crossing).

CKE

Input

Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE low provides Precharge Power-Down and

Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is

synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for

Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it

must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and

exit, VREF must maintain to this input. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input

buffers, excluding CKE, are disabled during Self-Refresh.



Input

Chip Select: All commands are masked when  is registered high.  provides for external rank

selection on systems with multiple memory ranks.  is considered part of the command code.

, , 

Input

Command Inputs: ,  and  (along with ) define the command being entered.

DM, LDM, UDM

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For

x8 device, the function of DM or RDQS /  is enabled by EMRS command.

BA0 – BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. Bank address also determines if the mode register or extended mode

register is to be accessed during a MRS or EMRS cycle.

A0 – A13

Input

Address Inputs: Provides the row address for Activate commands and the column address and

Auto Precharge or Read/Write commands to select one location out of the memory array in the

respective bank. A10 is sampled during a Precharge command to determine whether the

precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be

precharged, the bank is selected by BA0-BA1. The address inputs also provide the op-code during

Mode Register Set commands.A13 Row address use on x8 components only.

DQ

Input/output

Data Inputs/Output: Bi-directional data bus.

DQS, ()

LDQS, (),

UDQS,()

Input/output

Data Strobe: output with read data, input with write data. Edge aligned with read data, centered

with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to

the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single

ended mode or paired with the optional complementary signals , ,  to provide

differential pair signaling to the system during both reads and writes. An EMRS(1) control bit

enables or disables the complementary data strobe signals.

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

6

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Symbol

Type

Function

RDQS, ()

Input/output

Read Data Strobe: For x8 components a RDQS and  pair can be enabled via EMRS(1) for

real timing. RDQS and  is not support x16 components. RDQS and  are edge-aligned

with real data. If enable RDQS and  then DM function will be disabled.

ODT

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2

SDRAM. When enabled, ODT is applied to each DQ, DQS, , RDQS, , and DM signal for

x8 configuration. For x16 configuration ODT is applied to each DQ, UDQS, , LDQS, ,

UDM and LDM signal. The ODT pin will be ignored if the EMRS (1) is programmed to disable ODT.

NC

No Connect: No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply: 1.8V ± 0.1V

VSSQ

Supply

DQ Ground

VDDL

Supply

DLL Power Supply: 1.8V ± 0.1V

VSSDL

Supply

DLL Ground

VDD

Supply

Power Supply: 1.8V ± 0.1V

VSS

Supply

Ground

VREF

Supply

SSTL_1.8 reference voltage

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

7

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Ordering Information

Green

Standard Grade

Organization

Part Number

Package

Speed

Clock (MHz)

CL-TRCD-TRP

NT5TU64M8DE-3C

60-Ball BGA

333

5-5-5

NT5TU64M8DE-AC

400

5-5-5

NT5TU32M16DG-3C

84-Ball BGA

333

5-5-5

NT5TU32M16DG-AC

400

5-5-5

NT5TU32M16DG-BD

533

6-6-6

NT5TU32M16DG-BE

533

7-7-7

Industrial Grade

Organization

Part Number

Package

Speed

Clock (MHz)

CL-TRCD-TRP

NT5TU64M8DE-3CI

60-Ball BGA

333

5-5-5

NT5TU64M8DE-ACI

400

5-5-5

NT5TU32M16DG-3CI

84-Ball BGA

333

5-5-5

NT5TU32M16DG-ACI

400

5-5-5

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

8

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (64Mb x 8)

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

I/O Gating

DM Mask Logic

Bank 7

Row-Address

Latch &

Decoder

Bank 6

Row-Address

Latch &

Decoder

Bank 5

Row-Address

Latch &

Decoder

Bank 4

Row-Address

Latch &

Decoder

Bank 3

Row-Address

Latch &

Decoder

Bank 2

Row-Address

Latch &

Decoder

Bank 1

Row-Address

Latch &

Decoder

Command

Decode

Mode

Registers

Control Logic

CKE

CK

CS

WE

CAS

RAS

Address Register

17

Row-Address MUX

14

A0 – A13,

BA0 – BA2

10

17

14

Refresh Counter

Column-Address

Counter/Latch

2

Bank Control

Logic

8

Bank 0

Row-Address

Latch &

Decoder

Bank 7

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 6

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 5

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 4

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 3

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 2

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 1

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 0

Memory Array

(16384 x256 x32)

Sense Amplifier

16384

8192

256 (x32)

8

2

32

Read Latch

Write

FIFO

&

Drivers

8

MUX

COL0,1

Drivers

DQS

Generator

8

2

Data

DQS,

DQS

2

8

2

8

4

Mask

32

Data

COL0,1

CK,

CK

2

8

Receivers

ODT Control

DM

DQS,

DQS

ODT

DLL

CK, CK

14

3

COL0,1

Input

Register

Notes:

1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does

not represent an actual circuit implementation.

2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ

and DQS signals.

2

DQ0 – DQ7

RDQS , 

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

9

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Block Diagram (32Mb x 16)

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

Column

Decoder

I/O Gating

DM Mask Logic

Bank 7

Row-Address

Latch &

Decoder

Bank 6

Row-Address

Latch &

Decoder

Bank 5

Row-Address

Latch &

Decoder

Bank 4

Row-Address

Latch &

Decoder

Bank 3

Row-Address

Latch &

Decoder

Bank 2

Row-Address

Latch &

Decoder

Bank 1

Row-Address

Latch &

Decoder

Command

Decode

Mode

Registers

Control Logic

CKE

CK

CS

WE

CAS

RAS

Address Register

16

Row-Address MUX

13

A0 – A12,

BA0 – BA2

10

16

13

Refresh Counter

Column-Address

Counter/Latch

3

Bank Control

Logic

8

Bank 0

Row-Address

Latch &

Decoder

Bank 7

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 6

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 5

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 4

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 3

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 2

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 1

Memory Array

(16384 x512 x16)

Sense Amplifier

Bank 0

Memory Array

(8192 x 256 x 64)

Sense Amplifier

8192

16384

256 (x64)

8

2

64

Read Latch

Write

FIFO

&

Drivers

16

MUX

COL0,1

Drivers

DQS

Generator

16

4

Data

UDQS, 

LDQS, 

2

16

2

16

8

Mask

64

Data

COL0,1

CK,

CK

2

16

Receivers

ODT Control

UDM,

LDM

UDQS,

UDQS

DQ0 –

DQ15

ODT

DLL

CK, CK

13

3

COL0,1

Input

Register

Notes:

1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does

not represent an actual circuit implementation.

2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ

and DQS signals.

LDQS,

LDQS

4

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

10

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Functional Description

The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The

512Mb DDR2 SDRAM is internally configured as a quad-bank DRAM.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for

the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command,

which is followed by a Read or Write command. The address bits registered coincident with the activate command are

used to select the bank and row to be accesses (BA0 and BA1 select the banks, A0-A13 select the row for x8

components, A0-A12 select the row for x16 components). The address bits registered coincident with the Read or Write

command are used to select the starting column location for the burst access and to determine if the Auto-Precharge

command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information

covering device initialization, register definition, command description and device operation.

Power-up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

The following sequence is required for POWER UP and Initialization.

1. Either one of the following sequence is required for Power-up.

While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be unde-

fined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and

during the VDD voltage ramp up, IVDD-VDDQI≦0.3 volts. Once the ramping of the supply voltages is complete (when

VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating conditions table.

- VDD, VDDL, and VDDQ are driven from a signal power converter output, AND

- VTT is limited to 0.95V max, AND

- Vref tracks VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ>=VREF must be met at all times.

While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be

undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up.

During the ramping of the supply voltages, VDD≧VDDL≧VDDQ must be maintained and is applicable to both AC and

DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the

ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC operating

conditions table.

- Apply VDD/VDDL before or at the same time as VDDQ.

- VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin.

- Apply VDDQ before or at the same time as VTT.

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

11

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must

be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to

VDDQ.)

- Vref must track VDDQ/2; Vref must be within ±300mV with respect to VDDQ/2 during supply ramp time.

- VDDQ ≧ VREF must be met at all time.

- Apply VTT.

2. Start clock (CK, ) and maintain stable condition.

3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and

maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or

Deselect & take CKE HIGH.

4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period.

5. Issue an EMRS command to EMR (2). (Provide LOW to BA0, and HIGH to BA1).

6. Issue an EMRS command to EMR (3). (HIGH to BA0 and BA1).

7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1 and A13. And A9=A8=A7=LOW must

be used when issuing this command.)

8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0 and A13)

9. Issue a precharge all command.

10. Issue 2 more auto-refresh commands.

11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without

resetting the DLL.)

12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration

is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit

OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).

13. The DDR2 DRAM is now ready for normal operation.

* To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

Example:

CK, CK

1st Auto

refresh

MRS

PRE

ALL EMRS

CMD

2nd Auto

refresh

tRP tRP tRFC tRFC

Extended Mode

Register Set

with DLL enable

Mode Register Set

with DLL reset

PRE

ALL

tMRD tMRD

min. 200 cycles to

lock the DLL

CKE

Command

400 ns

MRS

NOP

tMRD

EMRS

Follow OCD

flowchart

ODT "low"

Follow OCD

flowchart

EMRS

NT5TU64M8DE / NT5TU32M16DG

512Mb DDR2 SDRAM

12

REV 1.8

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Register Definition

Programming the Mode Registration and Extended Mode Registers

For application flexibility, burst length, burst type,  latency, DLL reset function, write recovery time (tWR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable

function, additive  latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip

driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register

Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR (#)) can be altered by

re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables,

all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect

array contents, which mean re-initialization including those can be executed any time after power-up without affecting

array contents.

Mode Registration Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls  latency,

burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM

useful for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on , , , , BA0 and

BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged (idle)

mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is

required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharged state.

The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options

of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and  latency is defined by A4 ~ A6. A7 is

used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for

write recovery time (WR) definition for Auto-Precharge mode.

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MRS Mode Register Operation Table (Address Input for Mode Set)

A0A1A2A3A4A5A6A7A8A9A10A11A12A13BA0BA1BA2

Address Field

BLA0A1A2

4010

8110

Burst Length

Burst TypeA3

Sequential0

Interleave

1

Burst Type

CAS LatencyA4A5A6

Reserved000

Reserved100

/CAS Latency

010

110

001

101

011

111

6

Reserved

7

MRS mode

BA0BA1

MR

00

EMR(1)

10

MRS mode

01

11 EMR(3)

EMR(2)

Active power down

exit time

A12

Fast exit (use tXARD)0

Slow exit (use tXARDS)

1

Active power down exit time

* *

WR (cycles)A9A10A11

Reserved000

2100

Write recovery for autoprecharge

010

110

001

101

011

111

4

5

6

7

3

DLL ResetA8

NO0

YES

1

DLL Reset

ModeA7

Normal0

TEST

1

Mode

* BA2 and A13 are reserved for future use and must be set to

"0" when programming MR.

3

4

5

DDR2-1066

DDR2-667

DDR2-800

8

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Extended Mode Register Set -EMRS (1) Programming

A0A1A2A3A4A5A6A7A8A9A10A11A12A13BA0BA1BA2

Address Field

DLL

Enable

A0

Enable

0

Disable1

DLL

Output Driver

Impedance Control

A1

Full strength

0

Reduced strength

1

D.I.C

Rtt (Nominal)A2A6

ODT Disabled00

75 ohm10

Rtt

01

11 50 ohm *2

150 ohm

MRS mode

BA0BA1

MR

00

EMR(1)

10

MRS mode

01

11 EMR(3)

EMR(2)

Qoff

* *

DQSA10

Enable0

Disable

1

DQS

*BA2 and A13 are reserved for future use and must be set to0 when programming the EMR(1).

*2 Mandatory for DDR2-1066

*3 When Adjust mode is issued, AL from previously set value must be applied.

*4 After setting to default, OCD calibration mode needs to be exited by settin gA9-A7 to 000.

*5 Output disabled – DQs, DQSs, DQSs, RDQS, RDQS. This feature is used in conjunction with DIMM IDD

measurements when IDDQ is not desired to be included.

*6 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and do not care for writes.

Additive

Latency

A3A4A5

0000

1100

010

110

001

101

011

111

3

4

6

2

Reserved

Additive Latency

5

Qoff *5A12

Output buffer enabled0

Output buffer disabled

1

RDQS Enable*6A11

Enable

0Disable

1

RDQS

OCD Calibration ProgramA7A8

OCD Calibration mode

exit; maintain setting

00

Drive(1)10

01

00 Adjust mode *3

Drive(0)

A9

0

1

11 OCD Calibration default*41

OCD Program

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Extended Mode Register Set –EMRS (1)

The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive

latency, ODT,  disable, OCD program, RQDS enable. The default value of the extended mode register EMRS(1) is

not defined, therefore the extended mode register must be written after power-up for proper operation. The extended

mode register is written by asserting low on , , , , BA1 and high on BA0, while controlling the state of the

address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended

mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the

EMRS (1). Mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD control, A10 is used for 

disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.

Single-ended and Differential Data Strobe Signals

The following table lists all possible combinations for DQS, , RDQS,  which can be programmed by A10 & A11

address bits in EMRS(1). RDQS and  are available in x8 components only. If RDQS is enabled in x8 components,

the DM function is disabled. RDQS is active for reads and don’t care for writes.

EMRS (1)

Strobe Function Matrix

A11

(RDQS Enable)

A10

( Enable)

RDQS/DM



DQS



Signaling

0 (Disable)

0 (Enable)

DM

Hi-Z

DQS



differential DQS signals

0 (Disable)

1 (Disable)

DM

Hi-Z

DQS

Hi-Z

single-ended DQS signals

1 (Enable)

0 (Enable)

RDQS



DQS



differential DQS signals

1 (Enable)

1 (Disable)

RDQS

Hi-Z

DQS

Hi-Z

single-ended DQS signals

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning

to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh

operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset,

200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be

synchronized with the external clock. Less clock cycles may result in a violation of the tAC or tDQSCK

parameters.

Output Disable (Qoff)

Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS (1) is

set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to

measure IDD currents during Read operations, without including the output buffer current and external load currents.

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EMRS (2) Extended Mode Register Set Programming

Address Field

Extended Mode

Register

1PASR***

BA1BA0 A11 A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0*

A2 A1 A0 Partial Array Self Refresh

0 0 0 Full array

0 0 1 Half Array (BA[2:0]= 000 ,

001,

010, & 011 )

0 1 0 Quarter Array (BA[2:0 ]=000&001 )

0 1 1 1/8th

array (BA[2:0] = 000)

1 0 0 3

/

4 array (BA[2:0]=010,011,100,101,110,

&111)

1 0 1 Half array (BA[2:0]= 100 ,

101,

110, & 111)

1 1 0 Quarter array (BA[2:0]=110& 11

1)

1 1 1 1/8th

array (BA[2:0]=111)

0SRF

A7

0Disable

1Enable**

High Temperature Self-Refresh Rate Enable

A12

0*

BA2

0*

BA 0MRS mode

0MR S

1EMRS(1)

BA1

0

1

11

0EMRS (2)

EMRS (3):

Reserved

*The rest bits in EMRS (2) is reserved for future use and all bits in EMRS (2) expect A0-A2,

A7, BA0, and BA1 must be programmed to 0 when setting EMRS(2) during initialization.

**DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0].

***Optional, if PASR (Partial Array Self Refresh) is enabled, data located in areas of the array

beyond the spec. location will be lost if self refresh is entered.

Extended Mode Register Set EMRS (2)

The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is

not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1,

while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already

high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be

satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using

the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.

EMRS(3) Extended Mode Register Set Programming

All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode

register during initialization.

(Reserved)

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Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued.

MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully

controlled depending on system environment.

Start

EMRS: Drive(1)

DQ & DQS High; DQSLow

Test

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: Drive(0)

DQ & DQS Low; DQSHigh

Test

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

ALL OK ALL OK

Need Calibration

EMRS: OCD calibration mode exit

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

EMRS: OCD calibration mode exit

Need Calibration

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Extended Mode Register Set for OCD impedance adjustment

OCD impedance adjustment can be done using the following EMRS (1) mode. In drive mode all outputs are driven out by

DDR2 SDRAM and drive of RDQS is dependent on EMRS (1) bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS

(and RDQS) signals are driven high and all  (and ) signals are driven low. In Drive (0) mode, all DQ, DQS (and

RDQS) signals are driven low and all  (and ) signals are driven high. In adjust mode, BL = 4 of operation code

data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18

Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are

specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS (1) and if half

strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD

default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as ’000’ in order to

maintain the default or calibrated value.

Off- Chip-Driver program

A9

A8

A7

Operation

0

OCD calibration mode exit

0

1

Drive(1) DQ, DQS, (RDQS) high and  low

0

1

0

Drive(0) DQ, DQS, (RDQS) low and  high

1

0

Adjust mode

1

OCD calibration default

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OCD impedance adjust

To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to

DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before

activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at

bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs

simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength

setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or

decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust

mode command is issued, AL from previously set value must be applied.

4 bit burst code inputs to all DQs

Operation

DT0

DT1

DT2

DT3

Pull-up driver strength

Pull-down driver strength

0

NOP (no operation)

0

1

Increase by 1 step

NOP

0

1

0

Decrease by 1 step

NOP

0

1

0

NOP

Increase by 1 step

1

0

NOP

Decrease by 1 step

0

1

0

1

Increase by 1 step

0

1

0

Decrease by 1 step

Increase by 1 step

1

0

1

Increase by 1 step

Decrease by 1 step

1

0

1

0

Decrease by 1 step

Other Combinations

Reserved

For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing

diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or

interleave).

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OCD Adjust Mode

OCD adjust mode OCD calibration

mode exit

EMRS

CK

CMD NOP NOP NOP NOP NOP

WL

DQS

DQ

tDS tDH

DT0DT1DT2DT3

DM

EMRS NOP

WR

DQS

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Drive Mode

Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD

impedance adjustment. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers

are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.

NOP NOP NOP

NOP

EMRS(1)

CMD

DQ_in

NOP

DQS_in

CK, CK

EMRS(1) NOP

Enter Drive Mode OCD calibration

mode exit

NOP

DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0

DQS high for Drive(0)

DQS high for Drive(1)

tOIT tOIT

On-Die Termination (ODT)

ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS,

, RDQS, , and DM signal for x8 configurations via the ODT control pin. For x16 configuration ODT is applied to

each DQ, UDQS, , LDQS, , UDM and LDM signal via the ODT control pin. The ODT feature is designed to

improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination

resistance for any or all DRAM devices.

The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode.

Functional Representation of ODT

DRAM

Input

Buffer Input

Rval1

Rval2

sw1

sw2

VDDQ VDDQ

VSSQ VSSQ

Rval3

sw3

VDDQ

VSSQ

Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by “Rtt (nominal)” in EMRS.

Termination included on all DQs, DM, DQS, , RDQS, and  pins.

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ODT related timings

MRS command to ODT update delay

During normal operation the value of the effective termination resistance can be changed with an EMRS command. The

update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of

tMOD window for proper operation. The timings are shown in the following timing diagram.

CKE

Rtt

CK,CK

tIS

CMD

tAOFD

EMRS NOP NOP NOP NOP NOP

tMOD, min

tMOD, max

Old setting Updating New setting

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

However, to prevent any impedance glitch on the channel, the following conditions must be met.

- tAOFD must be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met.

Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT.

Following timing diagram shows the proper Rtt update procedure.

CKE

Rtt

CK,CK

tIS

CMD

tAOFD

EMRS NOP NOP NOP NOP

tMOD, max

Old setting New setting

EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal)

Setting in this diagram is the Register and I/O setting, not what is measured from outside.

tAOND

NOP

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ODT On/Off timings

ODT timing for active/standby mode

Rtt

tIS

tAOND tAOFD(2.5tck)

T-3 T-5

T-4T-0 T-2

T-1 T-6

CKE

Internal

Term Res.

ODT

CK, CK

tAON, min tAON, max tAOF, min tAOF, max

ODT Timing for Power-down mode

t

IS

t

IS

tAOFPD,max

Rtt

tAONPD,min

tAOFPD,min

tAONPD,max

T5 T6

T4T3T2

T0 T1

CKE

DQ

ODT

CK, CK

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Bank Activate Command

The Bank Activate command is issued by holding  and  high plus  and  low at the rising edge of the clock.

The bank addresses BA0 ~ BA1 are used to select the desired bank. The row addresses A0 through A13 are used to

determine which row to activate in the selected bank for and x8 organized components. For x16 components row

addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write

operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write

command (with or without Auto-Precharge) on the following clock cycle. If an R/W command is issued to a bank that has

not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command

which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive

latencies of 0, 1, 2, 3, 4, 5, and 6 are supported. Once a bank has been activated it must be precharged before another

Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP,

respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined

(tRC). The minimum time interval between Bank Active commands, to other bank, is the Bank A to Bank B delay time (tRRD).

In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices,

certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the

number of sequential ACTcommands that can be issued and another for allowing more time for RAS precharge for a

Precharge All command. The rules are list as follow:

* 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window.

Conveting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling

window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further

activate commands may be issued in clock N+1 through N+9.

*8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK,

where tRP is the value for a single bank pre-charge.

Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2

Address NOP

Command

T0 T2T1 T3 T4

Col. Addr.

Bank A Row Addr.

Bank B Col. Addr.

Bank B

Internal RAS-CAS delay tRCDmin.

Bank A to Bank B delay tRRD.

Activate

Bank B

Read A

Posted CAS

Activate

Bank A Read B

Posted CAS

Read A

Begins

Row Addr.

Bank A Addr.

Bank A

Precharge

Bank A NOP

Addr.

Bank B

Precharge

Bank B

Row Addr.

Bank A

Activate

Bank A

tRP Row Precharge Time (Bank A)

tRC Row Cycle Time (Bank A)

Tn Tn+1 Tn+2 Tn+3

ACT

RAS-RAS delay tRRD.

tRAS Row Active Time (Bank A)

additive latency AL=2

CK, CK

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Read and Write Commands and Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting  high,  and

 low at the clock’s rising edge.  must also be defined at this time to determine whether the access cycle is a read

operation ( high) or a write operation ( low). The DDR2 SDRAM provides a fast column access operation. A single

Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst

cycle is restricted to specific segments of the page length.

A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of

BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes

interrupted by a write with 4 bit burst boundary respectively, and the minimum  to  delay (tCCD) is minimum 2

clocks for read or write cycles.

Posted 

Posted  operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the 

bank activate command (or any time during the  to  delay time, tRCD, period). The command is held for the time of

the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the 

latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0

must be written into the EMRS (1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read

Latency is defined as the sum of Additive Latency plus  latency (RL=AL+CL). If a user chooses to issue a Read

command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL.

Example of posted  operation:

Read followed by a write to the same bank:

AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4

Dout0Dout1Dout2

Dout3

CMD

DQ

023 4 5 6 7 8 9 10 11 12-1 1

>=tRCD

AL = 2

RL = AL + CL = 5

CL = 3WL = RL -1 = 4

Din0 Din1 Din2 Din3

PostCAS1

DQS,

DQS

Activate Read Write

Bank A Bank A Bank A

CK, CK

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Read followed by a write to the same bank:

AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4

Activate

Bank A

023 4 5 6 7 8 9 10 11 12-1 1

CMD

DQ

>=tRCD

RL = AL + CL = 3

WL = RL – 1 = 2

PostCAS5

DQS,

DQS

Read

Bank A

Din0 Din1 Din2 Din3

Dout0 Dout1 Dout2 Dout3

Write

Bank A

CK, CK

AL=0

CL=3

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Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from

memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence

and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full

interleave address ordering is supported, however, sequential address ordering is nibble based for ease of

implementation. The burst type, either sequential or interleaved, is programmable and defined by the address

bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or

write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write

burst when burst length = 8 is used, see the “Burst Interruption “section of this datasheet. A Burst Stop

command is not supported on DDR2 SDRAM devices.

Bust Length and Sequence

Burst Length

Starting Address

(A2 A1 A0)

Sequential Addressing

(decimal)

Interleave Addressing

(decimal)

4

x 0 0

0, 1, 2, 3

x 0 1

1, 2, 3, 0

1, 0, 3, 2

x 1 0

2, 3, 0, 1

x 1 1

3, 0, 1, 2

3, 2, 1, 0

8

0 0 0

0, 1, 2, 3, 4, 5, 6, 7

0 0 1

1, 2, 3, 0, 5, 6, 7, 4

1, 0, 3, 2, 5, 4, 7, 6

0 1 0

2, 3, 0, 1, 6, 7, 4, 5

0 1 1

3, 0, 1, 2, 7, 4, 5, 6

3, 2, 1, 0, 7, 6, 5, 4

1 0 0

4, 5, 6, 7, 0, 1, 2, 3

1 0 1

5, 6, 7, 4, 1, 2, 3, 0

5, 4, 7, 6, 1, 0, 3, 2

1 1 0

6, 7, 4, 5, 2, 3, 0, 1

1 1 1

7, 4, 5, 6, 3, 0, 1, 2

7, 6, 5, 4, 3, 2, 1, 0

Note: 1) Page length is a function of I/O organization

64Mb X 16 organization (CA0-CA9); Page Size = 2K Byte; Page Length = 1024

128Mb X 8 organization (CA0-CA9 ); Page Size = 1K Byte; Page Length = 1024

256Mb x 4 organization (CA0-CA9, CA11); Page Size = 1K Byte; Page Length = 2048

2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or

DDR components

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Burst Read Command

The Burst Read command is initiated by having  and  low while holding  and  high at the rising edge of the

clock. The address inputs determine the starting column address for the burst. The delay from the start of the command

until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output

(DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is

synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with

the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus  latency (CL). The

CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS (1))

Basic Burst Read Timing

DQS,

DQS

DQ

DQS

tRPRE

tDQSQmax

tRPST

tDQSCK tAC

Dout Dout Dout Dout

CLK, CLK

CLK

tCH tCL tCK

DO-Read

tQH DQSQmax

tQH

t

tLZ tHZ

Examples:

Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)

NOP NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

<= tDQSCK

CMD

DQ

BRead523

DQS,

DQS

Post CAS

CK, CK

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Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8)

CMD

NOP NOP NOP NOP NOP NOP

DQ's

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 3

CL = 3

NOP

<= tDQSCK

BRead303

DQS,

DQS

Dout A4 Dout A5 Dout A6 Dout A7

CK, CK

Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around

time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.

NOP Posted CAS

WRITE A NOP NOP NOP NOP

NOP

READ A

Posted CAS

T0 T1

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

NOP

CMD

DQ

BRBW514

Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5

Din A0 Din A1 Din A2 Din A3

DQS,

DQS

WL = RL - 1 = 4

tRTW(Read to Write turn around time)

CK, CK

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Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4

NOP NOP NOP NOP NOP NOP

NOP

READ A

Post CAS READ B

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3

RL = 5

AL = 2 CL = 3

SBR523

CMD

DQ

DQS,

DQS

CK, CK

The seamless burst read operation’s supported by enabling a read command at every clock for BL=4 operation, and every

4 clock for BL=8 operation. This operation allows regardless of same or different banks as long as the banks activated.

Burst Write Command

The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock.

The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one

and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The

first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The

tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the

DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied

to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the

completion of the burst write to bank precharge is named “write recovery time” (WR) .

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the

EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which

the DDR2 SDRAM pin timing measured is mode dependent.

Basic Burst Write Timing

DQS,

DQS DQS

DQS

tDQSH tDQSL

tWPRE WPST

t

Din Din Din Din

tDS tDH

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Example:

Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4

NOP NOP NOP NOP NOP Precharge

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 4

BW543

CMD

DQ

NOP

DIN A0 DIN A1 DIN A2 DIN A3

<= tDQSS

tWR

Completion of

the Burst Write

DQS,

DQS

CK, CK

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Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around

time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation.

Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4

NOP NOP NOP NOP

NOP READ A

Post CAS

BWBR

CMD

DQ

NOP

DIN A0 DIN A1 DIN A2 DIN A3

AL=2 CL=3

NOP NOP

tWTR

T0 T2T1 T3 T4 T5 T6 T7 T8 T9

Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6

DQS,

DQS

WL = RL - 1 = 4

RL=5

CK, CK

The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where

tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the

time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array.

Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4

NOP NOP NOP NOP NOP NOP

NOP

DIN A0 DIN A1 DIN A2 DIN A3

WRITE A

Post CAS

WL = RL - 1 = 4

WRITE B

Post CAS

DIN B0 DIN B1 DIN B2 DIN B3

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

SBR

DQS,

DQS

CK, CK

The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This

operation is allowed regardless of same or different banks as long as the banks are activated.

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Write Data Mask

One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the

implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a

uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit

organization is not used during read cycles. However, DM of x8 bit organization can be used as RDQS during read cycles

by EMRS (1) setting.

Write Data Mask Timing

DQS

DQS, DQS

DQS

tDQSH tDQSL

tWPRE WPST

t

DQ Din Din Din Din

tDS DH

t

DM

don't care

Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = RL-1 = 2

DM

CMD

DQ

NOP

tWR

<= tDQSS

Precharge Bank A

Activate

tRP

DQS,

DQS

DM

DIN A0 DIN A1 DIN A3DIN A2

CK, CK

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Burst Interruption

Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of

8 under the following conditions:

1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or

Precharge Command is prohibited.

2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or

Precharge Command is prohibited.

3. Read burst interrupt occur exactly two clocks after the previous Read command. Any other Read burst

interrupt timings are prohibited.

4. Write burst interrupt occur exactly two clocks after the previous Write command. Any other Read burst

interrupt timings are prohibited.

5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.

6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted.

7. Read burst interruption is allowed by a Read with Auto-Precharge command.

8. Write burst interruption is allowed by a Write with Auto-Precharge command.

9. All command timings are referenced to burst length set in the mode register. They are not referenced to the

actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in

the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge

timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form

the end of the actual burst end.

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Examples:

Read Burst Interrupt Timing Example: (CL = 3, AL = 0, RL = 3, BL = 8)

NOP NOP NOP NOP NOP

NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

RBI

DQS,

DQS

READ B NOP

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7

NOP

CK, CK

Write Burst Interrupt Timing Example: (CL = 3, AL = 0, WL = 2, BL = 8)

NOP NOP NOP NOP

NOP

WRITE A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

WBI

DQS,

DQS

NOP

Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7

NOP

WRITE B

CK, CK

NOP

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Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge

Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The

Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three

address bits A10, BA0, and BA1 are used to define which bank to precharge when the command is issued.

Bank Selection for Precharge by Address Bit

A10

BA1

BA0

Precharge

Bank(s)

LOW

Bank 0 only

LOW

HIGH

Bank 1 only

LOW

HIGH

LOW

Bank 2 only

LOW

HIGH

Bank 3 only

HIGH

Don't Care

all banks

Burst Read Operation Followed by a Precharge

Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks.

For the earliest possible precharge, the Precharge command may be issued on the rising edge which is “Additive Latency

(AL) + BL/2 clocks” after a Read Command, as long as the minimum tRAS timing is satisfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates

the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the

time from the actual read (AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2

clocks after the Read to the Precharge command.

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Examples:

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP ≦ 2 clocks

NOP Precharge NOP Bank A

Activate NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

BR-P413

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1CL = 3

RL = 4

>=tRAS CL = 3

>=tRP

DQS,

DQS

NOP

>=tRC

>=tRTP

CK, CK

Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP ≦ 2 clocks

NOP NOP NOP

Post CAS

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

BR-P413(8)

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 1CL = 3

RL = 4

>=tRAS CL = 3

DQS,

DQS

NOP

>=tRC >=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP NOP

first 4-bit prefetch second 4-bit prefetch

CK, CK

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Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks

NOP NOP NOP Bank A

Activate NOP

NOP

Post CAS

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

BR-P523

NOP

AL + BL/2 clks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2CL = 3

RL = 5

>=tRAS CL = 3

>=tRP

Precharge

DQS,

DQS

>=tRC

>=tRTP

CK, CK

Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP ≦ 2 clocks

NOP NOP

NOP

READ A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

BR-P624

NOP

AL + BL/2 clocks

Dout A0 Dout A1 Dout A2 Dout A3

AL = 2

CL = 4

RL = 6

>=tRAS CL = 4

Precharge

A

Bank A

Activate

DQS,

DQS

NOP NOP

>=tRC

>=tRTP

CK, CK

>=tRP

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Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks

NOP NOP NOP

READ A

T0 T2T1 T3 T4 T5 T6 T7 T8

CMD

DQ

BR-P404(8)

NOP

AL + BL/2 clks + 1

Dout A0 Dout A1 Dout A2 Dout A3

CL = 4

RL = 4

>=tRAS

>=tRP

DQS,

DQS

NOP

>=tRTP

Dout A4 Dout A5 Dout A6 Dout A7

Precharge NOP Bank A

Activate

first 4-bit prefetch second 4-bit prefetch

CK, CK

Burst Write followed by Precharge

Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay

must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.

This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the

Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does

not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table

in this datasheet) and is not the programmed value for tWR in the MRS.

Examples:

Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T

0T

2

T

1T

3T

4T

5T

6T

7T

8

WL = 3

BW-P3

CMD

DQ

NOP

DIN

A0 DIN

A1 DIN

A2 DIN

A3

>=tWR

Completion of

the Burst Write

Precharge

A

NOP

DQS,

DQS

CK, CK

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Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3

NOP NOP NOP NOP

NOP

WRITE A

Post CAS

T0 T2T1 T3 T4 T5 T6 T7 T9

WL = 4

BW-P4

CMD

DQ

NOP

DIN A0 DIN A1 DIN A2 DIN A3

tWR

Completion of

the Burst Write

Precharge

A

NOP

DQS,

DQS

CK, CK

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Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge

Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the 

timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the

earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued,

then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence.

If A10 is high when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During

Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge

internally on the rising edge which is  Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is

also implemented for Write Commands. The precharge operation engaged by the Auto-Precharge command will not begin

until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge

operation to be partially or completely hidden during burst read cycles (dependent upon  Latency) thus improving

system performance for random data access. The RAS lockout circuit internally delays the precharge operation until the

array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write

command.

Burst Read with Auto-Precharge

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM

starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if

tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be

delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will

be delayed until tRTP(min) is satisfied.

In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the

next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate

command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL

+ 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal

precharge does not start earlier than two clocks after the last 4-bit prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously:

(1) The  precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The  cycle time (tRC) from the previous bank activation has been satisfied.

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Examples:

Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit)

RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

DQ

BR-AP5231

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRAS

tRCmin.

NOP

AL + BL/2

CK, CK

Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit):

RL = 5 (AL = 2, CL = 3), BL = 4, tRTP ≦ 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 5

AL = 2 CL = 3

NOP

CMD

DQ

BR-AP5232

A10 ="high"

tRP

Auto-Precharge Begins

DQS,

DQS

tRC

tRAS(min)

NOP

CK, CK

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Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP ≦ 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

DQ

BR-AP413(8)2

A10 ="high" tRP

Auto-Precharge Begins

DQS,

DQS

NOP

Dout A4 Dout A5 Dout A6 Dout A7

first 4-bit prefetch second 4-bit prefetch

>= tRTP

AL + BL/2

CK, CK

Burst Read with Auto-Precharge followed by an Activation to the Same Bank:

RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks

NOP NOP NOP NOP Bank

Activate

NOP

READ w/AP

Posted CAS

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

AL = 1 CL = 3

NOP

CMD

DQ

BR-AP4133

A10 ="high"

Auto-Precharge Begins

DQS,

DQS

NOP

first 4-bit prefetch

tRTP

AL + tRTP + tRP

tRP

CK, CK

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512Mb DDR2 SDRAM

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Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM

automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR),

programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of

the write burst may be reactivated if the following two conditions are satisfied.

(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

Examples:

Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4

NOP NOP NOP NOP NOP Bank A

Activate

NOP

WRITE

w/AP

T0 T2T1 T3 T4 T5 T6 T7

NOP

CMD

DQ

BW-AP223

A10 ="high"

tRP

Auto-Precharge Begins

DIN A0 DIN A1 DIN A2 DIN A3

WL = RL-1 = 2 WR

tRCmin.

DQS,

DQS

Completion of the Burst Write

tDAL

>=tRASmin.

CK, CK

Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4

NOP NOP NOP NOP NOP Bank A

Activate

NOP

Posted CAS

WRITE w/AP

T

0T

3T

4T

5T

6T

7T12

NOP

CMD

DQ

BW-AP423

A10 ="high"

tRP

Auto-Precharge Begins

DIN

A0 DIN

A1 DIN

A2 DIN

A3

WL = RL-1 = 4tWR

>=tRC

T

9

T

8

Completion of the Burst Write

DQS,

DQS

tDAL

>=tRAS

CK, CK

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Precharge & auto precharge clarification

From

Command

To Command

Minimum Delay between "From

command" to "to command"

Units

Note

Read

Precharge (to same Bank as Read)

AL + BL/2 + max(RTP,2) - 2

tCK

1,2

Precharge All

AL + BL/2 + max(RTP,2) - 2

tCK

1,2

Read w/AP

Precharge ( to same Bank as Read wAP)

AL + BL/2 + max(RTP,2) - 2

tCK

1,2

Precharge Al

AL + BL/2 + max(RTP,2) - 2

tCK

1,2

Write

Precharge (to same Bank as Write)

WL + BL/2 + tWR

tCK

2

Precharge Al

WL + BL/2 + tWR

tCK

2

Write w/AP

Precharge (to same bank as Write w/AP)

WL + BL/2 + WR

tCK

2

Precharge Al

WL + BL/2 + WR

tCK

2

Precharge

Precharge (to same bank as Precharge)

1

tCK

2

Precharge Al

1

tCK

2

Precharge All

Precharge

1

tCK

2

Precharge Al

1

tCK

2

Note:

1) RTP [cycles] = RU {tRTP(ns)/tCK(ns)}, where RI stands for round up.

2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge

all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest precharge command issued to that

bank.

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Refresh

SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an

explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows

into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to controlles for distributed

refresh timing. For example, a 1Gbit DDR2 SDRAM has 8392 rows resulting in a tREFI of 7.8 µs.

Auto-Refresh Command

Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued

each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the

address bits ”Don’t Care” during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an

average periodic interval of tREFI (maximum).

When ,  and  are held low and  high at the rising edge of the clock, the chip enters the Auto-Refresh mode.

All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh

Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the

external address bus is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the

Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or

equal to the Auto-Refresh cycle time (tRFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval

is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the

maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI.

T0 T2T1 T3

AR

CK, CK

CMD

Precharge

> = t

RP

NOP AUTO

REFRESH ANYNOP

> = t

RFC

> = t

RFC

AUTO

REFRESH

NOP NOP NOP

CKE "high"

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Self-Refresh Command

The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the

Self-Refresh mode, the DDR2 SDRAM retains data without external clocking.

The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is

defined by having , ,  and  held low with  high at the rising edge of the clock. ODT must be turned off

before issuing Self Refresh command, by either driving ODT pin low or using EMRS (1) command. Once the command is

registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered

Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during

Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one

clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit

Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must

be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit

period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge

during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be

turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the tXSRD timing is satisfied.

CK/CK

T1 T3T2

CK/CK may

be halted CK/CK must

be stable

CKE >=tXSRD

>= tXSNR

Tn TrTmT5

T4

tRP* tis

tAOFD

CMD Self Refresh

Entry NOP Non-Read

Command Read

Command

T0

tis

ODT

* Device must be in theing "All banks idle" state to enter Self Refresh mode.

* ODT must be turned off prior to entering Self Refresh mode.

* tXSRD (>=200 tCK) has to be satisfied for a Read or as Read with Auto-Precharge commend.

* tXSNR has to be satisfied for any command execept Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns.

* The minium CKE low time is defined by the tCKEmin. timming paramester.

* Since CKE is an SSTL input, VREF must maintained during Self-Refresh.

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Power-Down

Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not

allowed to go low while mode register or extended mode register command time, or read or write operation is in progress.

CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is

in progress, but power-down IDD specification will not be applied until finishing those operations.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down

mode for proper read operation.

If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two

different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “low” this mode

is referred as “standard active power-down mode” and a fast power-down exit timing defined by the tXARD timing parameter

can be used. When A12 is set to “high” this mode is referred as a power saving “low power active power-down mode”. This

mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied.

Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled

upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active

power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2

SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A

valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high.

Power-down exit latencies are defined in the AC spec table of this data sheet.

Power-Down Entry

Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a

precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh

command or MRS / EMRS(1) command when tMRD is satisfied.

Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until

the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge

command is allowed after RL + BL/2 is satisfied.

Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case

of a write command, active power-down mode entry is allowed then WL + BL/2 + tWTR is satisfied.

In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command

has been executed, which WL + BL/2 + WR is starting from the write with Auto-Precharge command. In case the DDR2

SDRAM enters the Precharge Power-down mode.

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512Mb DDR2 SDRAM

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Examples:

Active Power-Down Mode Entry and Exit after an Activate Command

NOP NOP

Activate

T0 T2T1

CMD NOP

Tn Tn+1

CKE

Active

Power-Down

Entry

NOP NOP

Act.PD 0

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4

NOP NOP

READ

T0 T2T1 T3 T4 T5 T6 T7 T8

Dout A0 Dout A1 Dout A2 Dout A3

RL = 4

CL = 3

CMD

DQ

DQS,

DQS

NOP NOP NOP NOP NOP NOP

Tn Tn+1

CKE

AL = 1

Active

Power-Down

Entry

RL + BL/2

NOP NOP

Act.PD 1

tIS

Tn+2

tIS

Active

Power-Down

Exit

Valid

Command

tXARD or

tXARDS *)

CK, CK

READ w/AP

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512Mb DDR2 SDRAM

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REV 1.8

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Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4

NOP NOP

WRITE

T0 T2T1 T3 T4 T5 T6 T7

CMD

DQ

DQS,

DQS

NOP NOP NOP NOP NOP NOP

Tn Tn+1

CKE

WL = RL - 1 = 2

Active

Power-Down

Entry

WL + BL/2 + tWTR

NOP NOP

Act.PD 2

tWTR

tIS

Tn+2

tIS

Valid

Command

Active

Power-Down

Exit

tXARD or

tXARDS *)

CK, CK

DIN

A0 DIN

A1 DIN

A2 DIN

A3

Precharge Power Down Mode Entry and Exit

tXP

NOP NOP

Precharge

*)

T0 T2T1

CMD

NOP NOP

Tn Tn+1

CKE

Precharge

Power-Down

Entry

NOP NOP

PrePD

tIS

Tn+2

tIS

Precharge

Power-Down

Exit

Valid

Command

tRP

NOP

T3

*) "Precharge" may be an external command or an internal

precharge following Write with AP.

CK, CK

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No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No

Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No

Operation Command is registered when  is low with , , and  held high at the rising edge of the clock. A No

Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when  is

brought high, the , , and  signals become don’t care.

Input Clock Frequency Change

During operation the DRAM input clock frequency can be changed under the following conditions:

a) During Self-Refresh operation

b) DRAM is in Precharge Power-down mode and ODT is completely turned off.

The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must

be at a logic “low” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock

frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a “high” logic

level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL

re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the

new clock frequency.

Example:

Input frequency change during Precharge Power-Down mode

NOP NOP

T0 T2T1 T3 T4 Tx Tx+1 Ty

CMD

NOP NOP NOP NOP NOP DLL

RESET

Ty+2 Ty+3

CKE

Frequency Change

occurs here

NOP NOP

Frequ.Ch.

Tz

tXP

Stable new clock

before power-down exit

CK, CK

tRP

tAOFD Minimum 2 clocks

required before

changing the frequency

Ty+1

NOP Valid

Command

200 clocks

ODT is off during

DLL RESET

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Asynchronous CKE Low Event

DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously

drops “low” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event

occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the

input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization

sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC

timing parametric table for tdelay specification.

Asynchronous CKE Low Event

CKE

CKE drops low due to an

asynchronous reset event Clocks can be turned off after

this point

tdelay

CK, CK

stable clocks

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Truth Table

Command Truth Table

Function

CKE

CS

RAS

CAS

WE

BA0-BA2

A13-A11

A10

A9 - A0

Notes

Current

Cycle

(Extended) Mode Register

Set

H

L

BA

OP Code

1, 2

Auto-Refresh

H

L

H

X

1

Self-Refresh Entry

H

L

H

X

1,8

Self-Refresh Exit

L

H

X

1,7,8

L

H

Single Bank Precharge

H

L

H

L

BA

X

L

X

1,2

Precharge all Banks

H

L

H

L

X

H

X

1

Bank Activate

H

L

H

BA

Row Address

1,2

Write

H

L

H

L

BA

Column

L

Column

1,2,3

Write with Auto-Precharge

H

L

H

L

BA

Column

H

Column

1,2,3

Read

H

L

H

L

H

BA

Column

L

Column

1,2,3

Read with Auto-Precharge

H

L

H

L

H

BA

Column

H

Column

1,2,3

No Operation

H

X

L

H

X

1

Device Deselect

H

X

H

X

1

Power Down Entry

H

L

H

X

1,4

L

H

Power Down Exit

L

H

X

1,4

L

H

1. All DDR2 SDRAM commands are defined by states of , , , , and CKE at the rising edge of the clock.

2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register.

3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" inspection for

details.

4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

6. X means "H or L (but a defined logic level)".

7. Self refresh exit is asynchronous.

8. Vref must be maintained during Self Refresh operation.

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Clock Enable (CKE) Truth Table for Synchronous Transitions

Current State 2

CKE

Command (N) 3

, , , 

Action (N) 3

Notes

(N-1)

Current

Cycle 1

(N)

Power-Down

L

X

Maintain Power-Down

11, 13, 15

L

H

DESELECT or NOP

Power-Down Exit

4, 8, 11, 13

Self Refresh

L

X

Maintain Self Refresh

11, 15, 16

L

H

DESELECT or NOP

Self Refresh Exit

4, 5, 9, 16

Bank(s) Active

H

L

DESELECT or NOP

Active Power-Down Entry

4,8,10,11,13

All Banks Idle

H

L

DESELECT or NOP

Precharge Power-Down

Entry

4,8,10,11,13

H

L

AUTOREFRESH

Self Refresh Entry

6, 9, 11,13

Any State other

than listed above

H

Refer to the Command Truth Table

7

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.

3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N).

4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may

be issued only after tXSRD (200 clocks) is satisfied.

6. Self Refresh mode can only be entered from the All Banks Idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELCT only.

10. Power-Down and Self Refresh cannot be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh

operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions.

11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefore limited by the refresh

requirements.

14. CKE must be maintained high while the device is in OCD calibration mode.

15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However DT must be driven high or low in Power Down if

the ODT function is enabled (Bit A2 or A6 set to "1" in MRS(1)).

16. Vref must be maintained during Self Refresh operation

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512Mb DDR2 SDRAM

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Operating Conditions

Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

Notes

VDD

Voltage on VDD pin relative to VSS

-1.0 to + 2.3

V

1,3

VDDQ

Voltage on VDDQ pin relative to VSS

-0.5 to + 2.3

V

1,3

VDDL

Voltage on VDDL pin relative to VSS

-0.5 to + 2.3

V

1,3

VIN, VOUT

Voltage on any pin relative to VSS

-0.5 to + 2.3

V

1

TSTG

Storage Temperature

-55 to + 100

℃

1, 2

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV.

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Units

Notes

TOPER

Operating Temperature

0 to 95 (Standard Grade)

℃

1,2

- 40 to 95 (Industrial Grade)

1

Note:

1. Operating temperature is the case surface temperature (TCASE) on the center/top side of the DRAM.

2. At 85℃~ 95℃ TOPER, it is required to set tRFI=3.9μs in auto refresh mode or to set ‘1’ for EMRS (2) bit A7 in self refresh mode.

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AC & DC Operating Conditions

DC Operating Conditions

Recommended DC Operating Conditions (SSTL_18)

Symbol

Parameter

Rating

Units

Notes

Min.

Typ.

Max.

VDD

Supply Voltage

1.7

1.8

1.9

V

1

VDDDL

Supply Voltage for DLL

1.7

1.8

1.9

V

5

VDDQ

Supply Voltage for Output

1.7

1.8

1.9

V

1,5

VREF

Input Reference Voltage

0.49 * VDDQ

0.5 * VDDQ

0.51 * VDDQ

V

2, 3

VTT

Termination Voltage

VREF - 0.04

VREF

VREF + 0.04

V

4

1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be

about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc).

4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must

track variations in die dc level of VREF.

5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ, and VDDL tied together.

ODT DC Electrical Characteristic

Parameter / Condition

Symbol

min.

nom.

max.

Units

Notes

Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm

Rtt1(eff)

60

75

90

ohms

1

Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 150 ohm

Rtt2(eff)

120

150

180

ohms

1

Rtt eff. impedance value for EMRS(1)(A6,A2)=1,1; 50 ohm

Rtt3(eff)

40

50

60

ohms

1

Deviation of VM with respect to VDDQ / 2

delta VM

-6

6

%

2

1) Measurement Definition for Rtt(eff):

Apply VIHac and VILac to test pin separately, then measure current I(VIHac) and I(VILac) respectively.

Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac))

2) Measurement Definition for VM:

Measure voltage (VM) at test pin (midpoint) with no load:

delta VM =(( 2* VM / VDDQ) - 1 ) x 100%

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DC & AC Logic Input Levels

DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the

EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by

which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are

measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships

are measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed

by design and characterization. In single ended mode, the DQS (and RDQS) signals are internally disabled and don’t care.

Single-ended DC & AC Logic Input Levels

Symbol

Parameter

DDR2-667/800/1066

Units

Min.

Max.

VIH (dc)

DC input logic high

VREF + 0.125

VDDQ + 0.3

V

VIL (dc)

DC input low

-0.3

VREF - 0.125

V

VIH (ac)

AC input logic high

VREF + 0.200

VDDQ+Vpeak

V

VIL (ac)

AC input low

VSSQ-Vpeak

VREF - 0.200

V

Single-ended AC Input Test Conditions

Symbol

Condition

Value

Units

Notes

VREF

Input reference voltage

0.5 * VDDQ

V

1, 2

VSWING(max)

Input signal maximum peak to peak swing

1

V

1, 2

SLEW

Input signal minimum slew rate

1

V / ns

3, 4

1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh.

2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.

3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the

range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure.

4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to

VIL(ac) on the negative transitions.

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Differential DC and AC Input and Output Logic Levels

Symbol

Parameter

min.

max.

Units

Notes

VID(ac)

AC differential input voltage

0.5

VDDQ

V

1

VIX(ac)

AC differential cross point input voltage

0.5 * VDDQ - 0.175

0.5 * VDDQ + 0.175

V

2

VOX(ac)

AC differential cross point output voltage

0.5 * VDDQ - 0.125

0.5 * VDDQ + 0.125

V

3

Notes:

1) VID(ac) specifices the allowable DC execution of each input of differential pair such as CK, , DQS, , LDQS, , UDQS, and

.

2) VIX(ac) specifices the input differential voltage lVTR-VCPl required for switching, where VTR is the true input (such as CK, DQS, LDQS, or

UDQS) level and VCP is the complementary input (such , , , or  ) level. The minimum value is equal to VIH(DC) - VIL(DC).

3) The typical value of VOX(AC) is expected to be about 0.5VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ.

VOX(AC) indicates the voltage at which differential signals must cross.

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Output Buffer Levels

Output AC Test Conditions

Symbol

Parameter

SSTL-18 Class II

Units

Notes

VOTR

Output Timing Measurement Reference Level

0.5 * VDDQ

V

1

1. The VDDQ of the device under test is referenced.

Output DC Current Drive

Symbol

Parameter

SSTL-18

Units

Notes

IOH(dc)

Output Minimum Source DC Current, nominal

-13.4

mA

1, 3, 4

IOL(dc)

Output Minimum Sink DC Current, nominal

13.4

mA

2, 3, 4

1. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of VOUT between 0V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to

ensure VIHmin. plus a noise margin and VILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values

are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement.

OCD Default Setting Table

Symbol

Description

Min.

Nominal

Max.

Unit

Notes

-

Pull-up / Pull down mismatch

0

-

4

Ohms

6

-

Output Impedance step size for OCD calibration

0

-

1.5

Ohms

1,2,3

SOUT

Output Slew Rate

1.5

-

5

V / ns

1,4,5,7,8

1) Absolute Specification: TOPEN; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V.

2) Impedance measurement condition for output source dc current: VDDQ = 1.7V, VOUT = 1420 mV; (VOUT-VDDQ)/IOH must be less than 23.4 ohms for

values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280mV; VOUT / IOL

must be less than 23.4 ohms for values of VOUT between 0V and 280 mV.

3) Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage.

4) Slew rates measured from VIL(AC) to VIH(AC) with the load specified in Section 8.2.

5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is

guaranteed by design and characterization.

6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM

uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 ohms under nominal conditions.

7) DRAM output slew rate specification applies to 533MT/s, 667MT/s, and 800MT/s speed pin.

8) Timing skew due to DRAM output slew rate mis-match between DQS /  and associated DQ's is included in tDQSQ and tQHS specification.

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Default Output V-I Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS (1) bits

A7~A9 = ’111’. The driver characteristics evaluation conditions area) Nominal Default 25℃ (Tcase), VDDQ=1.8V, typical

process. b) Minimum TOPER(max), VDDQ=1.7V, slow-slow process. c) Maximum 0℃ (Tcase), VDDQ=1.9V, fast-fast

process

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Full Strength Default Pullup Driver Characteristics

Voltage (V)

Minimum

(23.4 Ohms)

Nomal Default low

(18 Ohms)

Nomal Default high

(18 Ohms)

Maximum

(12.6 Ohms)

0.0

0.00

0.1

-4.30

-5.65

-5.90

-7.95

0.2

-8.60

-11.30

-11.80

-15.90

0.3

-12.90

-16.50

-16.80

-23.85

0.4

-16.90

-21.20

-22.10

-31.80

0.5

-20.05

-25.00

-27.60

-39.75

0.6

-22.10

-28.30

-32.40

-47.70

0.7

-23.27

-30.90

-36.90

-55.55

0.8

-24.10

-33.00

-40.90

-62.95

0.9

-24.73

-34.50

-44.60

-69.55

1.0

-25.23

-35.50

-47.70

-75.35

1.1

-25.65

-36.10

-50.40

-80.35

1.2

-26.02

-36.60

-52.60

-84.55

1.3

-26.35

-36.90

-54.20

-87.95

1.4

-26.65

-37.10

-55.90

-90.70

1.5

-26.93

-37.40

-57.10

-93.00

1.6

-27.20

-37.60

-58.40

-95.05

1.7

-27.46

-37.70

-59.60

-97.05

1.8

-

-37.90

-60.90

-99.05

1.9

-

-101.05

The driver characteristics evaluetion conditions are:

Nominal Default 25℃ (Tcase) , VDDQ = 1.8 V, typical process

Minimum Toper(max.), VDDQ = 1.7V, slow-slow process

Maximum 0 ℃ (Tcase). VDDQ = 1.9 V, fast-fast process

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Full Strength Default Pulldown Driver Characteristics

Voltage (V)

Minimum

(23.4 Ohms)

Nomal Default low

(18 Ohms)

Nomal Default high

(18 Ohms)

Maximum

(12.6 Ohms)

0.0

0.00

0.1

4.30

5.65

5.90

7.95

0.2

8.60

11.30

11.80

15.90

0.3

12.90

16.50

16.80

23.85

0.4

16.90

21.20

22.10

31.80

0.5

20.05

25.00

27.60

39.75

0.6

22.10

28.30

32.40

47.70

0.7

23.27

30.90

36.90

55.55

0.8

24.10

33.00

40.90

62.95

0.9

24.73

34.50

44.60

69.55

1.0

25.23

35.50

47.70

75.35

1.1

25.65

36.10

50.40

80.35

1.2

26.02

36.60

52.60

84.55

1.3

26.35

36.90

54.20

87.95

1.4

26.65

37.10

55.90

90.70

1.5

26.93

37.40

57.10

93.00

1.6

27.20

37.60

58.40

95.05

1.7

27.46

37.70

59.60

97.05

1.8

-

37.90

60.90

99.05

1.9

-

101.05

The driver characteristics evaluetion conditions are:

Nominal Default 25℃ (Tcase) , VDDQ = 1.8 V, typical process

Minimum Toper(max.), VDDQ = 1.7V, slow-slow process

Maximum 0 ℃ (Tcase). VDDQ = 1.9 V, fast-fast process

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Calibrated Output Driver V-I Characteristics

DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure

outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable

for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high

values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact

nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real

system calibration error needs to be added to these values. It must be understood that these V-I curves are represented

here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this a

system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM

portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to

operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters

in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated

between the minimum and maximum default values at all times. If this can’t be guaranteed by the system calibration

procedure, re-calibration policy and uncertainty with DQ to DQ variation, it is recommend that only the default values to be

used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result

of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an

extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice

versa.

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Full Strength Calibrated Pulldown Driver Characteristics

Voltage (V)

Nominal Minimum

(21 Ohms)

Normal Low

(18.75 Ohms)

Nominal

(18 ohms)

Normal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2

9.5

10.7

11.5

11.8

13.3

0.3

14.3

16.0

16.6

17.4

20.0

0.4

18.7

21.0

21.6

23.0

27.0

The driver characteristics evaluation conditions are:

Nominal 25℃ (Tcase) , VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25℃ (Tcase), VDDQ = 1.8V, any process

Nominal Minimum Toper(max), VDDQ = 1.7 V, any process

Nominal Maximum 0℃(Tcase), VDDQ = 1.9 V, any process

Full Strength Calibrated Pullup Driver Characteristics

Voltage (V)

Nominal Minimum

(21 Ohms)

Normal Low

(18.75 Ohms)

Nominal

(18 ohms)

Normal High

(17.25 Ohms)

Nominal Maximum

(15 Ohms)

0.2

-9.5

-10.7

-11.4

-11.8

-13.3

0.3

-14.3

-16.0

-16.6

-17.4

-20.0

0.4

-18.7

-21.0

-21.6

-23.0

-27.0

The driver characteristics evaluation conditions are:

Nominal 25℃ (Tcase) , VDDQ = 1.8 V, typical process

Nominal Low and Nominal High 25℃(Tcase), VDDQ = 1.8V, any process

Nominal Minimum Toper(max), VDDQ = 1.7 V, any process

Nominal Maximum 0℃ (Tcase), VDDQ = 1.9 V, any process

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Symbol

Parameter

-3C/3CI

-AC/ACI

-BE

-BD

Units

min.

max.

min.

max.

min.

max.

min.

max.

CCK

Input capacitance, CK and 

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

pF

CDCK

Input capacitance delta, CK and 

-

0.25

-

0.25

-

0.25

-

0.25

pF

CI

Input capacitance, all other input-only pins

1.0

2.0

1.0

1.75

1.0

1.75

1.0

1.75

pF

CDI

Input capacitance delta, all other input-only pins

-

0.25

-

0.25

-

0.25

-

0.25

pF

CIO

Input/output capacitance,

DQ, DM, DQS, 

2.5

3.5

2.5

3.5

2.5

3.5

2.5

3.5

pF

CDIO

Input/output capacitance delta,

DQ, DM, DQS, 

-

0.5

-

0.5

-

0.5

-

0.5

pF

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Power & Ground Clamp V-I Characteristics

Power and Ground clamps are provided on address (A0~A13, BA0, BA1, BA2), , , , WE, CKE, and

ODT pins. The V-I characteristics for pins with clamps is shown in the following table

Voltage across

clamp (V)

Minimum Power

Clamp Current (mA)

Minimum Ground

Clamp Current (mA)

0.0

0.1

0.0

0.2

0.0

0.3

0.0

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.8

0.1

0.9

1.0

2.5

1.1

4.7

1.2

6.8

1.3

9.1

1.4

11.0

1.5

13.5

1.6

16.0

1.7

18.2

1.8

21.0

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IDD Specifications and Measurement Conditions

IDD Specifications

(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)

Symbol

Parameter/Condition

I/O

-3C/-3CI

-AC/-ACI

-BE

-BD

Unit

Notes

IDD0

Operating Current

x8

x16

60

65

70

75

80

75

80

mA

1,2

IDD1

Operating Current

x8

x16

75

90

85

110

100

130

100

130

mA

1,2

IDD2P

Precharge Power-Down Current

All

6

mA

1,2

IDD2N

Precharge Standby Current

All

40

45

50

mA

1,2

IDD2Q

Precharge Quiet Standby Current

All

45

50

55

mA

1,2

IDD3P

Active Power-Down Standby Current

MRS(12)=0

All

25

30

35

mA

1,2

MRS(12)=1

All

11

mA

1,2

IDD3N

Active Standby Current

x8

x16

35

55

45

60

55

70

55

70

mA

1,2

IDD4R

Operating Current Burst Read

/x8

x16

100

130

115

160

130

180

130

180

mA

1,2

IDD4W

Operating Current Burst Write

x8

x16

100

130

120

190

155

250

155

250

mA

1,2

IDD5

Auto-Refresh Current

/x8

x16

140

190

155

200

180

210

180

210

mA

1,2

IDD6

Self-Refresh Current for standard products

All

6

mA

1,2

IDD7

Operating Current

/x8

x16

200

230

220

260

250

320

250

320

mA

1,2

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IDD Measurement Conditions

(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)

IDD1

Operating Current - One bank Active - Read - Precharge

IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL =

0; CKE is HIGH,  is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus

inputs are SWITCHING;

IDD2P

Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address

inputs are STABLE, Data Bus inputs are FLOATING.

IDD2N

Precharge Standby Current: All banks idle;  is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and

address bus inputs are SWICHTING; Data bus inputs are SWITCHING.

IDD2Q

Precharge Quiet Standby Current:All banks idle;  is HIGH; CKE is HIGH; tCK = tCKmin.; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING.

IDD3P(0)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address

inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit);

IDD3P(1)

Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address

inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit);

IDD3N

Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH;

 is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs

are SWITCHING.

IDD4R

Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK

= tCKmin.; tRAS = tRASmax., tRP = tRPmin., CKE is HIGH,  is HIGH between valid commands; Address

inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA.

IDD4W

Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK

= tCKmin.; tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH,  is HIGH between valid commands; Address

inputs are SWITCHING; Data Bus inputs are SWITCHING.

IDD5

Auto-Refresh Current: tRC = tRFC(min) which is 8 * tCK for DDR200 at tCK = 10 ns, 10 * tCK for DDR266

at tCK = 7.5 ns; 12 * tCK for DDR333 at tCK = 6ns; 14 * tCK for DDR400 at tCK = 5ns

IDD6

Self-Refresh Current: CKE <= 0.2V; external clock off, CK and  at 0V; Other control and address inputs

are FLOATING; Data Bus inputs are FLOATING.

IDD7

Operating Bank Interleave Read Current:

1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin.,

tRC = TRCmin.; tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTS.

2. Timing pattern:

- DDR2 -667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D

- DDR2 -800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D

- DDR2 -1066 6-6-6: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D

3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT

1. IDD specifications are tested after the device is properly initialized.

2. IDD parameter are specified with ODT disabled.

3. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.

4. Definitions for IDD :

LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);

STABLE is defined as inputs are stable at a HIGH or LOW level

FLOATING is defined as inputs are VREF = VDDQ / 2

SW ITCHING is defined as:

Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control

signals, and

inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including

mask or strobes

5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table.

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IDD Measurement Conditions (cont’d)

For testing the IDD parameters, the following timing parameters are used:

Parameter

Symble

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Latency

CL

5

7

6

tCK(avg)

Clock Cycle Time

tCK

3

2.5

1.875

ns

Active to Read or Write delay

tRCD

15

12.5

13.125

11.25

ns

Active to Active / Auto-Refresh

command period

tRC

60

57.5

58.125

56.25

ns

Active bank A to Active bank B

command delay

x8

tRRD

7.5

ns

x16

10

Active to Precharge Command

tRASmin

40

ns

tRASmax

70000

Precharge Command Period

tRP

15

12.5

13.125

11.25

ns

Refresh parameters

Parameter

Symbol

Component Type

512Mb

Unit

Auto-Refresh to Active / Auto-Refresh

command period

tRFC

All

105

ns

Average periodic Refresh interval

tREFI

Standard Grade

(0℃≦Tcase≦85℃)

7.8

μs

(85℃≦Tcase≦95℃)

3.9

Industry Grade

(-40℃≦Tcase≦95℃)

7.8

μs

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Electrical Characteristics & AC Timing - Absolute Specification

Timing Parameter by Speed Grade

(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)

Symbol

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tCK(avg)

Clock cycle time, CL=x, (Average)

3000

8000

2500

8000

1875

8000

1875

8000

ps

tCH(avg)

CK, high-level width (Average)

0.48

0.52

0.48

0.52

0.48

0.52

0.48

0.52

tCK(avg)

tCL(avg)

CK, low-level width (Average)

0.48

0.52

0.48

0.52

0.48

0.52

0.48

0.52

tCK(avg)

WL

Write command to DQS associated clock edge

RL-1

nCK

tDQSS

DQS latching rising transitions to associated clock edges

-0.25

0.25

-0.25

0.25

-0.25

0.25

-0.25

0.25

tCK(avg)

tDSS

DQS falling edge to CK setup time

0.2

-

0.2

-

0.2

-

0.2

-

tCK(avg)

tDSH

DQS falling edge hold time from CK

0.2

-

0.2

-

0.2

-

0.2

-

tCK(avg)

tDQSL,H

DQS input low (high) pulse width

0.35

-

0.35

-

0.35

-

0.35

-

tCK(avg)

tWPRE

Write preamble

0.35

-

0.35

-

0.35

-

0.35

-

tCK(avg)

tWPST

Write postamble

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK(avg)

tIS

Address and control input setup time

200

-

175

-

125

-

125

-

ps

tIH

Address and control input hold time

275

-

250

-

200

-

200

-

ps

tIPW

Address and control input pulse width (each input)

0.6

-

0.6

-

0.6

-

0.6

-

tCK(avg)

tDS

DQ and DM input setup time

differential

100

-

50

-

0

-

0

-

ps

tDH

DQ and DM input hold time

differential

175

-

125

-

75

-

75

-

ps

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Symbol

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tDIPW

DQ and DM input pulse width

(each input)

0.35

-

0.35

-

0.35

-

0.35

-

tCK(avg)

tAC

DQ output access time from CK / 

-450

450

-400

400

-350

350

-350

350

ps

tDQSCK

DQS output access time from CK / 

-400

400

-350

350

-325

325

-325

325

ps

tHZ

Data-out high-impedance time from CK /

-

tAC,max

-

tAC,max

-

tAC,max

-

tAC,max

ps

tLZ(DQS)

DQS() low-impedance time from CK / 

tAC,min

tAC,max

tAC,min

tAC,max

tAC,min

tAC,max

tAC,min

tAC,max

ps

tLZ(DQ)

DQ low-impedance time from CK /

2 x

tAC,min

tAC,max

2 x

tAC,min

tAC,max

2 x

tAC,min

tAC,max

2 x

tAC,min

tAC,max

ps

tDQSQ

DQS-DQ skew

(for DQS & associated DQ signals)

-

240

-

200

-

175

-

175

ps

tHP

Clock half period

Min

(tCH(avg)

tCL(avg) )

-

Min

(tCH(avg)

tCL(avg) )

-

Min

(tCH(avg)

tCL(avg) )

-

Min

(tCH(avg)

tCL(avg) )

-

ps

tQHS

Data hold skew factor

-

340

-

300

-

250

-

250

ps

tQH

Data output hold time from DQS

tHP -

tQHS

-

tHP -

tQHS

-

tHP -

tQHS

-

tHP -

tQHS

-

ps

tRPRE

Read preamble

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

tCK(avg)

tRPST

Read postamble

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK(avg)

tRRD

Active bank A to Active bank B

command period

X8

7.5

-

7.5

-

7.5

-

7.5

-

ns

X16

10

tFAW

Four Activate Window

X8

37.5

-

35

-

35

-

35

-

ns

X16

50

45

tCCD

 A to B command period

2

-

2

-

2

-

2

-

nCK

tWR

Write recovery time

15

-

15

-

15

-

15

-

ns

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Symbol

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tDAL

Auto-Precharge write recovery

+ precharge time

WR +

tnRP

-

WR +

tnRP

-

WR + tnRP

-

WR +

tnRP

-

nCK

tWTR

Internal Write to Read command

delay

7.5

-

7.5

-

7.5

-

7.5

-

ns

tRTP

Internal Read to Precharge

command delay

7.5

-

7.5

-

7.5

-

7.5

-

ns

tCKE

CKE minimum high and low pulse

width

3

-

3

-

3

-

3

-

nCK

tXSNR

Exit Self-Refresh to non-Read

command

tRFC +

10

-

tRFC + 10

-

tRFC + 10

-

tRFC +

10

-

ns

tXSRD

Exit Self-Refresh to Read command

200

-

200

-

200

-

200

-

nCK

tXP

Exit precharge power-down to any

valid command (other than NOP or

Deselect)

2

-

2

-

3

-

3

-

nCK

tXARD

Exit power down to any valid

command

(other than NOP or Deselect)

2

-

2

-

3

-

3

-

nCK

tXARDS

Exit active power-down mode to

Read command (slow exit, lower

power)

7-AL

-

8-AL

-

10-AL

-

10-AL

-

nCK

tAOND

ODT turn-on delay

2

nCK

tAON

ODT turn-on

tAC,min

tAC,max

+ 0.7

tAC,min

tAC,max

+ 0.7

tAC,min

tAC,max

+ 2.575

tAC,min

tAC,max

+ 2.575

ns

tAONPD

ODT turn-on (Power-Down mode)

tAC,min

+ 2

2 x

tCK(avg) +

tAC,max +

1

tAC,min +

2

2 x

tCK(avg)

+

tAC,max

+ 1

tAC,min +

2

3 x

tCK(avg)

+

tAC,max

+ 1

tAC,min

+ 2

3 x

tCK(avg) +

tAC,max +

1

ns

tAOFD

ODT turn-off delay

2.5

nCK

tAOF

ODT turn-off

tAC,min

tAC,max +

0.6

tAC,min

tAC,max

+ 0.6

tAC,min

tAC,max

+ 0.6

tAC,min

tAC,max +

0.6

ns

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Symbol

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

tAOFPD

ODT turn-off (Power-Down mode)

tAC,min

+ 2

2.5 x

tCK(avg) +

tAC,max +

1

tAC,min

+ 2

2.5 x

tCK(avg) +

tAC,max +

1

tAC,min

+ 2

2.5 x

tCK(avg) +

tAC,max +

1

tAC,min

+ 2

2.5 x

tCK(avg) +

tAC,max +

1

ns

tANPD

ODT to power down entry latency

3

-

3

-

4

nCK

tAXPD

ODT power down exit latency

8

-

8

-

11

-

11

-

nCK

tMRD

Mode register set command cycle

time

2

-

2

-

2

-

2

-

nCK

tMOD

MRS command to ODT update

delay

0

12

0

12

0

12

0

12

ns

tOIT

OCD drive mode output delay

0

12

0

12

0

12

0

12

ns

tDELAY

Minimum time clocks remain ON

after CKE asynchronously drops

LOW

tIS +

tCK(avg)

+ tIH

-

tIS +

tCK(avg)

+ tIH

-

tIS +

tCK(avg)

+ tIH

-

tIS +

tCK(avg)

+ tIH

-

ns

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General Note 1 DDR2 SDRAM AC timing reference load

The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not

intended to either a precise representation of the typical system environment or a depiction of the actual load presented by

a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a

system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line

terminated at the tester electronics. This reference load is also used for output slew rate characterization.

The output timing reference voltage level for single ended signals is the cross point with VTT.

The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the

complement (e.g. ) signal.

General Note 2 Slew Rate Measurement Levels

a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for

single ended signals. For differential signals (e.g. DQS - ) output slew rate is measured between DQS -

= - 500mV and DQS -  = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily

tested on each device.

b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from

Vref(dc) to VIL(ac),max for falling edges.

For differential signals (e.g. CK - ) slew rate for rising edges is measured from CK -  = - 250 mV to CK -

 = + 500 mV (+ 250 mV to - 500 mV for falling edges).

c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on , or

between DQS and  for differential strobe.

General Note 3 DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as following

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General Note 4 Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system

design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended

mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In

differential mode, these timing relationships are measured relative to the crosspoint of DQS and its

complement, . This distinction in timing methods is guaranteed by design and characterization. Note that

when differential data strobe mode is disabled via the EMRS, the complementary pin, , must be tied

externally to VSS through a 20 Ω to 10 kΩ resistor to insure proper operation.

General Note 5 AC timings are for linear signal transitions. See Specific Notes on derating for other signal

transitions.

General Note 6 All voltages are referenced to VSS.

General Note 7 These parameters guarantee device behavior, but they are not necessarily tested on each

device..

General Note 8 Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at

nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for

the full voltage range specified.

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Specific notes for dedicated AC parameters

Specific Note 1 User can choose which active power down exit timing to use via MRS (bit 12). tXARD is

expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active

power down exit timing where a lower power value is defined by each vendor data sheet.

Specific Note 2 AL = Additive Latency.

Specific Note 3 This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that

the tRTP and tRAS(min) have been satisfied.

Specific Note 4 A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency.

Specific Note 5 Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes

on derating for other slew rate values.

Specific Note 6 Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input

slew rate of 1.0V/ns. See Specific Notes on derating for other slew rate values.

Specific Note 7 Timings are specified with CK/ differential slew rate of 2.0 V/ns. Timings are guaranteed for

DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in

single ended mode. See Specific Notes on derating for other slew rate values.

Specific Note 8 Data setup and hold time derating.

Data Setup (tDS) and Hold Time (tDH) Derating Table with differential data strobe

DQ Slewrate (V/ns)

DQS,  Differential Slew Rate (-3C/-3CI/-AC/-ACI/-ACL/-BE/-BD)

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

D tDS

D tDH

2.0

100

45

100

45

100

45

-

1.5

67

21

67

21

67

21

79

33

-

1.0

0

12

24

-

0.9

-

-5

-14

-5

-14

7

-2

19

10

31

22

-

0.8

-

-13

-31

-1

-19

11

-7

23

5

35

17

-

0.7

-

-10

-42

2

-30

14

-18

26

-6

38

6

-

0.6

-

-10

-59

2

-47

14

-35

26

-23

38

-11

0.5

-

-24

-89

-12

-77

0

-65

12

-53

0.4

-

-52

-140

-40

-128

-28

-116

1. All units in ps.

2. For all input signals the total Tds (setup time) and Tdh (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table

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Specific Note 9 tIS and tIH (input setup and hold) derating

Input Setup (tIS) and Hold (tIH) Time Derating Table

Command/Address Slew rate (V/ns)

CK,  Differential Slew Rate

Units

(-3C/-3CI/-AC/-ACI/-ACL/-BE/-BD)

2.0 V/ns

1.5 V/ns

1.0 V/ns

D tIS

D tIH

D tIS

D tIH

D tIS

D tIH

4.00

150

94

180

124

210

154

ps

3.50

143

89

173

119

203

149

ps

3.00

133

83

163

113

193

143

ps

2.50

120

75

150

105

180

135

ps

2.00

100

45

130

75

160

105

ps

1.50

67

21

97

51

127

81

ps

1.00

0

30

60

ps

0.90

-5

-14

25

16

55

46

ps

0.80

-13

-31

17

-1

47

29

ps

0.70

-22

-54

8

-24

38

6

ps

0.60

-34

-83

-4

-53

26

-23

ps

0.50

-60

-125

-30

-95

0

-65

ps

0.40

-100

-188

-70

-158

-40

-128

ps

0.30

-168

-292

-138

-262

-108

-232

ps

0.25

-200

-375

-170

-345

-140

-315

ps

0.20

-325

-500

-295

-470

-265

-440

ps

0.15

-517

-708

-487

-678

-457

-648

ps

0.10

-1000

-1125

-970

-1095

-940

-1065

ps

Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min

and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, If the actual signal is always earlier than the

nominal slew rate line between shaded ‘dc to ac region’, use nominal slew rate for derating value. If the actual signal is later

than the nominal slew rate line anywhere between shaded ‘dc to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to dc level is used for derating value.

Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (dc) max

and the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VIH(dc)min and the first crossing of Vref. If the actual signal is always later than the nominal slew rate line

between shaded ‘dc to Vref region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal

slew rate line anywhere between shaded ‘dc to Vref region’, the slew rate of a tangent line to the actual signal from the dc

level to Vref level is used for derating value.

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V

SS

V

IL(ac)

max

V

IL(dc)

max

V

REF

V

IH(dc)

min

V

DDQ

V

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

V

SS

V

IL(ac)

max

V

IL(dc)

max

V

REF

V

IH(dc)

min

V

DDQ

V

IH(ac)

min

Delta TFS Delta TRH Delta TFH

Delta TRS

tStH

dc to ac

region

dc to ac

region

dc to Vref

region

dc to Vref

region

Setup Slew Rate = VIL(dc)max - VIL(ac)max

Delta TFS falling signal

Setup Slew Rate = VIH(dc)min - VIL(ac)min

Delta TRS rising signal

Hold Slew Rate = VREF - VIL(dc)max

Delta TRH rising signal

Hold Slew Rate = VIH(dc)min - VREF

Delta TFH falling signal

Setup Slew Rate =

tangent line [VIL(dc)max - VIL(ac)max]

Delta TFS

Setup Slew Rate =

tangent line [VIH(dc)min - VIL(ac)min]

Delta TRS

Hold Slew Rate =

tangent line [REF - VIL(dc)max]

Delta TRH

Hold Slew Rate =

tangent line [VIH(dc)min - VREF]

Delta TFH

falling

signal

falling

signal

rising

signal

rising

signal

Specific Note 10 The maximum limit for this parameter is not a device limit. The device will operate with a

greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.

Specific Note 11 MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH

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time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and

tCH).For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock

source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.

Specific Note 12 tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).

tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to

n-channel variation of the output drivers.

Specific Note 13 tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel

variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in

any given cycle.

Specific Note 14 tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.

WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an

integer,round up to the next highest integer. tCK refers to the application clock period.

Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.

tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

Specific Note 15 The clock frequency is allowed to change during self–refresh mode or precharge

power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is

required.

Specific Note 16 ODT turn on time min is when the device leaves high impedance and ODT resistance begins

to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND,

which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge

that registered a first ODT HIGH counting the actual input clock edges.

Specific Note 17 ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time

max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per

speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second

trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual

input clock edges.

Specific Note 18 tHZ and tLZ transitions occur in the same access time as valid data transitions. These

parameters are referenced to a specific voltage level which specifies when the device output is no longer

driving (tHZ), or begins driving (tLZ) .The following figure shows a method to calculate the point when device is

no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the

DQ’s and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and  each treated as single-ended signal.

Specific Note 19 tRPST end point and tRPRE begin point are not referenced to a specific voltage level but

specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). The following figure

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shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving

(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not

critical as long as the calculation is consistent.

Specific Note 20 Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced

from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal,

and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling

signal applied to the device under test. DQS, signals must be monotonic between Vil(dc)max and

Vih(dc)min.

Specific Note 21 Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced

from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal

and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal

applied to the device under test. DQS,signals must be monotonic between Vil(dc)max and Vih(dc)min.

Specific Note 22 Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a

rising signal and VIL(ac) for a falling signal applied to the device under test.

Specific Note 23 Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a

rising signal and VIH(dc) for a falling signal applied to the device under test.

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Specific Note 24 tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.

Specific Note 25 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced

from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the

start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the

single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device

under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

Specific Note 26 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced

from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end

of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended

data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test.

The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.

Specific Note 27 tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock

edges.CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration.

Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK

+ tIH.

Specific Note 28 If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid

data before a valid READ can be executed.

Specific Note 29 These parameters are measured from a command/address signal (, , , ,

,ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/) crossing. The spec values

are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are

relative to the clock signal crossing that latches the command/address. That is, these parameters should be

met whether clock jitter is present or not.

Specific Note 30 These parameters are measured from a data strobe signal ((L/U/R)DQS/) crossing to its

respective clock signal (CK/) crossing. The spec values are not affected by the amount of clock jitter applied

(i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should

be met whether clock jitter is present or not.

Specific Note 31 These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.)

transition edge to its respective data strobe signal ((L/U/R)DQS/) crossing.

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Specific Note 32 For these parameters, the DDR2 SDRAM device is characterized and verified to support

tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are

satisfied.

For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter

specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP =

RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm

and active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter.

Specific Note 33 tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is

the value programmed in the mode register set.

Specific Note 34 New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.

Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.

Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.

ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at

Tm+2,even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.

Specific Note 35 Input clock jitter spec parameter. These parameters and the ones in the table below are

referred to as 'input clock jitter spec parameters' and these parameters apply. The jitter specified is a random

jitter meeting a Gaussian distribution.

Input clock jitter spec parameter apply to DDR2-667, DDR2-800 and DDR2-1066

Parameter

Symbol

DDR2-667

DDR2-800

DDR2-1066

Units

min

max

min

max

min

max

Clock period jitter

tJIT(per)

-125

125

-100

100

-90

90

ps

Clock period jitter during DLL

locking period

tJIT(per,lck)

-100

100

-80

80

-80

80

ps

Cycle to cycle clock period jitter

tJIT(cc)

-250

250

-200

200

-180

180

ps

Cycle to cycle clock period jitter

during DLL locking period

tJIT(cc,lck)

-200

200

-160

160

-160

160

ps

Cumulative error across 2 cycles

tERR(2per)

-175

175

-150

150

-132

132

ps

Cumulative error across 3 cycles

tERR(3per)

-225

225

-175

175

-157

157

ps

Cumulative error across 4 cycles

tERR(4per)

-250

250

-200

200

-175

175

ps

Cumulative error across 5 cycles

tERR(5per)

-250

250

-200

200

-188

188

ps

Cumulative error across n

cycles,n = 6 ... 10, inclusive

tERR(6-10per)

-350

350

-300

300

-250

250

ps

Cumulative error across n

cycles,n = 11 ... 50, inclusive

tERR(11-50per)

-450

450

-450

450

-425

425

ps

Duty cycle jitter

tJIT(duty)

-125

125

-100

100

-75

75

ps

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Definitions:

- tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.

- tCH(avg) and tCL(avg)

tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH

pulses.

tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.

- tJIT(duty)

tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of

any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).

tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}

where,

tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}

tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}

- tJIT(per), tJIT(per,lck)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).

tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}

tJIT(per) defines the single period jitter when the DLL is already locked.

tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.

- tJIT(cc), tJIT(cc,lck)

tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:

tJIT(cc) = Max of |tCKi+1 – tCKi|

tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

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tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.

- tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)

tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).

Specific Note 36 These parameters are specified per their average values, however it is understood that the

following relationship between the average timing and the absolute instantaneous timing holds at all times.

(min and max of SPEC values are to be used for calculations in the table below.)

Parameter

Symbol

min

max

Units

Absolute clock period

tCK(abs)

tCK(avg),min + tJIT(per),min

tCK(avg),max + tJIT(per),max

ps

Absolute clock HIGH pulse width

tCH(abs)

tCH(avg),min x tCK(avg),min +tJIT(duty),min

tCH(avg),max x tCK(avg),max +

tJIT(duty),max

ps

Absolute clock LOW pulse width

tCL(abs)

tCL(avg),min x tCK(avg),min +

tJIT(duty),min

tCL(avg),max x tCK(avg),max +

tJIT(duty),max

ps

Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps

Specific Note 37 tHP is the minimum of the absolute half period of the actual input clock. tHP is an input

parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM

output timing tQH. The value to be used for tQH calculation is determined by the following equation;

tHP = Min ( tCH(abs), tCL(abs) ),

where,

tCH(abs) is the minimum of the actual instantaneous clock HIGH time;

tCL(abs) is the minimum of the actual instantaneous clock LOW time;

Specific Note 38 tQHS accounts for:

1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the

input is transferred to the output; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and

pchannel to n-channel variation of the output drivers

Specific Note 39 tQH = tHP – tQHS, where:

tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value

under the max column.

{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye

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will be.}

Examples:

1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps

minimum.

2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps

minimum.

Specific Note 40 When the device is operated with input clock jitter, this parameter needs to be derated by the

actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-

10per),max = + 293 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = -

693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 ps + 272 ps = + 672 ps.

Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = - 1193 ps and

tLZ(DQ),max(derated)= 450 ps + 272 ps = + 722 ps. (Caution on the min/max usage!)

Specific Note 41 When the device is operated with input clock jitter, this parameter needs to be derated by the

actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = +

93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and

tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. (Caution on the

min/max usage!)

Specific Note 42 When the device is operated with input clock jitter, this parameter needs to be derated by the

actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max =

+ 93ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and

tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. (Caution on the

min/max usage!)

Specific Note 43 When the device is operated with input clock jitter, this parameter needs to be derated by { -

tJIT(duty),max - tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock.

(output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6-

10per),max = + 293 ps, tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) =

tAOF,min+ { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and

tAOF,max(derated) =tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = +

1428 ps. (Caution on the min/max usage!)

Specific Note 44 For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg),

average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be

derated

by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For

example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting

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0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be

derated by adding 0.02 x tCK(avg) to it. Therefore, we have;

tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg)

tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg)

or

tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg))

tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg))

where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at

the DRAM input balls.

Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and

tERR(6-10per).

However tAC values used in the equations shown above are from the timing parameter table and are not

derated.

Thus the final derated values for tAOF are;

tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max }

tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }

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Overshoot and Undershoot Specification

AC Overshoot / Undershoot Specification for Address and Control Pins

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Maximum peak amplitude allowed for overshoot area

0.5

V

Maximum peak amplitude allowed for undershoot area

0.5

V

Maximum overshoot area above VDD

0.8

0.66

V-ns

Maximum undershoot area below VSS

0.8

0.66

V-ns

VDD

VSS

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins

Parameter

-3C/-3CI

-AC/-ACI

-BE

-BD

Units

Maximum peak amplitude allowed for overshoot area

0.5

V

Maximum peak amplitude allowed for undershoot area

0.5

V

Maximum overshoot area above VDD

0.23

V.ns

Maximum undershoot area below VSS

0.23

V.ns

VDDQ

VSSQ

Overshoot Area

Undershoot Area

Maximum Amplitude

Time (ns)

Volts (V)

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Package Dimensions

(x4/x8; 60 balls; BGA Package)

Note : All dimensions are typical unless otherwise stated

10.00 +/- 0.10

0. 40 Max.

0.25 Min.

60 Ball BGA

0.80

8.00

Dia.

Min 0.40

Max

0.50

Unit : Millimeters

Min 0.10 Min 0.10

0.80 6.40

8.00+/-0.10

Pin A1 Index

1.20 Max.

0.10Max.

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Package Dimensions

(X16; 84 balls; BGA Package)

Note : All dimensions are typical unless otherwise stated

.

12.50 +/- 0.10

0.40 Max.

0. 25 Min.

1. 20 Max.

84 Ball BGA

0.80

11.20

Dia.

Min 0.40

Max

0.50

Unit : Millimeters

Min 0.10 Min 0.10

0.80 6.40

8.00+/-0.10 Pin A1 Index

0. 10Max.

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Revision Log

Rev

Date

Modification

0.1

06/2010

Preliminary Release

0.2

07/2010

Revised Block Diagram Description

0.3

09/2010

Revised Description, Electrical Characteristics, tFAW, the feature of –BE, and

ordering information

0.4

09/2010

Revised tRRD

0.5

10/2010

Updated CAS Latency Frequency Table

0.6

11/2010

Revised Refresh Parameter Component Type

1.0

12/2010

Official Release

1.1

02/2011

Revised 60 balls BGA Package Pin Configuration and –BD tCK parameters

1.2

04/2011

Removed x8/1066 Part Number from Ordering Information

1.3

05/2011

Revised Note Description of Operating Temperature Range and Table of Bank

Selection for Prechange by Address Bit

1.4

08/2011

Revised the number bit of address bus

1.5

12/2011

Added TC and TOPER relation into the description of Operating Temperature

1.6

12/2011

Revised Self Refresh Exit in the Command Truth Table

1.7

07/2012

Added General Note and Specific Note from the page 75 to the page 87

1.8

02/2013

Modified tRAS.