DS90LV047A
DS90LV047A 3V LVDS Quad CMOS Differential Line Driver
Literature Number: SNLS044B
DS90LV047A
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV047A is a quad CMOS flow-through differential
line driver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV047A accepts low voltage TTL/CMOS input lev-
els and translates them to low voltage (350 mV) differential
output signals. In addition, the driver supports a TRI-STATE®
function that may be used to disable the output stage, dis-
abling the load current, and thus dropping the device to an
ultra low idle power state of 13 mW typical. The
DS90LV047A has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
drivers. The DS90LV047A and companion line receiver
(DS90LV048A) provide a new alternative to high power
psuedo-ECL devices for high speed point-to-point interface
applications.
Features
n>400 Mbps (200 MHz) switching rates
nFlow-through pinout simplifies PCB layout
n300 ps typical differential skew
n400 ps maximum differential skew
n1.7 ns maximum propagation delay
n3.3V power supply design
n±350 mV differential signaling
nLow power dissipation (13mW at 3.3V static)
nInteroperable with existing 5V LVDS receivers
nHigh impedance on LVDS outputs on power down
nConforms to TIA/EIA-644 LVDS Standard
nIndustrial operating temperature range (−40˚C to +85˚C)
nAvailable in surface mount (SOIC) and low profile
TSSOP package
Connection Diagram
Dual-In-Line
10088701
Order Number DS90LV047ATM, DS90LV047ATMTC
See NS Package Number M16A, MTC16
Truth Table
ENABLES INPUT OUTPUTS
EN EN*D
IN
D
OUT+
D
OUT−
H L or Open L L H
HHL
All other combinations of
ENABLE inputs XZZ
Functional Diagram
10088702
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
January 2003
DS90LV047A 3V LVDS Quad CMOS Differential Line Driver
© 2003 National Semiconductor Corporation DS100887 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
Input Voltage (D
IN
) −0.3V to (V
CC
+ 0.3V)
Enable Input Voltage (EN,
EN*) −0.3V to (V
CC
+ 0.3V)
Output Voltage (D
OUT+
,D
OUT−
) −0.3V to +3.9V
Short Circuit Duration
(D
OUT+
,D
OUT−
) Continuous
Maximum Package Power Dissipation @+25˚C
M Package 1088 mW
MTC Package 866 mW
Derate M Package 8.5 mW/˚C above +25˚C
Derate MTC Package 6.9 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range
Soldering (4 sec.) +260˚C
Maximum Junction
Temperature +150˚C
ESD Rating (Note 10)
(HBM, 1.5 kΩ, 100 pF) ≥10 kV
(EIAJ, 0 Ω, 200 pF) ≥1200 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +3.0 +3.3 +3.6 V
Operating Free Air
Temperature (T
A
) −40 +25 +85 ˚C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3, 4)
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD1
Differential Output Voltage R
L
= 100Ω(Figure 1)D
OUT−
D
OUT+
250 310 450 mV
∆V
OD1
Change in Magnitude of V
OD1
for
Complementary Output States
1 35 |mV|
V
OS
Offset Voltage 1.125 1.17 1.375 V
∆V
OS
Change in Magnitude of V
OS
for
Complementary Output States
1 25 |mV|
V
OH
Output High Voltage 1.33 1.6 V
V
OL
Output Low Voltage 0.90 1.02 V
V
IH
Input High Voltage D
IN
,
EN,
EN*
2.0 V
CC
V
V
IL
Input Low Voltage GND 0.8 V
I
IH
Input High Current V
IN
=V
CC
or 2.5V −10 2 +10 µA
I
IL
Input Low Current V
IN
= GND or 0.4V −10 −2 +10 µA
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 −0.8 V
I
OS
Output Short Circuit Current
(Note 11)
ENABLED,
D
IN
=V
CC
,D
OUT+
=0Vor
D
IN
= GND, D
OUT−
=0V
D
OUT−
D
OUT+
−4.2 −9.0 mA
I
OSD
Differential Output Short Circuit
Current (Note 11)
ENABLED, V
OD
= 0V −4.2 −9.0 mA
I
OFF
Power-off Leakage V
OUT
= 0V or 3.6V, V
CC
=0V
or Open
−20 ±1 +20 µA
I
OZ
Output TRI-STATE Current EN = 0.8V and EN* = 2.0V
V
OUT
=0VorV
CC
−10 ±1 +10 µA
I
CC
No Load Supply current Drivers
Enabled
D
IN
=V
CC
or GND V
CC
4.0 8.0 mA
I
CCL
Loaded Supply Current Drivers
Enabled
R
L
= 100ΩAll Channels, D
IN
=
V
CC
or GND (all inputs)
20 30 mA
I
CCZ
No Load Supply Current Drivers
Disabled
D
IN
=V
CC
or GND, EN = GND,
EN*=V
CC
2.2 6.0 mA
DS90LV047A
www.national.com 2
Switching Characteristics
V
CC
= +3.3V ±10%, T
A
= −40˚C to +85˚C (Notes 3, 9, 12)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω,C
L
=15pF
(Figure 2 and Figure 3)
0.5 0.9 1.7 ns
t
PLHD
Differential Propagation Delay Low to High 0.5 1.2 1.7 ns
t
SKD1
Differential Pulse Skew |t
PHLD
−t
PLHD
|
(Note 5) 0 0.3 0.4 ns
t
SKD2
Channel-to-Channel Skew (Note 6) 0 0.4 0.5 ns
t
SKD3
Differential Part to Part Skew (Note 7) 0 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 8) 0 1.2 ns
t
TLH
Rise Time 0.5 1.5 ns
t
THL
Fall Time 0.5 1.5 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω,C
L
=15pF
(Figure 4 and Figure 5)
25ns
t
PLZ
Disable Time Low to Z 2 5 ns
t
PZH
Enable Time Z to High 3 7 ns
t
PZL
Enable Time Z to Low 3 7 ns
f
MAX
Maximum Operating Frequency (Note 14) 200 250 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and
∆VOD1.
Note 3: All typicals are given for: VCC = +3.3V, TA= +25˚C.
Note 4: The DS90LV047A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical
range is (90Ωto 110Ω).
Note 5: tSKD1 |tPHLD −t
PLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
Note 6: tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device.
Note 7: tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5˚C of each other within the operating temperature range.
Note 8: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 9: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO=50Ω,t
r≤1 ns, and tf≤1 ns.
Note 10: ESD Ratings:
HBM (1.5 kΩ, 100 pF) ≥10 kV
EIAJ (0 Ω, 200 pF) ≥1200 V
Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 12: CLincludes probe and jig capacitance.
Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 14: fMAX generator input conditions: tr=t
f<1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD >250mV, all channels
switching.
Parameter Measurement Information
10088703
FIGURE 1. Driver V
OD
and V
OS
Test Circuit
DS90LV047A
www.national.com3
Parameter Measurement Information (Continued)
10088704
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
10088705
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
10088706
FIGURE 4. Driver TRI-STATE Delay Test Circuit
DS90LV047A
www.national.com 4
Parameter Measurement Information (Continued)
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 6. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic
differential impedance of the media is in the range of 100Ω.
A termination resistor of 100Ω(selected to match the media),
and is located as close to the receiver input pins as possible.
The termination resistor converts the driver output current
(current mode) into a voltage that is detected by the receiver.
Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s),
cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90LV047A differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to
produce a logic state and in the other direction to produce
the other logic state. The output current is typically 3.1 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode driver requires(as discussed above) that a resistive
termination be employed to terminate the signal and to com-
plete the loop as shown in Figure 6. AC or unterminated
configurations are not allowed. The 3.1 mA loop current will
develop a differential voltage of 310mV across the 100Ω
termination resistor which the receiver detects with a 250mV
minimum differential noise margin, (driven signal minus re-
ceiver threshold (250mV – 100mV = 150mV)). The signal is
centered around +1.2V (Driver Offset, V
OS
) with respect to
ground as shown in Figure 7. Note that the steady-state
voltage (V
SS
) peak-to-peak swing is twice the differential
voltage (V
OD
) and is typically 620mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
10088707
FIGURE 5. Driver TRI-STATE Delay Waveform
10088708
FIGURE 6. Point-to-Point Application
DS90LV047A
www.national.com5
Typical Application (Continued)
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the
current mode driver switches a fixed current between its
output without any substantial overlap current. This is similar
to some ECL and PECL devices, but without the heavy static
I
CC
requirements of the ECL/PECL designs. LVDS requires
>80% less current than similar PECL devices. AC specifi-
cations for the driver are a tenfold improvement over other
existing RS-422 drivers.
The TRI-STATE function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
The DS90LV047A has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the
device easily allows for matching electrical lengths of the
differential pair trace lines between the driver and the re-
ceiver as well as allowing the trace lines to be close together
to couple noise as common-mode. Noise isolation is
achieved with the LVDS signals on one side of the device
and the TTL signals on the other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be <10mm long). This will help eliminate
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will re-
sult. (Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber or vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
TERMINATION
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90Ωand 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor ter-
mination. Typically, connecting a single resistor across the
pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be <10mm
(12mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (>100kΩ), low capacitance
(<2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise
reduction and signal quality. Balanced cables tend to gener-
ate less EMI due to field canceling effects and also tend to
pick up electromagnetic radiation a common-mode (not dif-
ferential mode) noise which is rejected by the receiver.
For cable distances <0.5M, most cables can be made to
work effectively. For distances 0.5M ≤d≤10M, CAT 3
(category 3) twisted pair cable works well, is readily available
and relatively inexpensive.
LVDS FAIL-SAFE
This section addresses the common concern of fail-safe
biasing of LVDS interconnects, specifically looking at the
DS90LV047A driver outputs and the DS90LV048A receiver
inputs.
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
DS90LV047A
www.national.com 6
Typical Application (Continued)
1. Open Input Pins. The DS90LV048A is a quad receiver
device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2. Terminated Input. If the DS90LV047A driver is discon-
nected (cable unplugged), or if the DS90LV047A driver
is in a TRI-STATE or power-off condition, the receiver
output will again be in a HIGH state, even with the end of
cable 100Ωtermination resistor across the input pins.
The unplugged cable can become a floating antenna
which can pick up noise. If the cable picks up more than
10mV of differential noise, the receiver may see the
noise as a valid signal and switch. To insure that any
noise is seen as common-mode and not differential, a
balanced interconnect should be used. Twisted pair
cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩto 15kΩrange to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
Pin Descriptions
Pin No. Name Description
2, 3, 6, 7 D
IN
Driver input pin, TTL/CMOS
compatible
10, 11, 14,
15
D
OUT+
Non-inverting driver output pin,
LVDS levels
9, 12, 13,
16
D
OUT−
Inverting driver output pin, LVDS
levels
1 EN Driver enable pin: When EN is
low, the driver is disabled. When
EN is high and EN*is low or
open, the driver is enabled. If both
EN and EN*are open circuit, then
the driver is disabled.
Pin No. Name Description
8EN
*Driver enable pin: When EN*is
high, the driver is disabled. When
EN*is low or open and EN is
high, the driver is enabled. If both
EN and EN*are open circuit, then
the driver is disabled.
4V
CC
Power supply pin, +3.3V ±0.3V
5 GND Ground pin
Ordering Information
Operating Package Type/ Order Number
Temperature Number
−40˚C to +85˚C SOP/M16A DS90LV047ATM
−40˚C to +85˚C TSSOP/MTC16 DS90LV047ATMTC
10088709
FIGURE 7. Driver Output Levels
DS90LV047A
www.national.com7
Typical Performance Curves
Output High Voltage vs
Power Supply Voltage
Output Low Voltage vs
Power Supply Voltage
10088714 10088715
Output Short Circuit Current vs
Power Supply Voltage
Output TRI-STATE Current vs
Power Supply Voltage
10088716 10088717
Differential Output Voltage
vs Power Supply Voltage
Differential Output Voltage
vs Load Resistor
10088718 10088719
DS90LV047A
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Typical Performance Curves (Continued)
Offset Voltage vs
Power Suppy Voltage
Power Supply Current
vs Frequency
10088720 10088721
Power Supply Current vs
Power Supply Voltage
Power Supply Current vs
Ambient Temperature
10088722 10088723
Differential Propagation Delay vs
Power Supply Voltage
Differential Propagation Delay vs
Ambient Temperature
10088724 10088725
DS90LV047A
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Typical Performance Curves (Continued)
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
10088726 10088727
Transition Time vs
Power Supply Voltage
Transition Time vs
Ambient Temperature
10088728 10088729
DS90LV047A
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Typical Performance Curves
(Continued)
Data Rate vs
Cable Length
10088730
DATA RATE VS CABLE LENGTH GRAPH TEST PROCEDURE
A pseudo-random bit sequence (PRBS) of 2
9
−1 bits was
programmed into a function generator (Tektronix HFS9009)
and connected to the driver inputs via 50Ωcables and SMB
connectors. An oscilloscope (Tektronix 11801B) was used to
probe the resulting eye pattern, measured differentially at the
input to the receiver. A 100Ωresistor was used to terminate
the pair at the far end of the cable. The measurements were
taken at the far end of the cable, at the receiver"s input, and
used for the jitter analysis for this graph. The frequency of
the input signal was increased until the measured jitter (t
tcs
)
equaled 20% with respect to the unit interval (t
tui
) for the
particular cable length under test. Twenty percent jitter is a
reasonable place to start with many system designs. The
data used was NRZ. Jitter was measured at the 0V differen-
tial voltage of the differential eye pattern. The cables used
were LG UTP 4 pair 24 gauge CAT 5 cables. The
DS90LV047A and DS90LV048A were tested using the new
LVDS Flow-Evaluation Board LVDS47/48PCB which is avail-
able in the LVDS47/48EVK evaluation kit.
The curve shows very good typical performance that can be
used as a design guideline for data rate vs cable length.
Increasing the jitter percentage increases the curve respec-
tively, allowing the device to transmit faster over longer cable
lengths. This relaxes the jitter tolerance of the system allow-
ing more jitter into the system, which could reduce the reli-
ability and efficiency of the system. Alternatively, decreasing
the jitter percentage will have the opposite effect on the
system. The area under the curve is considered the safe
operating area based on the above signal quality criteria. For
more information on eye pattern testing, please see National
Application Note AN-808.
DS90LV047A
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Physical Dimensions inches (millimeters)
unless otherwise noted
16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV047ATM
NS Package Number M16A
DS90LV047A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90LV047ATMTC
NS Package Number MTC16
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DS90LV047A 3V LVDS Quad CMOS Differential Line Driver
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