December 2004 Document Control #ML0022 rev 1.0 1
STK14CA8
128K x 8 Au t oStoreTM nvSRAM
QuantumTrapTM CM OS
Nonvolatile Static RAM
FEATURES
• 25ns, 35ns and 45n s Access Times
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin
or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Up
• Unlimited READ, WRITE and RECALL Cycles
• 5mA Typical ICC at 200ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap™
• 100-Year Data Retention to QuantumTrap™
• Single 3V +20%, -10% Op eratio n
• Commercial and Industrial Temperatures
• SOIC, SSOP and DIP Packages
• RoHS Compliance
DESCRIPTION
The Simtek STK14CA8 is a fast static RAM with a
nonvolatile element in each memory cell. The
embedded nonvolatile elements incorporate
Simtek’s QuantumTrapTM technology producing the
world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles,
while independent, nonvolatile data resides in the
highly reliable QuantumTrapTM cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at
power down. On power up, data is restored to the
SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations
are also available under software control.
BLOCK DIAGRAM
ROW DECODER INPUT BUFFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT A15 – A0
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 A1 A2 A3 A4 A10 A11
VCC VCAP
Figure 1. Block Diagram
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 2
V
CAP
DQ
0
DQ
1
DQ
2
G
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
V
CC
A
15
A
13
A
8
A
11
V
SS
DQ
6
A
10
DQ
7
DQ
5
DQ
4
DQ
3
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
W
HSB
E
32 Pin
SOIC or PDIP
48 Pin SSOP
V
CAP
V
SS
A
16
A
14
A
12
A
7
A
6
A
5
A
4
V
CC
A
15
A
13
A
8
DQ
0
V
SS
DQ
6
A
9
1
2
3
4
5
6
7
8
9
1
0
11
12
13
14
15
16 33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
W
HSB
DQ
1
DQ
2
G
A
3
A
2
A
1
A
0
DQ
5
A
10
DQ
7
DQ
4
DQ
3
V
CC
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
E
A
11
PACKAGES
PIN DESCRIPTIONS
Pin Name I/O Description
A16 – A0 Input
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
DQ7 –DQ0 I/O
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
E Input Chip Enable: The active low E input selects the device.
W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by
the falling edge of E .
G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G
high causes the DQ pins to tri-state.
VCC Power Supply
Power 3.0V +20%, -10%
HSB I/O
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
VCAP Power Supply
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
elements.
VSS Power Supply
Ground
(Blank) No Connect
Unlabeled pins have no internal connection.
SSOP
Relative PCB area usage.
See website for detailed
package size specifications.
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 3
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Commercial Industrial
Symbol Parameter MIN MAX MIN MAX
Units Notes
tAVAV = 25ns
tAVAV = 35ns
ICC1 Average VCC Current
65
55
50
70
60
55
mA
mA
mA tAVAV = 45ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
ICC2 Average VCC Current during STORE
3 3 mA
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current at tAVAV = 200ns W ≥ (VCC – 0.2V)
ICC3 3V, 25°C, Typical
5 5 mA
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
ICC4 Average VCAP Current during
AutoStore™ Cycle 3 3 mA
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
VCC Standby Current E ≥ (VCC – 0.2V)
ISB (Standby, Stable CMOS Input Levels)
2 2 mA
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
VCC = max
IILK Input Leakage Current
±1 ±1 µA VIN = VSS to VCC
VCC = max
IOLK Off-State Output Leakage Current
±1 ±1 µA VIN = VSS to VCC, E or G ≥ VIH
VIH Input Logic “1” Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V All Inputs
VIL Input Logic “0” Voltage VSS – 0.5 0.8 VSS – 0.5 0.8 V All Inputs
VOH Output Logic “1” Voltage 2.4 2.4 V IOUT = –2mA
VOL Output Logic “0” Voltage 0.4 0.4 V IOUT = 4mA
TA Operating Temperature 0 70 –40 85
oC
VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10%
VCAP Storage Capacitor 17 57 17 57 µF Between Vcap pin and Vss, 5V rated.
AB SOLUTE MAXIMUM RATINGS a
Power Supply Voltage
Voltage on Input Relative to VSS
Voltage on Outputs
Temperature under Bias
Junction Temperature
Storage Temperature
Power Dissipation
DC Output Current (1 output at a time, 1s duration)
Notes
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions ab o ve th os e i ndi c ate d in th e op er ati o nal sect io ns of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
-0.5V to +4.1V
-0.5V to (VCC + 0.5V)
-0.5V to (VCC + 0.5V)
–55°C to 125°C
–55°C to 140°C
–65°C to 150°C
1W
15mA
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 4
AC TEST CONDITIONS
CAPACITANCEb (TA = 25°C, f = 1.0MHz)
SYMBOL PARAMETER MAX UNITS CONDITIONS
CIN Input Capacitance 7 pF ∆V = 0 to 3V
COUT Output Capacitance 7 pF ∆V = 0 to 3V
Notes
b: These parameters are guaranteed but not tested
3.0V
30 pF
INCLUDING
SCOPE AND
FIXTURE
577 Ohms
789 Ohms
OUTPUT
3.0V
30 pF
INCLUDING
SCOPE AND
FIXTURE
577 Ohms
789 Ohms
OUTPUT
Figure 3. AC Output Loading,
for tristate specs (
tHZ, tLZ, tWLQZ, tWHQZ,
tGLQX, tGHQZ )
Figure 2. AC Output Loading
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3V
≤ 5ns
1.5V
See Figure 2 and Figure 3
5 pF
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 5
SRAM READ CYCLES #1 & #2
SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45
NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX MIN MAX
UNITS
1 t
ELQV t
ACS Chip Enable Access Time 25 35 45 ns
2 tAVAV
c t
AVAV
c t
RC Read Cycle Time 25 35 45 ns
3 tAVQV
d t
AA Address Access Time 25 35 45 ns
4 t
GLQV t
OE Output Enable to Data Valid 12 15 20 ns
5 tAXQX
d t
OH Output Hold after Address Change 3 3 3 ns
6 t
ELQX t
LZ Chip Enable to Output Active 3 3 3 ns
7 t
EHQZ
e t
HZ Chip Disable to Output Inactive 10 13 15 ns
8 t
GLQX t
OLZ Output Enable to Output Active 0 0 0 ns
9 t
GHQZ
e t
OHZ Output Disable to Output Inactive 10 13 15 ns
10
tELICC
b tPA Chip Enable to Power Active 0 0 0 ns
11 t
EHICC
b t
PS Chip Disable to Power Standby 25 35 45 ns
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
SRAM READ CYCLE #2: E Controlledc,f
DQ (DATA OUT)
A
DDRESS
3
tAVQV
5
tAXQX
DATA VALID
2
tAVAV
2
tAVAV
DATA VALID
ADDRESS
DQ
(
DATA OUT
)
ICC STANDBY
ACTIVE
1
tELQV
6
tELQ
X
4
tGLQV
8
tGLQ
X
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ
E
G
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 6
SRAM WRITE CYCLES #1 & #2
Notes
g: If W is low when E goes low, the outputs remain in the high-impedance state.
h: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
SRAM WRITE CYCLE #2: E Controlledh,f
SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45 UNITS
NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX MIN MAX
12 tAVAV t
AVAV t
WC Write Cycle Time 25 35 45 ns
13 tWLWH t
WLEH t
WP Write Pulse Width 20 25 30 ns
14 tELWH t
ELEH t
CW Chip Enable to End of Write 20 25 30 ns
15 tDVWH t
DVEH t
DW Data Set-up to End of Write 10 12 15 ns
16 tWHDX t
EHDX t
DH Data Hold after End of Write 0 0 0 ns
17 tAVWH t
AVEH t
AW Address Set-up to End of Write 20 25 30 ns
18 tAVWL t
AVEL t
AS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX t
EHAX t
WR Address Hold after End of Write 0 0 0 ns
20 tWLQZe,g t
WZ Write Enable to Output Disable 10 13 15 ns
21 tWHQX t
OW Output Active after End of Write 3 3 3 ns
ADDRESS
DATA OUT
DATA IN
W
E
ADDRESS
HIGH IMPEDANCE
DATA VALID
PREVIOUS DATA
14
tELWH
19
tWHAX
17
tAVWH
18
tAVWL 13
tWLWH
15
tDVWH
16
tWHD
X
20
tWLQZ 21
tWHQX
12
t
A
VA
V
DATA OUT
DATA IN
W
E
HIGH IMPEDANCE
DATA VALID
12
tAVAV
14
tELEH
18
tAVEL
19
tEHAX
17
tAVEH 13
tWLEH
15
tDVEH
16
tEHDX
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 7
MODE SELECTION
E W G A15 - A0 MODE I/O POWER NOTES
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active i, j, k
L H L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active i, j, k
L H L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
ICC2
i, j, k
L H L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active i, j, k
Notes
i: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
j: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
k: I/O state depends on the state of G . The I/O table shown assumes G low.
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 8
AutoStore™ /POWER-UP RECALL
SYMBOLS PARAMETER STK14CA8
NO. Standard Alternate MIN MAX
UNITS NOTES
22 tHRECALL Power-up RECALL Duration 20 ms
l
23 tSTORE t
HLHZ STORE Cycle Duration 12.5 ms
m
24 VSWITCH Low Voltage Trigger Level 2.55 2.65 V
25 tVCCRISE VCC Rise Time 150 µs
Notes
l: tHRECALL starts from the time VCC rises above VSWITCH
m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStore™/POWER-UP RECALL
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.
POWER-UP RECALL
VCC
23
tSTORE
22
tHRECALL
24
VSWITCH
AutoStore
TM
POWER DOWN
AutoStoreTM
BROWN OUT
AutoStoreTM
POWER-UP
RECALL
Read & Write Inhibited
25
tVCCRISE
23
tSTORE
22
tHRECALL
POWER-UP
RECALL
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 9
SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o
SYMBOLS STK14CA8-25 STK14CA8-35 STK14CA8-45
NO. E
cont
G
cont Alt. PARAMETER MIN MAX MIN MAX MIN MAX
UNITS NOTES
26 tAVAV t
AVAV t
RC STORE/RECALL Initiation Cycle Time 25 35 45 ns o
27 tAVEL t
AVGL t
AS Address Set-up Time 0 0 0 ns
28 tELEH t
GLGH t
CW Clock Pulse Width 20 25 30 ns
29 tELAX t
GLAX Address Hold Time 20 20 20 ns
30 tRECALL t
RECALL RECALL Duration 40 40 40 µs
Notes
n: The software sequence is clocked with E controlled READs or G controlled READs.
o: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
SOFTWARE STORE/RECALL CYCLE: G Controlledo
DQ (DATA)
G
E
26
t
A
VA
V
DATA VALID
ADDRESS ADDRESS #1
HIGH IMPEDENCE
27
tAVEL
29
tELAX
28
tELEH
30
tRECALL
26
t
A
VA
V
ADDRESS #6
23
tSTORE
DATA VALID
/
ADDRESS
E
G
DQ (DATA)
26
tAVAV
DATA VALID
ADDRESS #1
HIGH IMPEDENCE
29
tGLAX
30
tRECALL
26
tAVAV
ADDRESS #6
23
tSTORE
27
t
A
VGL
28
tGLGH
DATA VALID
/
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 10
HARDWARE STORE CYCLE
SYMBOLS STK14CA8
NO. Standard Alternate PARAMETER MIN MAX UNITS NOTES
31 tDELAY t
HLQZ Time Allowed to Complete SRAM Cycle 1 µs p
32 tHLHX Hardware STORE Pulse Width 15 ns
33 tHLBL Hardware STORE Low to STORE Busy 300 ns
Notes
p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
HSB (OUT)
HSB (IN)
DQ (DATA OUT)
HIGH IMPEDENCE
31
tDELA
Y
DATA VALID
32
tHLHX
33
tHLBL
HIGH IMPEDENCE
DATA VALID
23
t
S
T
O
RE
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 11
nvSRAM
The STK14CA8 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile QuantumTrap™ cell. The SRAM memory
cell operates as a standard fast static RAM. Data in
the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell
to SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK14CA8 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations from the
nonvolatile cells and up to 1 million STORE
operations.
SRAM READ
The STK14CA8 performs a READ cycle whenever
E and G are low while W and HSB are high.
The address specified on pins A16-0 determines which
of the 131,072 data bytes will be accessed. When the
READ is initiated by an address transition, the
outputs will be valid after a delay of tAVQV (READ
cycle #1). If the READ is initiated by E or G , the
outputs will be valid at tELQV or at tGLQV, whichever is
later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
tAVQV access time without the need for transitions on
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
VCC
VCAP
10k Ohm
0.1µF
VCC
VCAP
W
SRAM WRITE
A WRITE cycle is performed whenever E and W
are low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK14CA8 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore™, on
device power down.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK14CA8.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
Figure 4 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer
to the DC CHARACTERISTICS table for the size of
Vcap. The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect
an AutoStore™ cycle is in progress.
DEVICE OPERATION
Figure 4: AutoStoreTM Mode
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 12
HARDWARE STORE (HSB ) OPERATION
The STK14CA8 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK14CA8 will
conditionally initiate a STORE operation after tDELAY.
An actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14CA8 will
continue SRAM operations for tDELAY. During tDELAY,
multiple SRAM READ operations may take place. If
a WRITE is in progress when HSB is pulled low it
will be allowed a time, tDELAY, to complete. However,
any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
During any STORE operation, regardless of how it
was initiated, the STK14CA8 will continue to drive
the HSB pin low, releasing it only when the STORE
is complete. Upon completion of the STORE
operation the STK14CA8 will remain disabled until
the HSB pin returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will
automatically be initiated and will take tHRECALL to
complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK14CA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations in exact order. During
the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with E
controlled READs or G controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the
following sequence of E controlled READ operations
must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 13
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the tRECALL cycle time the SRAM will once
again be ready for READ and WRITE operations.
The RECALL operation in no way alters the data in
the nonvolatile elements.
PREVENTING AUTOSTORETM
The AutoStore™ function can be disabled by initiat-
ing an AutoStore Disable sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence
of E controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore™ can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of read
operations is performed in a manner similar to the
software RECALL initiation. To initiate the AutoStore
Enable sequence, the following sequence of E
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore™ function is disabled or re-enabled
a manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore™ enabled.
DATA PROTECTION
The STK14CA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
voltage condition is detected when VCC < VSWITCH .
If the STK14CA8 is in a WRITE mode (both E and
W low ) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
NOISE CONSIDERATIONS
The STK14CA8 is a high-speed memory and so must
have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and VSS,
using leads and traces that are as short as possible.
As with all high-speed CMOS ICs, careful routing of
power, ground and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14CA8 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 5 shows the
relationship between ICC and READ/WRITE cycle
time. Worst-case current consumption is shown for
commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK14CA8 depends on
the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. I/O loading.
Average Active Current (mA)
100 150 200 300
0
10
20
30
40
50
Writes
Reads
Cycle Time (ns)
50
Figure 5 C urrent vs. Cycle time
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 14
ORDERING INFORMATION
STK14CA8 – R F 45 I
Temperature Range
Blank = Commercial (0 to 70ºC)
I = Industrial (-40 to 85ºC)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85% Sn / 15% Pb
F = 100% Sn (Matte Tin) RoHS Compliant
Package
N = Plastic 32-pin 300 mil SOIC (50 mil pitch)
R = Plastic 48-pin 300 mil SSOP (25 mil pitch)
W = Plastic 32-pin 600 mil DIP (100 mil pitch)
STK14CA8
December 2004 Document Control #ML0022 rev 1.0 15
Document Revision History
Revision Date Summary
0.0 January 2003
Publish new datasheet
0.1 May 2003
Add 48 pin SSOP, Modify AutoStore drawing (Figure 2), Update Mode
Selection Table and Absolute Maximum Ratings, Added G control software
store
0.2 September
2003
Added lead-free lead finish
1.0 December
2004
Parameter Old Value New Value Notes
Vcap Min 10µF 17 µF
tVCCRISE NA 150 µs New Spec
ICC1 Max Com. 35 mA 50 mA @ 45ns access
ICC1 Max Com. 40 mA 55 mA @ 35ns access
ICC1 Max Com. 50 mA 65 mA @ 25ns access
ICC1 Max Ind. 35 mA 55 mA @ 45ns access
ICC1 Max Ind. 45 mA 60 mA @ 35ns access
ICC1 Max Ind. 55 mA 70 mA @ 25ns access
ICC2 Max 1.5 mA 3.0 mA Com. & Ind.
ICC4 Max 0.5 mA 3 mA Com & Ind.
tHRECALL 5 ms 20 ms
tSTORE 10 ms 12.5 ms
tRECALL 20µs 40µs
tGLQV 10ns 12ns 25 ns device
SIMTEK STK14CA8 Data Sheet, December 2004
Copyright 2004, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or
means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but
changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or
transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
