MC74HC00ADT - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995 1

10/95

REV 7

   

High–Performance Silicon–Gate CMOS

The MC54/74HC00A is identical in pinout to the LS00. The device

inputs are compatible with Standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2 to 6V

•Low Input Current: 1µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements

•Chip Complexity: 32 FETs or 8 Equivalent Gates

3Y1

PIN 14 = VCC

PIN 7 = GND

LOGIC DIAGRAM

6Y2

A2 5

8Y3

A3 10

11 Y4

A4 13

Y = AB

Pinout: 14–Lead Packages (Top View)

1314 12 11 10 9 8

21 3 4 5 6 7

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND



FUNCTION TABLE

Inputs Output

A B

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXAJ

MC74HCXXAN

MC74HCXXAD

MC74HCXXADT

Ceramic

Plastic

SOIC

TSSOP

14 DT SUFFIX

TSSOP PACKAGE

CASE 948G–01

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

MC54/74HC00A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

Ceramic DIP

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC00A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

Guaranteed Limit

Symbol Parameter Condition

VCC

–55 to 25°C≤85°C≤125°C Unit

VIH Minimum High–Level Input Voltage Vout = 0.1V or VCC –0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High–Level Output

Voltage Vin = VIH or VIL

|Iout| ≤ 20µA2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low–Level Output

Voltage Vin = VIH or VIL

|Iout| ≤ 20µA2.0

4.5

6.0

0.1

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

ICC Maximum Quiescent Supply

Current (per Package) Vin = VCC or GND

Iout = 0µA6.0 1.0 10 40 µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

VCC

Guaranteed Limit

Symbol Parameter

VCC

–55 to 25°C≤85°C≤125°C Unit

tPLH,

tPHL Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 2) 2.0

3.0

4.5

6.0

110

tTLH,

tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 2) 2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC00A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Figure 1. Switching Waveforms

GND

VCC

OUTPUT Y

INPUT

A OR B

CL*

*Includes all probe and jig capacitance

TEST

POINT

90%

50%

10%

tTLH

DEVICE

UNDER

TEST

OUTPUT

Figure 2. Test Circuit

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

tTHL

90%

50%

10%

tPLH tPHL

tftr

MC54/74HC00A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.785

0.280

0.200

0.020

0.065

0.015

0.170

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G N

0.25 (0.010) T A

MS0.25 (0.010) T B

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

MC54/74HC00A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

8.55

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B– P 7 PL

SEATING

PLANE

D 14 PL MJ

R X 45°

814

0.25 (0.010) T B A

MS S

B0.25 (0.010) M M

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

_ _ _ _

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L–U–

SEATING

PLANE

0.10 (0.004)

–T–

ÇÇÇ

SECTION N–N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

–W–

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

–V–

14X REFK

MC54/74HC00A

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

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and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

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MC54/74HC00A/D

*MC54/74HC00A/D*

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