1. Product profile
1.1 General description
NPN/PNP Resistor-Equipped Transistors (RET).
1.2 Features
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
1.3 Applications
Low current peripheral driver
Control of IC inputs
Replaces general-purpose transistors in digital applications
1.4 Quick reference data
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors;
R1 = 10 kΩ, R2 = 10 kΩ
Rev. 10 — 15 November 2009 Product data sheet
Table 1. Product overview
Type number Package PNP/PNP
complement NPN/NPN
complement
NXP JEITA
PEMD3 SOT666 - PEMB11 PEMH11
PIMD3 SOT457 SC-74 - -
PUMD3 SOT363 SC-88 PUMB11 PUMH11
Table 2. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCEO collector-emitter voltage open base - - 50 V
IOoutput current (DC) - - 100 mA
R1 bias resistor 1 (input) 7 10 13 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 2 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
2. Pinning information
3. Ordering information
4. Marking
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 3. Pinning
Pin Description Simplified outline Symbol
1 GND (emitter) TR1
2 input (base) TR1
3 output (collector) TR2
4 GND (emitter) TR2
5 input (base) TR2
6 output (collector) TR1 001aab55
5
6 45
1 32
65 4
123
R2
TR1
TR2
R1
R2 R1
006aaa14
3
Table 4. Orderin g i nformation
Type number Package
Name Description Version
PEMD3 - plastic surface mounted package; 6 leads SOT666
PIMD3 SC-74 plastic surface mounted package; 6 leads SOT457
PUMD3 SC-88 plastic surface mounted package; 6 leads SOT363
Table 5. Marking codes
Type number Marking code[1]
PEMD3 D3
PIMD3 M7
PUMD3 D*3
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 3 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint.
[3] Reflow soldering is the only recommended soldering method.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor with negative polarity
VCBO collector-base voltage open emitter - 50 V
VCEO collector-emitter voltage open base - 50 V
VEBO emitter-base voltage open collector - 10 V
VIinput voltage TR1
positive - +40 V
negative - −10 V
input voltage TR2
positive - +10 V
negative - −40 V
IOoutput current (DC) - 100 mA
ICM peak collector current - 100 mA
Ptot total power dissipation Tamb ≤25 °C
SOT363 [1] -200mW
SOT457 [2] -300mW
SOT666 [1][3] -200mW
Tstg storage temperature −65 +150 °C
Tjjunction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Per device
Ptot total power dissipation Tamb ≤25 °C
SOT363 [1] -300mW
SOT457 [2] -600mW
SOT666 [1][3] -300mW
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 4 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint.
[3] Reflow soldering is the only recommended soldering method.
7. Characteristics
Table 7. Thermal characteris tics
Symbol Parameter Conditions Min Typ Max Unit
Per transis tor
Rth(j-a) thermal resistance from
junction to ambient in free air
SOT363 [1] --625K/W
SOT457 [2] --417K/W
SOT666 [1][3] --625K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient in free air
SOT363 [1] --416K/W
SOT457 [2] --208K/W
SOT666 [1][3] --416K/W
Table 8. Characteristics
Tamb = 25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per transistor; for the PNP transistor with negative polarity
ICBO collector-base cut-off
current VCB =50V; I
E= 0 A - - 100 nA
ICEO collector-emitter
cut-off current VCE =30V; I
B=0A - - 1 μA
VCE =30V; I
B=0A;
Tj=150°C--50μA
IEBO emitter-base cut-off
current VEB =5V; I
C= 0 A - - 400 μA
hFE DC current gain VCE =5V; I
C=5mA 30 - -
VCEsat collector-emitter
saturation voltage IC=10mA; I
B= 0.5 mA - - 150 mV
VI(off) off-state input voltage VCE =5V; I
C=100μA-1.10.8V
VI(on) on-state input voltage VCE =0.3V; I
C=10mA 2.5 1.8 - V
R1 bias resistor 1 (input) 7 10 13 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2
Cccollector capacitance VCB =10V; I
E=i
e=0A;
f=1MHz ---
TR1 (NPN) - - 2.5 pF
TR2 (PNP) - - 3 pF
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 5 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
VCE =5V
(1) Tamb = 150 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
IC/IB=20
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
Fig 1. TR1 (NPN): DC current gain as a function of
collector current; typical values Fig 2. TR1 (NPN): Collector-emitter voltage as a
function of collector current; typical values
VCE =0.3V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
VCE =5V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
Fig 3. TR1 (NPN): On-state input voltage as a
function of collector current; typical values Fig 4. TR1 (NPN): Off-state input voltage as a
function of collector current; typical values
IC (mA)
10−1102
101
006aaa034
102
10
103
hFE
1
(1)
(2)
(3)
IC (mA)
110
2
10
006aaa035
10−1
1
VCEsat
(V)
10−2
(1)
(2)
(3)
006aaa036
IC (mA)
10−1102
101
1
10
VI(on)
(V)
10−1
(2)
(3)
(1)
006aaa037
IC (mA)
10−210110−1
1
10
VI(off)
(V)
10−1
(1)
(2)
(3)
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 6 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
VCE =−5V
(1) Tamb = 150 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
IC/IB=20
(1) Tamb = 100 °C
(2) Tamb =25°C
(3) Tamb =−40 °C
Fig 5. TR2 (PNP): DC current gain as a function of
collector current; typical values Fig 6. TR2 (PNP): Collector-emitter voltage as a
function of collector current; typical values
VCE =−0.3 V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
VCE =−5V
(1) Tamb =−40 °C
(2) Tamb =25°C
(3) Tamb = 100 °C
Fig 7. TR2 (PNP): On-state input voltage as a
function of collector current; typical values Fig 8. TR2 (PNP): Off-state input voltage as a
function of collector current; typical values
IC (mA)
−10−1−102
−10−1
006aaa046
−102
−10
−103
hFE
−1
(1)
(2)
(3)
IC (mA)
−1−102
−10
006aaa047
−10−1
−1
VCEsat
(V)
−10−2
(1)
(2)
(3)
IC (mA)
−10−1−102
−10−1
006aaa048
−10
−1
−102
VI(on)
(V)
−10−1
(1) (2)
(3)
006aaa049
IC (mA)
−10−2−10−1−10−1
−1
−10
VI(off)
(V)
−10−1
(1)
(2)
(3)
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 7 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
8. Package outline
Fig 9. Pac kage outline SOT363 (SC-88) Fig 10. Package outline SOT457 (SC-74)
Fig 11. Package outline SOT666
06-03-16Dimensions in mm
0.25
0.10
0.3
0.2
pin 1
index
1.3
0.65
2.2
2.0
1.35
1.15
2.2
1.8
1.1
0.8
0.45
0.15
132
465
04-11-08Dimensions in mm
3.0
2.5
1.7
1.3
3.1
2.7
pin 1 index
1.9
0.26
0.10
0.40
0.25
0.95
1.1
0.9
0.6
0.2
132
4
56
Dimensions in mm 04-11-08
1.7
1.5
1.7
1.5
1.3
1.1
1
0.18
0.08
0.27
0.17
0.5
pin 1 index
123
456
0.6
0.5
0.3
0.1
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 8 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
9. Packing information
[1] For further information and the availability of packing methods, see Section 12.
[2] T1: normal taping
[3] T2: reverse taping
Table 9. Packing methods
The indicated -xxx are the last thre e digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 4000 8000 10000
PEMD3 SOT666 2 mm pitch, 8 mm tape and reel - - -315 -
4 mm pitch, 8 mm tape and reel - -115 - -
PIMD3 SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165
PUMD3 SOT363 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 9 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
10. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PEMD3_PIMD3_ PUMD3_10 20091115 Product data sheet - PEMD3_PIMD3_ PUMD3_9
Modifications: •This data sheet was changed to reflect the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•Figure 9 “Package outline SOT363 (SC-88)”: updated
PEMD3_PIMD3_ PUMD3_9 20050518 Product data sheet - PEMD3_PIMD3_ PUMD3_8
PEMD3_PIMD3_ PUMD3_8 20041206 Product data sheet - PEMD3_PUMD3_7
PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 10 of 11
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
11. Legal information
11.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
11.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
11.3 Disclaimers
General — In formation in this document is believed to be accurate and
reliable. However, NXP Semiconductors d oes not give an y represent ations or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and with out
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ra tings System of IEC 60134) may cause permane nt
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertain i ng to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patent s or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
11.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
12. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 15 November 2009
Document identifier: PEMD3_PIMD3_PUMD3_10
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
13. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Packing information . . . . . . . . . . . . . . . . . . . . . 8
10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
11.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
11.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Contact information. . . . . . . . . . . . . . . . . . . . . 10
13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
