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Single-chip Type with built-in FET Switching Regulator Series
Output 0.5A or Less High Efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9122GUL
●Description
ROHM’s high efficiency step-down switching regulator (BD9122GUL) is a power supply designed to produce a low voltage
including 1 volts from 5/3.3 volts power supply line. Offers high efficiency with our original pulse skip control technology and
synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLMTM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs WL-CSP : VCSP50L2
●Use
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute Maximum Ratings (Ta=25℃)
Parameter Symbol Limits Unit
VCC Voltage VCC -0.3～+7 ＊1 V
PVCC Voltage PVCC -0.3～+7 ＊1 V
EN Voltage VEN -0.3～+7 V
SW,ITH Voltage VSW,VITH -0.3～+7 V
Power Dissipation Pd 660＊2 mW
Operating temperature range Topr -25～+85 ℃
Storage temperature range Tstg -55～+150 ℃
Maximum junction temperature Tjmax +150 ℃
＊1 Pd should not be exceeded.
＊2 Derating in done 5.28mW/℃ for temperatures above Ta=25℃, Mounted on 50mm×58mm×1.6mm Glass Epoxy PCB.
●Operating Conditions (Ta=25℃)
Parameter Symbol Limits Unit
Min. Typ. Max.
VCC Voltage VCC *3 2.5*4 3.3 5.5 V
PVCC Voltage PVCC *3 2.5*4 3.3 5.5 V
EN Voltage EN 0 - VCC V
SW average output Isw *3 - - 0.3 A
Output voltage Setting Range VOUT 1.0 - 2.0 V
＊3 Pd should not be exceeded.
＊4 In case set output voltage 1.8V or more, VccMin = 2.7V.
No.09027EAT31
Technical Note
BD9122GUL
2/13
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●Electrical Characteristics
◎(Ta=25℃, VCC=PVCC=3.3V, EN=VCC, R1=20k, R2=10k, unless otherwise specified.)
Parameter Symbol Limits Unit Conditions
Min. Typ. Max.
Standby current ISTB - 0 10 A EN=GND
Bias current ICC - 250 400 A
EN Low voltage VENL - GND 0.8 V Standby mode
EN High voltage VENH 2.0 VCC - V Active mode
EN input current IEN - 1 10 A VEN=3.3V
Oscillation frequency FOSC 0.8 1 1.2 MHz
Pch FET ON resistance RONP - 0.3 0.6 PVCC=3.3V
Nch FET ON resistance RONN - 0.2 0.5 PVCC=3.3V
ADJ Voltage VADJ 0.780 0.800 0.820 V
Output voltage VOUT - 1.200 - V
ITH SInk current ITHSI 10 20 - A VADJ=1.0V
ITH Source Current ITHSO 10 20 - A VADJ=0.6V
UVLO threshold voltage VUVLO1 2.2 2.3 2.4 V VCC=30V
UVLO release voltage VUVLO2 2.22 2.35 2.5 V VCC=03V
Soft start time TSS 0.5 1 2 ms
Timer latch time TLATCH 1 2 4 ms SCP/TSD operated
Output Short circuit Threshold Voltage VSCP - VOUT×0.5 - V VOUT=2→0V
●Block Diagram, Application Circuit
Fig.1 Block Diagram
3.3V
Input
PVCC
PGND
SW
GND
Output
Gm Amp 4.7µH
VCC
R
S
Q
OSC
UVLO
TSD
+
4.7μF
VCC
VCC
CLK
SLOPE
EN
Current
Comp 10µF
Soft
Start
Current
Sense/
Protect
+
Driver
Logic
+
VREF
ITH
A
DJ
RITH CITH
R1 R2
SCP
Technical Note
BD9122GUL
3/13
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© 2009 ROHM Co., Ltd. All rights reserved.
0.0
0.5
1.0
1.5
2.0
012345
INPUT VOLTAGE:VCC[V]
OUTPUT VOLTAGE:VOUT[V]
Ta= 2 5 ℃
Io=0A
0.0
0.5
1.0
1.5
2.0
012345
EN VOLTAGE:VEN[V]
OUTPUT VOLTAGE:VOUT[V]
0.0
0.5
1.0
1.5
2.0
0123
OUTPUT CURRENT:IOUT [A]
OUTPUT VOLTAGE:VOUT[V]
【VOUT=1.5V】
Ta= 2 5 ℃
Io=0A
【VOUT=1.5V】 【VOUT=1.5V】
VCC=3.3V
Ta= 2 5 ℃
●Pin configuration
Fig.2 TOP View Fig.3 Physical Dimension : VCSP50L2
●Pin number and function
Pin No. Pin name Pin function
A1 PGND Nch FET source pin
A2 GND Ground
A3 EN Enable pin（Active High）
A4 ITH Gm Amp output pin/Connected phase compensation capacitor
B1 SW Pch/Nch FET drain output pin
B2 PVCC Pch FET source pin
B3 VCC Vcc power supply input pin
B4 ADJ Output voltage detect pin
●Characteristics data(Reference data)
Fig.4 Vcc - VOUT Fig.5 VEN - VOUT Fig.6 IOUT - VOUT
9 1 2 2
Lot No.
(unit : mm)
VCC=3.3V
TOP View
SW B1
PVcc B2
Vcc B3
ADJ B4
A
1 PGND
A
2 GND
A
3 EN
A
4 ITH
Technical Note
BD9122GUL
4/13
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© 2009 ROHM Co., Ltd. All rights reserved.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
-25-15-5 5 1525354555657585
TEMPERATURE:Ta [℃]
ON RESISTANCE:R ON [ Ω]
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-25-15 -5 5 1525 35455565 7585
TEMPERATURE:Ta[℃]
EN VOLTAGE:VEN[V]
100
130
160
190
220
250
280
310
340
370
400
-25-15 -5 5 1525 35455565 7585
TEMPERATURE:Ta[℃]
CIRCUIT CURRENT:ICC [μA]
PMOS
NMOS
VCC=3.3V VCC=3.3V
VCC=3.3V
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
-25-15-5 5 1525354555 657585
TEMPERATURE:Ta[℃]
OUTPUT VOLTAGE:VOUT[V]
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
OUTPUT CURRENT:IOUT[mA]
EFFICIENCY:
η[%]
VCC=3.3V
Io=0A
【VOUT=1.5V】
VCC=3.3V
Ta= 2 5 ℃
【VOUT=1.5V】
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
FREQUENCY:FOSC[MHz]
●Characteristics data(Reference data) – Continued
Fig. 7 Ta - VOUT Fig.8 Efficiency Fig.9 Ta - Fosc
Fig.10 Ta – RONN, RONP Fig.11 Ta - VEN Fig.12 Ta - Icc
Fig.13 Vcc - Fosc Fig.14 Soft start waveform Fig.15 SW waveform Io=10mA
Fig.16 SW waveform Io=200mA
Fig.17 Transient Response
Io=50→125mA(10s)
Fig.18 Transient Response
o=125→50mA(10s)
VCC=3.3V
0.8
0.9
1
1.1
1.2
2.545.5
INPUT VOLTAGE:VCC[V]
FREQUENCY:FOSC[MHz]
Ta= 2 5 ℃
VOUT
VCC=PVCC
=EN
VCC=3.3
V
Ta= 2 5 ℃
Io=0
SW
VOUT
VCC=3.3
V
Ta= 2 5 ℃
【SLLMTM control VOUT=1.5V】
【VOUT=1.5V】
VOUT
IOUT
VOUT
IOUT
SW
VOUT VCC=3.3V
Ta= 2 5 ℃
【PWM control VOUT=1.5V】
VCC=3.3V
Ta= 2 5 ℃
【VOUT=1.8V】
VCC=3.3V
T
a
=2
5
℃
【VOUT=1.8V】
Technical Note
BD9122GUL
5/13
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© 2009 ROHM Co., Ltd. All rights reserved.
●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
Fig.19 Comparison of transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance
MOS FETs incorporated as power transistor.
ON resistance of P-channel MOS FET : 0.3(Typ.)
ON resistance of N-channel MOS FET : 0.2(Typ.)
Fig.20 Efficiency
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
Reduces a mounting area required.
Fig.21 Example application
・Output capacitor Co required for current mode control: 10F ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2H inductor
0.001 0.01 0.1 1
0
50
100
①
②
PWM
SLLM
TM
①inprovement by SLLM system
②improvement by synchronous rectifier
Efficiency [%]
Output current Io[A]
BD9122GUL(transient response IO=50mA⇔125mA)
VOUT
IOUT
VCC=3.3V
Ta
=
25
℃
【VOUT=1.8V】
VOUT
IOUT
VCC=3.3V
T
a
=2
5
℃
【VOUT=1.8V】
Io=50→125mA Io=125→50mA
DC/DC
Convertor
Controller
RITH
L
Co
VOUT
CITH
VCC
Cin
8mm
8mm
RITH
CITH
CIN CO L
CVCC
Technical Note
BD9122GUL
6/13
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●Operation
BD9122GUL is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse
is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is
tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the
switching dissipation and improves the efficiency.
Fig.22 Diagram of current mode PWM control
Fig.23 PWM switching timing chart Fig.24 SLLMTM switching timing chart
Curren
t
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
IL(AVE)
VOUT(AVE)
SENSE
FB
Current
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
0A
VOUT(AVE)
SENSE
FB
IL
Not switching
IL
OSC
Level
Shift Driver
Logic
RQ
S
IL
SW
ITH
Current
Comp
Gm Amp.
SET
RESET
FB
Load
SENSE
VOUT
VOUT
Technical Note
BD9122GUL
7/13
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●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0F (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
50 mV (Typ.) is provided to prevent output chattering.
Fig.25 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the
fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
Fig.26 Short-current protection circuit with time delay timing chart
Hysteresis 50mV
Ts s Ts s Ts s
Soft start
Standby mode Operating mode
Standby
mode Operating mode
Standby
mode Operating mode Standby mode
UVLO
EN UVLO
UVLO
VCC
EN
VOU
T
t2=TLATCH
Output OFF
latch
EN
VOUT
Output Short circuit
Threshold Voltage
IL
Standby
mode Operating mode Operating mode
EN Timer latch EN
Standby
mode
IL Limi
t
t1<TLATCH
Technical Note
BD9122GUL
8/13
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●Switching regulator efficiency
Efficiency may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors PD as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[]：DC resistance of inductor, RON[]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor, ESR[]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
Fig.27 Thermal derating curve
(VCSP50L2)
If VCC=3.3V, VOUT=1.5V, RONP=0.3, RONN=0.2
IOUT=0.3A, for example,
D=VOUT/VCC=1.5/3.3=0.45
RON=0.45×0.3+(1-0.45)×0.2
=0.135+0.11
=0.245[]
P=0.32×0.245≒22.1[mW]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
= VOUT×IOUT
Vin×Iin
×100[%]= POUT
Pin
×100[%]= POUT
POUT+PD
×100[%]
Vin2×CRSS×IOUT×f
IDRIVE
3)PD(SW)= (CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
Power dissipation:Pd [W]
Ambient temperature:Ta [℃]
0 25 50 75 100 125 150
0
1.0
0.66W
VCSP50L2(2.50×1.10mm)
ROHM standard 1 layer board
Board size：50mm×58mm
j-a=189.4℃/W
0.8
0.6
0.4
0.2
Technical Note
BD9122GUL
9/13
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●Selection of components externally connected
1. Selection of inductor (L)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
2. Selection of output capacitor (CO)
As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be
determined with consideration on the requirements of equation (5):
if VOUT=1.5V, IOUT=0.3A, and TSS=1ms,
Inappropriate capacitance may cause problem in startup. 10F to 100F ceramic capacitor is recommended.
3. Selection of input capacitor (Cin)
A low ESR 10F/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
The inductance significantly depends on output ripple current.
A
s seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
IL=
(VCC-VOUT)×VOUT
L×VCC×f
[
A
]
・・・
(
1
)
A
ppropriate ripple current at output should be 30% more or less of the
maximum output current.
IL=0.3×IOUTmax. [A]・・・(2)
L=
(VCC-VOUT)×VOUT
IL×VCC×f [H]・・・
(
3
)
(IL: Output ripple current, and f: Switching frequency)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4)：
VOUT=IL×ESR [V]・・・(4)
(IL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
* Rating of the capacitor should be determined allowing sufficient margin
against output voltage. Less ESR allows reduction in output ripple voltage.
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (6):
IRMS=IOUT×
VOUT
(
VCC-VOUT
)
VCC [A]・・・
(
6
)
√
When Vcc is twice the VOUT, IRMS=
IOUT
2
Fig.29 Output capacitor
< Worst case > IRMS(max.)
IRMS=0.3×
1.5
(
3.3-1.5
)
3.3 =0.15
[
ARMS
]
√
Fig.30 Input capacitor
IL
VCC
IL
L
Co
VOUT
Fig.28 Output ripple current
IL
VCC
L
Co
VOUT
ESR
VCC
L Co
VOUT
Cin
If VCC=3.3V, VOUT=1.5V, and IOUTmax.=0.3A
Co≦ TSS×(Ilimit-IOUT)
VOUT ・・・
(
5
)
Tss: Soft-start time
Ilimit: Over current detection level, 1A(Typ)
Co≦ 1m×(1-0.3)
1.5
≒467 [F]
Technical Note
BD9122GUL
10/13
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4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
5. Determination of output voltage
The output voltage VOUT is determined by the equation (7):
VOUT=(R2/R1+1)×VADJ・・・(7) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
Adjustable output voltage range : 1.0V～2.0V
Use 1 k～100 k resistor for R1. If a resistor of the resistance higher than
100 k is used, check the assembled set carefully for ripple voltage etc.
Fig.34 Deter mination
of output voltage
Fig.31 Open loop gain characteristics
Fig.32 Error amp phase compensation characteristics
fp=
2×RO×CO
1
fz(ESR)=2×ESR×CO
1
Pole at power amplifie
r
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fp(Min.)=2×ROMax.×CO
1[Hz]with lighter load
fp(Max.)=2×ROMin.×CO
1[Hz] with heavier load
Zero at power amplifie
r
fz(Amp.)=2×RITH×CITH
1
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
VOUT
Cin
RITH
CITH
L
ESR
CO
RO
VOUT
Fig.33 Typical application
fz(Amp.)= fp(Min.)
2×RITH×CITH
1 = 2×ROMax.×CO
1
Gain
[dB]
Phase
[deg]
A
0
0
-90
A
0
0
-90
fz(Amp.)
fp(Min.)
fp(Max.)
fz(ESR)
IOUTMin. IOUTMax.
Gain
[dB]
Phase
[deg]
SW
A
DJ
L
Co R2
R1
Output
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacito
r
ESR reduces to half.)
Technical Note
BD9122GUL
11/13
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●Cautions on PC Board layout
Fig.35 Layout diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND.
③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
●Recommended components Lists on above application
Symbol Part Value Manufacturer Series
L Coil 2.2uH FDK MIPF2016D2R2
CIN Ceramic capacitor 10uF murata GRM188B30J106ME47B
CO Ceramic capacitor 10uF murata GRM188B30J106ME47B
CITH Ceramic capacitor
VOUT=1.0V
2200pF
murata GRM15 Series
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V 1000pF
VOUT=2.0V
RITH Resistance
VOUT=1.0V
6.8k
ROHM
MCR006 6801 VOUT=1.2V
VOUT=1.5V
VOUT=1.8V 4.7k MCR006 4701
VOUT=2.0V
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your
application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the
depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode
established between the SW and PGND pins.
●I/O equivalent circuit
Fig.36 I/O equivalent circuit
SW
PVcc
Vcc
A
DJ
PGND
GND
EN
ITH
CO
GNDVOUT
VCC
L
①
③
RITH
CITH
CIN
②
ENR2
R1
EN
・EN pin ・SW pin PVCC
SW
PVCC PVCC
ITH
・ITH pin
VCC
・ADJ pin
A
DJ
Technical Note
BD9122GUL
12/13
www.rohm.com 2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
●Cautions on use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4.Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 37.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Fig.37 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
Resistor Transistor (NPN)
N
N N P+ P
+
P
P substrate
GND
Parasitic element
Pin A
N
N P+ P+
P
P substrate
GND
Parasitic element
Pin B C B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
Technical Note
BD9122GUL
13/13
www.rohm.com 2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
●Ordering part number
B D 9 1 2 2 G U L - E 2
Part No. Part No.
9122
Package
GUL: VCSP50L2
Packaging and forming specification
E2: Embossed tape and reel
(VCSP50L2)
(Unit:mm)
V
CSP50L2
<Dimension>
Direction of feed
Tape
Quantity
Direction
of feed
Embossed carrier tape
3000pcs
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand.)
<Tape and Reel information>
Reel 1Pin
1234 1234 1234 1234 1234 1234
※When you order , please order in times the amount of package quantity.
R0039
A
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
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