Freescale Semiconductor
Data Sheet: Technical Data
© 2013-2014 Freescale Semiconductor, Inc. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
The P5021 QorIQ integrated communication processor
combines two Power Architecture® processor cores with
high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and aerospace
applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
The chip includes the following function and features:
• Two e5500 Power Architecture cores
– Each core has a backside 512 KB L2 cache with ECC
– Three levels of instructions: user, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet endpoints
• Frontside 2 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os,
datapath accelerators, and high and low speed peripheral
interfaces
• Two 10-Gigabit Ethernet (XAUI) controllers
• Ten 1-Gigabit Ethernet controllers
– SGMII, 2.5Gb/s SGMII and RGMII interfaces
• Two 64-bit DDR3/3L SDRAM memory controllers with
ECC
• Multicore programmable interrupt controller (PIC)
•Four I
2C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
• Two serial ATA (SATA) 2.0 controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• Two high-speed USB 2.0 controllers with integrated PHYs
• RAID 5 and 6 storage accelerator with support for
end-to-end data protection information
• Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Frame Manager (FMan) for packet parsing,
classification, and distribution
– Queue Manager (QMan) for scheduling, packet
sequencing and congestion management
– Hardware Buffer Manager (BMan) for buffer allocation
and deallocation
– Encryption/Decryption
• 1295 FC-PBGA package
This figure shows the major functional units within the chip.
P5021 QorIQ
Integrated Processor
Data Sheet
Document Number: P5021
Rev. 1, 05/2014
P5021
FC-PBGA–1295
37.5 mm ×37.5 mm
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor2
Table of Contents
1 Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .3
1.1 1295 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3
1.2 Pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .52
2.2 Power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .60
2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.5 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.8 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.9 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .66
2.10 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.11 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.12 Ethernet: data path three-speed Ethernet (dTSEC),
management interface, IEEE Std 1588. . . . . . . . . . . . .77
2.13 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.14 Enhanced local bus interface (eLBC) . . . . . . . . . . . . . .87
2.15 Enhanced secure digital host controller (eSDHC) . . . .92
2.16 Multicore programmable interrupt controller (MPIC)
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
2.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.20 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101
3 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 129
3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . 136
3.3 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.4 Decoupling recommendations . . . . . . . . . . . . . . . . . . 139
3.5 SerDes block power supply decoupling recommendations
140
3.6 Connection recommendations. . . . . . . . . . . . . . . . . . 140
3.7 Recommended thermal model . . . . . . . . . . . . . . . . . 150
3.8 Thermal management information. . . . . . . . . . . . . . . 150
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 151
4.2 Mechanical dimensions of the FC-PBGA . . . . . . . . . 152
5 Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 153
6.2 Orderable part numbers addressed by this document 154
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 3
Figure 1. P5021 block diagram
1 Pin assignments and reset states
1.1 1295 FC-PBGA ball layout diagrams
These figures show the FC-PBGA ball map diagrams.
Real-time debug
18-Lane 5-GHz SerDes
512 KB
backside
L2 cache
Frame Manager
QorIQ P5021
Power Architecture®
e5500 Core
Security
5.0
eLBC
Queue
Mgr
Buffer
Mgr
eOpenPIC
Internal
Power mgmt
SD/MMC
SPI
2x DUART
4x I
2
Cs
Clocks/Reset
GPIO
CCSR
BootROM
2x USB 2.0
+ 2x PHY
Security
Monitor
PreBoot
Loader
32 KB
D-cache
32 KB
I-cache
1024 KB
frontside
L3 cache
64-bit
1600 MT/s DDR-3
memory controller
CoreNet™
Coherency Fabric
PA M UPA M U PA M U
Buffer
Parse, classify,
distribute
PCIe
PCIe
SATA 2.0
SATA 2.0
64-bit
1600 MT/s DDR-3
memory controller
1024 KB
frontside
L3 cache
PA M U
Perf
monitor
CoreNet
trace
Watchpoint
cross
trigger
Tes t
Port/
SAP
RAID5/6
PCIe
DMA
DMA
10GE
1GE
1GE
1GE
1GE 1GE
Frame Manager
Buffer
Parse, classify,
distribute
1GE
1GE 1GE
1GE
1GE
1GE
10GE
PA M U
Peripheral access
management unit (PAMU)
SATA
SerDes
RGMII
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor4
Figure 2. 1295 BGA ball map diagram (top view)
LA
29
29 30 31 321171615141312111098765432 18 19 20 21 22 23 24 25 26 27 28 33 34 3635
AJ
AK
AL
AM
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
AN
AP
AR
AT
D2_
MDQ
20
D2_
MDQ
10
D2_
MDQS
1
D2_
MDQ
08
D2_
MDQ
03
D2_
MDQ
07
D2_
MDQ
04
D1_
MDQ
03
D1_
MDQ
06
D2_
MDQ
16
GVDD D2_
MDQ
17
D2_
MDM
1
D2_
MDQ
13
D2_
MDQ
02
D2_
MDM
0
D2_
MDQ
05
D1_
MDQ
07
D2_
MDQS
2
D2_
MDM
2
D2_
MDQ
14
D1_
MDQ
21
D2_
MDQ
22
D2_
MDQ
23
D2_
MDQ
18
D2_
MDQ
15
D2_
MDQ
09
D1_
MDQS
2
D1_
MDM
2
D1_
MDQ
17
D1_
MDQ
20
D2_
MDQ
00
D1_
MDQ
02
D1_
MDQ
08
D2_
MDQ
19
D2_
MDQ
29
D1_
MDQ
18
D1_
MDQ
19
D1_
MDQ
13
RSRV D2_
MDQ
24
D2_
MDQ
25
D1_
MDQ
24
D1_
MDQ
28
D1_
MDQ
25
D2_
MDM
3
D2_
MDQS
3
D1_
MDQ
11
D1_
MDQS
1
LAD
31
D2_
MDQ
31
D2_
MDQ
30
D2_
MDQ
26
D2_
MDQ
27
D1_
MDQ
30
D1_
MDQ
31
NC_
H15
D2_
MECC
5
D2_
MECC
4
D1_
MECC
5
D1_
MDQ
27
NC_
J14
LAD
15
D2_
MDM
8
D1_
MDM
8
D1_
MECC
0
NC_
K14
LAD
14
D2_
MECC
6
D2_
MECC
7
D1_
MECC
6
D1_
MECC
7
D2_
MCKE
3
D2_
MECC
02
D1_
MBA
2
D2_
MECC
3
D2_MA
09
D2_
MCKE
2
D2_MA
06
D2_MA
08
D2_MA
07
D2_
MCKE
0
D2_MA
03
D2_MA
04
D2_MA
05
D1_MA
01
D1_MA
02
D1_MA
03
D1_MA
04
D1_
MDM
0
D1_
MDQ
00
D2_
MDQ
06
D1_
MDQS
0
D1_
MDQ
05
D2_
MDQ
12
D1_
MDQS
0
D1_
MDQ
04
D1_
MDM
1
D1_
MDQ
22
D1_
MDQ
10
GVDD
GND
GVDD
GND
GVDD
GND
GND
GVDD
GVDD
GND
GVDD
GND
GND
GVDD
GND
GVDD
GVDD
GND
GVDD
NC_
E16
GND
GND
GVDD
NC_
D18
LA
28
GND GVDD D1_
MDQ
29
GND GVDD D1_
MDQ
15
GND D1_
MDQ
12
GVDD GND D1_
MDQS
3
GVDD GND D1_
MDQ
09
GVDD
GVDD GND GVDD
GND
NC_
H12
NC_
H13
GVDD BVDD
GND GVDD D1_
MECC
4
GND NC_
J11
GVDD NC_
J13
LAD
13
D2_
MECC
1
GVDD D1_
MDQS
8
GND GVDD NC_
K11
NC_
K12
NC_
K13
SENSE-
VDD_CA
SENSE-
GND_CA
GVDD GND GVDD VDD_PL GND VDD_PL VDD_PL VDD_PLGND GND GND
D2_
MBA
2
GND GVDD GND GND VDD_PL GND GND GNDVDD_PL VDD_CA VDD_CA
D2_MA
12
D2_MA
14
GVDD GND GVDD VDD_PL VDD_PL VDD_CA VDD_CAGND GND GND GND
GVDD GND GVDD D1_
MCKE
0
GND VDD_PL GND GND GNDVDD_CA VDD_CA VDD_CA
GND GVDD D1_MA
07
GND VDD_PL VDD_PL VDD_CA VDD_CAGND GND GND GND
GVDD D1_
MDIC
0
GND D1_MA
06
GVDD GND VDD_PL GND GND GNDVDD_PL VDD_CA VDD_CA
GVDD GND GVDD VDD_PL VDD_PL VDD_PL VDD_PLGND GND GND GND
GVDD GND GND VDD_PL GND GND GNDVDD_PL VDD_PL VDD_PL
D2_
MDQ
21
SD_RX
16
TMS
TMS
PD
GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
NC_
W27 SD_TX
12
SD_TX
12
XGND SD_RX
12
SD_RX
12
SGND SVDD
GND GND GND GND
GND VDD_PL VDD_PL VDD_PL GND XGND SD_TX
13
SVDD
SGND
SD_RX
13
SD_RX
13
GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL SD1_IMP_
CAL_TX
XVDD SD_TX
14
SD_RX
14
SD_RX
14
SGND
GND GND GND GNDGND VDD_PL VDD_PL VDD_PL GND SD_TX
18
SD_TX
18
SD_TX
15
XGND SGND
SVDD
AVD D_
SRDS3
AGND_
SRDS3
GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL VDD_
LL
S1VDD XVDD
GND GND GND GND
VDD_PL VDD_PL VDD_PL VDD_PL GND VDD_
LP
XGND
SD_
REF_
CLK3
SD_
REF_
CLK3
SGND SVDD
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND SD_RX
18
SVDD
SGND
GND GND GND GND
VDD_PL VDD_PL VDD_PL SD_RX
19
SGNDSD_RX
19
SD1_IMP
CAL_RX
SD_RX
16
SVDD SGND
DMA2_
DACK
0
GPIO
07
OVDD PD SD_TX
19
S1V
DD
RSRVX1VDD
SD_TX
19
IO_
VSEL
4
MSRCID
0
GPIO
04
GND USB1_
AGND
USB1_
VDD_
USB2_
VDD_ USB2_
AGND
SPI_
MISO
SD_PLL4
_TPD
GND
EMI2_
MDIO
EMI2_
MDC
MSRCID
1
DMA2_
DREQ
0
GPIO
05
OVDD USB1_
AGND
USB1_
VDD_
USB2_
VDD_
USB2_
VDD_ SPI_CS
1
CVDD GND EMI1_
MDC
LVDD
GND CLK_
OUT
GPIO
06
GPIO
01
USB1_
UID
USB1_
VBUS_
USB2_
VBUS_ USB2_
UID
GND SPI_
CLK
LVDD
DMA1_
DACK
0
OVDD GPIO
00
SHDC_ USB1_
VDD_
USB1_
IBIAS_
GND LVDD EMI1_
MDIO
EC2_
GTX_
GND
TSEC_
1588_CLK
_IN
SDHC_
GND
GPIO
02
CKSTP_
OUT
USB_
CLKIN
USB1_
VDD_1P8
SPI_CS
3
GND EC1_
RXD
03
LVDD
OVDD
DMA1_
DDONE
0
GPIO
03
TMP_
DETECT RTC
SPI_CS
0
GND PD
12
PD
06
LVDD EC1_
RXD
2
EC1_
RXD
1
EC1_
RXD
0
GND
DMA2_
DDONE
0
DMA1_
DREQ
0
GND PD
14 CVDD PD
02
LVDD PD
07
PD
05
GND
EC1_
GTX_
CLK
EC1_
TXD
3
TRST ASLEEP TCK OVDD
AVDD_
FM
SPI_CS
2
PD
03
PD
09
GND
EC1_
RX_DV
PD
10
EC1_
TXD
1
LVDD EC1_
TX_EN
AVD D_
PLAT
TEST_
SEL
GND SYSCLK
PD
15 SPI_
MOSI
PD
04
PD
01
PD
08
PD
11
EC1_
TXD
2
EC1_
TXD
0
GND
EC1_
RX_CLK
EC_XTRNL
_TX_STMP
2
EC_XTRNL
_RX_STMP
2
TSEC_
1588_CLK_
OUT
TSEC_
1588_PULSE
_OUT01
TSEC_
1588_PULSE
_OUT2
EC_XTRNL
_TX_STMP
1
TSEC_
1588_ALARM
_OUT2
TSEC_
1588_ALARM
_OUT1
TSEC_
1588_TRIG
_IN2
TSEC_
1588_TRIG
_IN1
SD_IMP_
CAL_TX
LA
19
LAD
11
GNDLA
28
AVDD_
DDR
MVREF
LBCTL
LCS
5
LCS
00
LCS
1
LA
21
LA
22
LAD
04
SD_TX
03
LAD
07
LAD
06
LA
29
LA
20
LA
18
LAD
05
LAD
03
LA
26
LA
23
GND
LA
24
GND XGND
AVDD_
SRDS4
SD_RX
04
SD_RX
05
SD_RX
05
SGND
SGND
SD_RX
08
SD_RX
09
SD_RX
09
SD_RX
10
SD_RX
10
AVDD_
CC1 LALE AVDD_
SRDS1
AGND_
SRDS1
SD_
REF_
CLK1
SD_
REF_
CLK1
LCS
3
LCS
4
LWE
0
LCS
2
LWE
1
NC_
C19
NC_
C20
GND
GND
GND
GND
LCLK
1
LCLK
0
LAD
09
BVDD LGPL
0
LGPL
4
LGPL
2
GND
NC_
C26
NC_
C27
NC_
D27
SGND
SVDD
SD_RX
00
SD_RX
00
SD_RX
01
SD_RX
01
SGND
SVDD
SVDD SD_RX
03
SD_RX
03
SGND
XGND
SD_RX
02
SVDD
SD_RX
02
SGND SD_TX
04
XGND
BVDD LAD
08
BVDD LGPL
1
LGPL
5
NC_
E27
XGND SD_TX
03
XVDD XVDD SGND SVDD
LAD
12
BVDD GND LCS
6
BVDD GND SD_TX
01
SVDD
LA
25
LA
17
LCS
7
NC_
G27
XVDD SVDD
BVDD LGPL
3
NC_
H27
XGND XGND SD_RX
06
SD_RX
06
GND LAD
10
GND LDP
0
LA
16
LAD
02
SD_TX
06
XGND SGND SVDD
LA
27
BVDD LDP
1
BVDD LAD
00
XVDD SD_TX
07
SD_TX
07
SVDD SD_RX
07
SD_RX
07
VDD_PL VDD_PLGND VDD_PL VDD_PLGND GND LAD
01
SENSE-
GND_PL
2
SENSE-
VDD_PL
2
XVDD XGND SD_RX
08
SVDD SGND
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND XVDD XGND SD_TX
08
SD_TX
08
SVDD SGND
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL SD_TX
09
SD_TX
09
XVDD SGND SVDD
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND XGND XVDD SD_TX
10
SD_TX
10
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL XVDD XGND SVDD SGND
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND AGND_
SRDS4
XVDD SGND
AVDD_
SRDS2
AGND_
SRDS2
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_
REF_
XGND SGND
GND GND GND GNDVDD_PL VDD_PL VDD_PL VDD_PL GND SD_ XGND XVDD SGND
SVDD
XVDD
SD_IMP_
CAL_RX
29 30 31 321171615141312111098765432 18 19 20 21 22 23 24 25 26 27 28 33 34 3635
AJ
AK
AL
AM
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
AN
AP
AR
AT
D2_
MDQ
48
D1_
MDQ
54
D1_
MDQ
50
D2_
MDQ
56
D2_
MDQ
58
D2_
MDQS
6
D2_
MDQ
54
D2_
MDQS
7
D1_
MDQ
62
D1_
MDQ
59
D2_
MDQ
55
D2_
MDQ
61
D2_
MDQ
57
D2_
MDQ
63
D2_
MDQ
59
D1_
MDQ
56
D1_
MDQS
7
D1_
MDQ
58
D2_
MCK
0
D1_
MCK
0
D2_
MDIC
1
D2_
MCS
0
D1_
MDQ
33
D1_
MDQ
32
D2_
MODT
2
D2_
MODT
0
D1_
MDM
4
D1_
MODT
0
D2_
MODT
3
D2_
MDQ
37
D1_
MDQ
35
D2_
MDM
4
D2_
MDQ
32
D1_
MDQ
45
D1_
MDQ
44
D1_
MODT
1
D2_
MDQ
38
D1_
MDQS
5
D1_
MDM
5
D2_
MDQ
35
D2_
MDQ
34
D1_
MDQ
42
D2_
MDQ
45
D2_
MDQ
44
D1_
MDQ
53
D2_
MDM
5
D2_
MDQ
41
D2_
MDQ
40
D1_
MDQ
49
D1_
MDM
6
D2_
MDQ
52
D2_
MDQS
5
D2_
MDQ
46
D1_
MDQS
6
D1_
MCK
0
GND D1_
MCK
3
D1_
MCK
3
GVDD VDD_PL VDD_PL GND GND
GND GND GND GND
GND GVDD D1_
MBA
1
GND VDD_PL GND GND GND
VDD_PL GND GND
D2_
MAPAR_
OUT
D1_
MDIC
1
GVDD GND VDD_PL VDD_PL GND GND
GND GND GND GND
D2_
MRAS
GVDD GND GVDD GND VDD_PL GND GND GND
GND GND GND
GVDD D2_MA
13
GND GVDD D1_
MCS
0
VDD_PL VDD_PL GND GND
GND GND GND GND
GND GVDD D1_
MODT
2
GND GND VDD_PL GND GND GND
VDD_PL VDD_PL VDD_PL
D1_
MDQ
39
GND GVDD VDD_PL VDD_PL VDD_PL VDD_PL
GND GND GND GND
D2_
MODT
1
GVDD GND GVDD D1_
MCS
3
SENSE-
VDD_PL
1
SENSE-
GND_PL
1
GND GND GND
VDD_PL VDD_PL VDD_PL
GND D1_
MDQ
40
GVDD GND IIC4_
SCL
NC_
AG15
GND
IRQ
06
D2_
MDQS
4
GVDD D1_
MDQS
5
GND GVDD GND IRQ
10
IIC1_
SCL
IRQ
01
IRQ
04
GVDD D2_
MDQ
39
GND D1_
MDQ
46
GVDD GND OVDD IRQ
05
OVDD IRQ
03
IRQ
00
EVT
0
OVDD
GND GVDD GND IRQ
09
IRQ
02
IIC3_
SCL
IRQ_
OUT
GND EVT
3
EVT
1
IO_
VSEL
2
GVDD GND D1_
MDQ
48
GVDD IRQ
11
GND IIC2_
SDA
IIC4_
SDA
OVDD SCAN_
MODE
IO_
VSEL
0
GVDD GND GVDD GND IRQ
07
IIC3_
SDA
IIC2_
SCL
EVT
4
GND IO_
VSEL
3
D2_
MDQ
53
GND D2_
MDQ
42
D2_
MDQ
43
GVDD D1_
MDQ
55
GND D1_
MDQ
51
GVDD IIC1_
SDA
GND EVT
2TDI OVDD
D2_
MDM
6
D2_
MDQ
49
GVDD D2_
MDM
7
GND D1_
MDQ
60
GVDD GND TDO OVDD
PORESET
IO_
VSEL
1
GVDD D2_
MDQ
60
GND D2_
MDQ
62
GVDD D1_
MDQ
61
D1_
MDQ
57
GND GVDD MDVAL GND GND
HRESET
D2_
MDQ
51
D2_
MDQS
7
OVDD RESET_
REQ POVDD
GVDD
AVDD_
CC2
D2_
MDQS
1
D2_
MDQS
0
D2_
MDQS
0
D2_
MDQ
01
D2_
MDQ
11
D2_
MDQS
2
D1_
MDQ
16
D1_
MDQS
2
D1_
MDQ
01
GND
D2_
MDQ
28
D1_
MDQ
23
D1_
MDQ
14
D1_
MDQS
1
D2_
MDQS
3
D1_
MDQS
3
D1_
MDM
3
D1_
MDQ
26
D2_
MECC
0
D1_
MECC
1
D2_
MDQS
8
D1_
MDQS
8
D1_MA
15
D1_
MECC
2
D2_MA
15
D1_MA
14
D1_
MECC
3
D2_
MAPAR_
ERR
D1_MA
12
D1_
MAPAR_
ERR
D1_
MCKE
3
D2_MA
11
D1_MA
09
D1_MA
11
D1_
MCKE
2
D1_MA
08
D1_
MCKE
1
D2_
MCKE
1
D1_MA
05
GNDD2_MA
01
D2_MA
02
D2_
MCK
2
D1_
MCK
1
D2_
MCK
2
D2_
MCK
1
D2_
MCK
1
D1_
MCK
1
D1_
MCK
2
D1_
MCK
2
D2_
MCK
3
D2_
MCK
3
D2_
MCK
0
GVDD GND D2_MA
00
D1_
MAPAR_
OUT
D1_MA
00
D2_
MBA
1
D2_MA
10
D2_
MBA
0
D2_
MDIC
0
D1_MA
10
D1_
MBA
0
D1_
MRAS
D2_
MWE
D2_
MCS
2
D1_
MDQ
36
D1_
MDQ
37
D1_
MWE
D1_
MCS
2
D2_
MCAS
D1_
MCAS
D1_
MDQS
4
D1_
MDQS
4
D2_
MCS
1
D2_
MCS
3
D1_
MDQ
38
D1_MA
13
D1_
MCS
1
D2_
MDQ
36
D1_
MDQ
34
D1_
MODT
3
D2_
MDQ
33
D2_
MDQS
4
D1_
MDQ
41
MSRCID
2
GND
D1_
MDQ
47
D1_
MDQ
43
D1_
MDQ
52
GVDD
D2_
MDQS
5
D2_
MDQ
47
D1_
MDQS
6
VID_
VDD_CA
VID_
VDD_CA
D2_
MDQS
6
TEST_
SEL2
D1_
MDQ
63
VID_
VDD_CA
D2_
MDQ
50
D1_
MDM
7
D1_
MDQS
7
VID_
VDD_CA
NC_
A27
SVDD SGND
NC_
B26
SGND SVDD SGND SVDD
SVDD SD_RX
04
SGND SVDD
SGND
XGND SD_TX
01
SD_TX
04
XVDD SD_TX
05
XVDD
SD_TX
00
XGND XGND SD_TX
05
SGND
SD_TX
00
SD_TX
02
SD_TX
02
XVDD XGND XVDD
LA
30
XVDD XGND XVDD SD_TX
06
GND XGND
XGND XVDD
XGND XGND XGND
XVDD XGND
XVDD XGND SGND SVDD
SD_TX
11
SD_TX
11
XVDD SD_RX
11
SD_RX
11
XGND XVDD SVDD
XGND XVDD SD_
REF_
CLK2
SD_
REF_
CLK2
XVDD
SD_TX
13
XVDD
XGND
XGND SD_TX
14
SVDD
SD_TX
15
XVDD XVDD
XGND SD_RX
15
SD_RX
15
XGND
XGND XVDD
XVDD SD_TX
16
SD_TX
16
XVDD XGND
XGND SD_TX
17
SD_TX
17
SGND SVDD SD_RX
17
SD_RX
17
UART2_
CTS
UART2_
SOUT
UART2_
RTS
UART1_
SOUT
UART1_
RTS
UART2_
SIN
UART1_
CTS
UART1_
SIN
D2_
MDQS
8
SEE DETAIL A SEE DETAIL B
XGND XVDD SGND SGND SVDD
EC_XTRNL
_RX_STMP
1
RSRV
_AD34
SD_RX
18
RSRV
_AD33
RSRV
_AG11
RSRV
_AG12
RSRV
_A25
RSRV
_AH12
RSRV
_AH11
SEE DETAIL C
OVDD
I/O Supply Voltage
LVDD
I/O Supply Voltage
Local Bus I/O Supply
SerDes Core Power Supply
SVDD
SerDes Transcvr Pad Supply
XVDD
DDR DRAM I/O Supply
GVDD
BVDD
Platform Supply Voltage
VDD_
PL
VDD_
CA
Core Group A Supply Voltage
AVDD_
SRDS1
SerDes 1 PLL Supply Voltage
AVDD_
SRDS2
SerDes 2 PLL Supply Voltage
CVDD
SPI Voltage Supply
Platform Voltage Sense
SENSE-
VDD_PL
SENSE-
VDD
Core Group A Voltage Sense
SENSE-
VDD_CB
Core Group B Voltage Sense
Platform PLL Supply Voltage
Core PLL Supply Voltage
AVDD_
CC
AVDD_
PLAT
Reserved
Signal Groups
Fuse Programming Override Supply
POVDD
RSRV
17 13
CLK
DAT
RSRV LA
31
RSRV RSRV
GND LDP
3
LDP
02
_F1 _F2
_G1 _G2
LA
30
LWE
2
LWE
3
IRQ
08
RSRV
_AK1
RSRV
_AK2
RSRV
_AL1
RSRV
_AL2
RSRV
_A21
TEMP_
CATH-
ODE
TEMP_
ANODE
RSRV
_L28
RSRV
_N28
RSRV
_P28
LP_TMP
_DETECT
RSRV
_U35
RSRV
_U32
CVDD
1P0 1P0
3P3 3P3 3P3
CLMP CLMP
2
EC2_
RX_ER
3P3
USB1_
AGND
_DECAP
USB2_
VDD_1P8
_DECAP
USB1_
AGND CLK125
USB1_
AGND
REXT
USB2_
IBIAS_
REXT
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB1_
UDP
USB1_
UDM
USB2_
UDM
USB2_
UDP
USB2_
AGND
RSRV
_C32
RSRV
_D32
EC1_
GTX_
CLK125
LAD
27
CLK4
REF_
CLK4
SEE DETAIL D
_CB3
_CB2
_CB1
_CB0
_AG29
RSRV
_M28
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 5
Figure 3. 1295 BGA ball map diagram (detail view A)
D2_
MDQ
20
D2_
MDQ
10
D2_
MDQS
1
D2_
MDQ
08
D2_
MDQ
03
D2_
MDQ
07
D2_
MDQ
04
D1_
MDQ
03
D1_
MDQ
06
D2_
MDQ
16
GVDD D2_
MDQ
17
D2_
MDM
1
D2_
MDQ
13
D2_
MDQ
02
D2_
MDM
0
D2_
MDQ
05
D1_
MDQ
07
D2_
MDQS
2
D2_
MDM
2
D2_
MDQ
14
D1_
MDQ
21
D2_
MDQ
22
D2_
MDQ
23
D2_
MDQ
18
D2_
MDQ
15
D2_
MDQ
09
D1_
MDQS
2
D1_
MDM
2
D1_
MDQ
17
D1_
MDQ
20
D2_
MDQ
00
D1_
MDQ
02
D1_
MDQ
08
D2_
MDQ
19
D2_
MDQ
29
D1_
MDQ
18
D1_
MDQ
19
D1_
MDQ
13
D2_
MDQ
24
D2_
MDQ
25
D1_
MDQ
24
D1_
MDQ
28
D1_
MDQ
25
D2_
MDM
3
D2_
MDQS
3
D1_
MDQ
11
D1_
MDQS
1
LA
31
D2_
MDQ
31
D2_
MDQ
30
D2_
MDQ
26
D2_
MDQ
27
D1_
MDQ
30
D1_
MDQ
31
NC_
H15
D2_
MECC
5
D2_
MECC
4
D1_
MECC
5
D1_
MDQ
27
NC_
J14
LAD
15
D2_
MDM
8
D1_
MDM
8
D1_
MECC
0
NC_
K14
LAD
14
D2_
MECC
6
D2_
MECC
7
D1_
MECC
6
D1_
MECC
7
D2_
MCKE
3
D2_
MECC
2
D1_
MBA
2
D2_
MECC
3
D2_MA
09
D2_
MCKE
2
D2_MA
06
D2_MA
08
D2_MA
07
D2_
MCKE
0
D2_MA
03
D2_MA
04
D2_MA
05
D1_MA
01
D1_MA
02
D1_MA
03
D1_MA
04
D1_
MDM
0
D1_
MDQ
00
D2_
MDQ
06
D1_
MDQS
0
D1_
MDQ
05
D2_
MDQ
12
D1_
MDQS
0
D1_
MDQ
04
D1_
MDM
1
D1_
MDQ
22
D1_
MDQ
10
GVDD
GND
GVDD
GND
GVDD
GND
GND
GVDD
GVDD
GND
GVDD
GND
GND
GVDD
GND
GVDD
GVDD
GND
GVDD
NC_
E16
GND
GND
GVDD
NC_
D18
GND GVDD D1_
MDQ
29
GND GVDD D1_
MDQ
15
GND D1_
MDQ
12
GVDD GND D1_
MDQS
3
GVDD GND D1_
MDQ
09
GVDD
GVDD GND GVDD GND NC_
H12
NC_
H13
GVDD BVDD
GND GVDD D1_
MECC
4
GND NC_
J11
GVDD NC_
J13
LAD
13
D2_
MECC
1
GVDD D1_
MDQS
8
GND GVDD NC_
K11
NC_
K12
NC_
K13
SENSE-
VDD_CA
SENSE-
GND_CA
GVDD GND GVDD VDD_PL GND VDD_PL VDD_PL VDD_PLGND GND GND
D2_
MBA
2
GND GVDD GND GND VDD_PL GND GND GNDVDD_PL VDD_CA VDD_CA
D2_MA
12
D2_MA
14
GVDD GND GVDD VDD_PL VDD_PL VDD_CA VDD_CAGND GND GND GND
GVDD GND GVDD D1_
MCKE
0
GND VDD_PL GND GND GNDVDD_CA VDD_CA VDD_CA
GND GVDD D1_MA
07
GND VDD_PL VDD_PL VDD_CA VDD_CAGND GND GND GND
GVDD D1_
MDIC
0
GND D1_MA
06
GVDD GND VDD_PL GND GND GNDVDD_PL VDD_CA VDD_CA
GVDD GND GVDD VDD_PL VDD_PL VDD_PL VDD_PLGND GND GND GND
GVDD GND GND VDD_PL GND GND GNDVDD_PL VDD_PL VDD_PL
D2_
MDQ
21
D2_
MDQS
1
D2_
MDQS
0
D2_
MDQS
0
D2_
MDQ
01
D2_
MDQ
11
D2_
MDQS
2
D1_
MDQ
16
D1_
MDQS
2
D1_
MDQ
01
GND
D2_
MDQ
28
D1_
MDQ
23
D1_
MDQ
14
D1_
MDQS
1
D2_
MDQS
3
D1_
MDQS
3
D1_
MDM
3
D1_
MDQ
26
D2_
MECC
0
D1_
MECC
1
D2_
MDQS
8
D1_
MDQS
8
D1_MA
15
D1_
MECC
2
D2_MA
15
D1_MA
14
D1_
MECC
3
D2_
MAPAR_
ERR
D1_MA
12
D1_
MAPAR_
ERR
D1_
MCKE
3
D2_MA
11
D1_MA
09
D1_MA
11
D1_
MCKE
2
D1_MA
08
D1_
MCKE
1
D2_
MCKE
1
D1_MA
05
GNDD2_MA
01
D2_MA
02
D2_
MCK
2
D1_
MCK
1
D2_
MCK
2
D2_
MCK
1
D2_
MCK
1
D1_
MCK
1
D1_
MCK
2
D1_
MCK
2
D2_
MDQS
8
1181312111098765432
A
B
C
D
E
F
G
H
J
K
L
M
N
T
14 15
P
R
U
V
16 17
DETAIL A
RSRV
_F1
RSRV
_F2
RSRV
_G1
RSRV
_G2
LDP
3
LDP
2
LAD
30
LWE
LAD
29
LAD
28
LAD
31
3
LWE
2
GND
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor6
Figure 4. 1295 BGA ball map diagram (detail view B)
LA
19
LAD
11
GNDLA
28
AVDD_
DDR
MVREF
LBCTL
LCS
5
LCS
0
LCS
1
LA
21
LA
22
LAD
04
SD_TX
03
LAD
07
LAD
06
LA
29
LA
20
LA
18
LAD
05
LAD
03
LA
26
LA
23
GND
LA
24
GND XGND
AVDD_
SRDS4
SD_RX
04
SD_RX
05
SD_RX
05
SGND
SGND
SD_RX
08
SD_RX
09
SD_RX
09
SD_RX
10
SD_RX
10
AVDD_
CC1 LALE AVDD_
SRDS1
AGND_
SRDS1
SD_
REF_
CLK1
SD_
REF_
CLK1
LCS
3
LCS
4
LWE
0
LCS
2
LWE
1
NC_
C19
NC_
C20
GND
GND
GND
GND
LCLK
1
LCLK
0
LAD
09
BVDD LGPL
0
LGPL
4
LGPL
2
GND
NC_
C26
NC_
C27
NC_
D27
SGND
SVDD
SD_RX
00
SD_RX
00
SD_RX
01
SD_RX
01
SGND
SVDD
SVDD SD_RX
03
SD_RX
03
SGND
XGND
SD_RX
02
SVDD
SD_RX
02
SGND SD_TX
04
XGND
BVDD LAD
08
BVDD LGPL
1
LGPL
5
NC_
E27
XGND SD_TX
03
XVDD XVDD SGND SVDD
LAD
12
BVDD GND LCS
06
BVDD GND SD_TX
01
SVDD
LA
25
LA
17
LCS
7
NC_
G27
XVDD SVDD
BVDD LGPL
3
NC_
H27
XGND XGND SD_RX
06
SD_RX
06
GND LAD
10
GND LDP
00
LA
16
LAD
02
SD_TX
06
XGND SGND SVDD
LA
27
BVDD LDP
1
BVDD LAD
00
XVDD SD_TX
07
SD_TX
07
SVDD SD_RX
07
SD_RX
07
VDD_PL VDD_PLGND VDD_PL VDD_PLGND GND LAD
01
SENSE-
GND_PL
02
SENSE-
VDD_PL
02
XVDD XGND SD_RX
08
SVDD SGND
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND XVDD XGND SD_TX
08
SD_TX
08
SVDD SGND
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL SD_TX
09
SD_TX
09
XVDD SGND SVDD
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND XGND XVDD SD_TX
10
SD_TX
10
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL XVDD XGND SVDD SGND
GND GND GND GNDVDD_CA VDD_PL VDD_PL VDD_PL GND AGND_
SRDS4
XVDD SGND
AVDD_
SRDS2
AGND_
SRDS2
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_
REF_
XGND SGND
GND GND GND GNDVDD_PL VDD_PL VDD_PL VDD_PL GND SD_
REF_
XGND XVDD SGND
SVDD
XVDD
SD_IMP_
CAL_RX
NC_
A27
SVDD SGND
NC_
B26
SGND SVDD SGND SVDD
SVDD SD_RX
04
SGND SVDD
SGND
XGND SD_TX
01
SD_TX
04
XVDD SD_TX
05
XVDD
SD_TX
00
XGND XGND SD_TX
05
SGND
SD_TX
00
SD_TX
02
SD_TX
02
XVDD XGND XVDD
LA
30
XVDD XGND XVDD SD_TX
06
GND XGND
XGND XVDD
XGND XGND XGND
XVDD XGND
XVDD XGND SGND SVDD
SD_TX
11
SD_TX
11
XVDD SD_RX
11
SD_RX
11
XGND XVDD SVDD
XGND XVDD SD_
REF_
CLK2
SD_
REF_
CLK2
3619 24 25 26 27 28 29 30 31 32 33 34 35
A
B
C
D
E
F
G
H
J
K
L
M
N
T
2322
P
R
U
V
2120
DETAIL B
RSRV
_U35
RSRV
_U32
RSRV
_A25
RSRV
_C32
RSRV
_D32
TEMP_
CATH-
ODE
TEMP_
ANODE
RSRV
_A21
RSRV
_L28
RSRV
_M28
RSRV
_N28
RSRV
_P28
LAD
27
CLK4
CLK4
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 7
Figure 5. 1295 BGA ball map diagram (detail view C)
D2_
MDQ
48
D1_
MDQ
54
D1_
MDQ
50
D2_
MDQ
56
D2_
MDQ
58
D2_
MDQS
6
D2_
MDQ
54
D2_
MDQS
7
D1_
MDQ
62
D1_
MDQ
59
D2_
MDQ
55
D2_
MDQ
61
D2_
MDQ
57
D2_
MDQ
63
D2_
MDQ
59
D1_
MDQ
56
D1_
MDQS
7
D1_
MDQ
58
D2_
MCK
0
D1_
MCK
0
D2_
MDIC
1
D2_
MCS
0
D1_
MDQ
33
D1_
MDQ
32
D2_
MODT
2
D2_
MODT
0
D1_
MDM
4
D1_
MODT
0
D2_
MODT
3
D2_
MDQ
37
D1_
MDQ
35
D2_
MDM
4
D2_
MDQ
32
D1_
MDQ
45
D1_
MDQ
44
D1_
MODT
1
D2_
MDQ
38
D1_
MDQS
5
D1_
MDM
5
D2_
MDQ
35
D2_
MDQ
34
D1_
MDQ
42
D2_
MDQ
45
D2_
MDQ
44
D1_
MDQ
53
D2_
MDM
5
D2_
MDQ
41
D2_
MDQ
40
D1_
MDQ
49
D1_
MDM
6
D2_
MDQ
52
D2_
MDQS
5
D2_
MDQ
46
D1_
MDQS
6
D1_
MCK
0
GND D1_
MCK
3
D1_
MCK
3
GVDD VDD_PL VDD_PL GND GND
GND GND GND GND
GND GVDD D1_
MBA
1
GND VDD_PL GND GND GND
VDD_PL GND GND
D2_
MAPAR_
OUT
D1_
MDIC
1
GVDD GND VDD_PL VDD_PL GND GND
GND GND GND GND
D2_
MRAS
GVDD GND GVDD GND VDD_PL GND GND GND
GND GND GND
GVDD D2_MA
13
GND GVDD D1_
MCS
0
VDD_PL VDD_PL GND GND
GND GND GND GND
GND GVDD D1_
MODT
2
GND GND VDD_PL GND GND GND
VDD_PL VDD_PL VDD_PL
D1_
MDQ
39
GND GVDD VDD_PL VDD_PL VDD_PL VDD_PL
GND GND GND GND
D2_
MODT
1
GVDD GND GVDD D1_
MCS
3
SENSE-
VDD_PL
1
SENSE-
GND_PL
1
GND GND GND
VDD_PL VDD_PL VDD_PL
GND D1_
MDQ
40
GVDD GND IRQ
08
IIC4_
SCL
NC_
AG15
GND
IRQ
06
D2_
MDQS
4
GVDD D1_
MDQS
5
GND GVDD GND IRQ
10
IIC1_
SCL
IRQ
01
IRQ
04
GVDD D2_
MDQ
39
GND D1_
MDQ
46
GVDD GND OVDD IRQ
05
OVDD IRQ
03
IRQ
00
EVT
0
OVDD
GND GVDD GND IRQ
09
IRQ
02
IIC3_
SCL
IRQ_
OUT
GND EVT
3
EVT
1
IO_
VSEL
2
GVDD GND D1_
MDQ
48
GVDD IRQ
11
GND IIC2_
SDA
IIC4_
SDA
OVDD SCAN_
MODE
IO_
VSEL
0
GVDD GND GVDD GND IRQ
07
IIC3_
SDA
IIC2_
SCL
EVT
4
GND IO_
VSEL
3
D2_
MDQ
53
GND D2_
MDQ
42
D2_
MDQ
43
GVDD D1_
MDQ
55
GND D1_
MDQ
51
GVDD IIC1_
SDA
GND EVT
2TDI OVDD
D2_
MDM
6
D2_
MDQ
49
GVDD D2_
MDM
7
GND D1_
MDQ
60
GVDD GND TDO OVDD
PORESET
IO_
VSEL
1
GVDD D2_
MDQ
60
GND D2_
MDQ
62
GVDD D1_
MDQ
61
D1_
MDQ
57
GND GVDD MDVAL GND GND
HRESET
D2_
MDQ
51
D2_
MDQS
7
OVDD RESET_
REQ POVDD
GVDD
AVDD_
CC3
D2_
MCK
3
D2_
MCK
3
D2_
MCK
0
GVDD GND D2_MA
00
D1_
MAPAR_
OUT
D1_MA
00
D2_
MBA
1
D2_MA
10
D2_
MBA
0
D2_
MDIC
0
D1_MA
10
D1_
MBA
0
D1_
MRAS
D2_
MWE
D2_
MCS
2
D1_
MDQ
36
D1_
MDQ
37
D1_
MWE
D1_
MCS
2
D2_
MCAS
D1_
MCAS
D1_
MDQS
4
D1_
MDQS
4
D2_
MCS
1
D2_
MCS
3
D1_
MDQ
38
D1_MA
13
D1_
MCS
1
D2_
MDQ
36
D1_
MDQ
34
D1_
MODT
3
D2_
MDQ
33
D2_
MDQS
4
D1_
MDQ
41
MSRCID
2
GND
D1_
MDQ
47
D1_
MDQ
43
D1_
MDQ
52
GVDD
D2_
MDQS
5
D2_
MDQ
47
D1_
MDQS
6
VID_
VDD_CA
VID_
VDD_CA
D2_
MDQS
6
TEST_
SEL2
D1_
MDQ
63
VID_
VDD_CA
D2_
MDQ
50
D1_
MDM
7
D1_
MDQS
7
VID_
VDD_CA
1181312111098765432
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AA
14 15
AC
AB
Y
W
16 17
DETAIL C
RSRV
_AG11
RSRV
_AG12
RSRV
_AH12
RSRV
_AH11
RSRV
_AK1
RSRV
_AK2
RSRV
_AL1
RSRV
_AL2
_CB3
_CB2
_CB1
_CB0
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor8
Figure 6. 1295 BGA ball map diagram (detail view D)
SD_RX
16
TMS
TMS
SDHC_
DAT
3
GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_TX
12
SD_TX
12
XGND SD_RX
12
SD_RX
12
SGND SVDD
GND GND GND GNDGND VDD_PL VDD_PL VDD_PL GND XGND SD_TX
13
SVDD
SGND
SD_RX
13
SD_RX
13
GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL SD1_IMP
_CAL_TX
XVDD SD_TX
14
SD_RX
14
SD_RX
14
SGND
GND GND GND GNDGND VDD_PL VDD_PL VDD_PL GND SD_TX
18
SD_TX
18
SD_TX
15
XGND SGND
SVDD
AVDD_
SRDS3
AGND_
SRDS3
GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL S1VDD XVDD
GND GND GND GNDVDD_PL VDD_PL VDD_PL VDD_PL GND SD_RX
18
XGND
SD_
REF_
CLK3
SD_
REF_
CLK3
SGND SVDD
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND SD_RX
18
SVDD
SGND
GND GND GND GNDVDD_PL VDD_PL VDD_PL SD_RX
19
SGNDSD_RX
19
SD1_IMP
_CAL_RX
SD_RX
16
SVDD SGND
DMA2_
DACK
0
GPIO
07
OVDD SDHC_
CMD
SD_TX
19
S1VDD RSRVX1VDD
SD_TX
19
IO_
VSEL
4
MSRCID
0
GPIO
04
GND SPI_
MISO
SD_PLL4
_TPD
GND
EMI2_
MDIO
EMI2_
MDC
MSRCID
1
DMA2_
DREQ
0
GPIO
05
OVDD SPI_CS
1
CVDD GND EMI1_
MDC
LVDD
GND CLK_
OUT
GPIO
06
GPIO
01
GND SPI_
CLK
LVDD
DMA1_
DACK
0
OVDD GPIO
00
SDHC_
CLK
GND LV DD EMI1_
MDIO
GND
TSEC_
1588_CLK
_IN
SDHC_
DAT
02
GND
GPIO
02
CKSTP_
OUT
RSRV
[29]
SPI_CS
3
GND EC1_
RXD
3
LVDD
OVDD
DMA1_
DDONE
00
GPIO
03
TMP_
DETECT RTC
SPI_CS
0
GND EC2_
GTX_
CLK
EC2_
RXD
2
LVDD EC1_
RXD
2
EC1_
RXD
1
EC1_
RXD
0
GND
DMA2_
DDONE
0
DMA1_
DREQ
0
GND SDHC_
DAT
0
CVDD EC2_
TXD
2
LV DD EC2_
RXD
1
EC2_
RXD
3
GND
EC1_
GTX_
CLK
EC1_
TXD
3
TRST ASLEEP TCK OVDD
SPI_CS
2
EC2_
TXD
1
EC2_
TX_EN
GND
EC1_
RX_DV
EC2_
RX_DV
EC1_
TXD
1
LVDD EC1_
TX_EN
AVDD_
PLAT
TEST_
SEL
GND SYSCLK
SDHC_
DAT
1
SPI_
MOSI
EC2_
TXD
0
EC2_
TXD
3
EC2_
RXD
0
EC2_
RX_CLK
EC1_
TXD
2
EC1_
TXD
0
GND
EC1_
RX_CLK
EC_XTRNL
_TX_STMP
1
EC_XTRNL
_TX_STMP
2
EC_XTRNL
_RX_STMP
2
TSEC_
1588_CLK_
OUT
TSEC_
1588_PULSE
_OUT1
TSEC_
1588_PULSE
_OUT2
EC1_
GTX_
CLK125
EC_XTRNL
_RX_STMP
1
TSEC_
1588_ALARM
_OUT2
TSEC_
1588_ALARM
_OUT1
TSEC_
1588_TRIG
_IN2
TSEC_
1588_TRIG
_IN1
SD_IMP_
CAL_TX
XVDD
SD_TX
13
XVDD
XGND
XGND SD_TX
14
SVDD
SD_TX
15
XVDD XVDD
XGND SD_RX
15
SD_RX
15
XGND
XGND XVDD
XVDD SD_TX
16
SD_TX
16
XVDD XGND
XGND SD_TX
17
SD_TX
17
SGND SVDD SD_RX
17
SD_RX
17
UART2_
CTS
UART2_
SOUT
UART2_
RTS
UART1_
SOUT
UART1_
RTS
UART2_
SIN
UART1_
CTS
UART1_
SIN
3619 24 25 26 27 28 29 30 31 32 33 34 35
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AA
2322
AC
AB
Y
W
2120
DETAIL D
XGND XVDD SGND SGND SVDD
CVDD
USB1_
VDD_
1P0
USB2_
VDD_
1P0
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB1_
AGND
USB2_
AGND
USB1_
VDD_
3P3
USB2_
_VDD_
3P3
USB2_
VDD_
3P3
USB2_
UID
USB2_
UID
USB1_
VDD_
3P3
USB_
CLKIN
USB1_
VBUS_
CLMP
USB1
_AGND
USB1_
AGND
USB2_
AGND
USB2_
UDM
USB1_
UDM
USB2_
VBUS_
CLMP
USB1_
VDD_1P8_
DECAP
USB2_
_DD_1P8_
DECAP
USB2_
AGND
USB2_
UDP
USB1_
AGND
USB1_
UDP
USB1_
IBIAS_
REXT
USB2_
IBIAS_
REXT
EC2_
GTX_
CLK125
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB2_
AGND
USB1_
AGND
EC_RX_
ER
VDD_
LL
VDD_
LP
LP_
TEMP_
DETECT
NC_
W27
AVDD_
FM
RSRV
_AD34
RSRV
_AD33
_AG29
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 9
1.2 Pinout list
This table provides the pinout listing for the 1295 FC-PBGA package by bus.
Table 1. Pins listed by bus
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
DDR SDRAM Memory interface 1
D1_MDQ00 Data A17 I/O GVDD —
D1_MDQ01 Data D17 I/O GVDD —
D1_MDQ02 Data C14 I/O GVDD —
D1_MDQ03 Data A14 I/O GVDD —
D1_MDQ04 Data C17 I/O GVDD —
D1_MDQ05 Data B17 I/O GVDD —
D1_MDQ06 Data A15 I/O GVDD —
D1_MDQ07 Data B15 I/O GVDD —
D1_MDQ08 Data D15 I/O GVDD —
D1_MDQ09 Data G15 I/O GVDD —
D1_MDQ10 Data E12 I/O GVDD —
D1_MDQ11 Data G12 I/O GVDD —
D1_MDQ12 Data F16 I/O GVDD —
D1_MDQ13 Data E15 I/O GVDD —
D1_MDQ14 Data E13 I/O GVDD —
D1_MDQ15 Data F13 I/O GVDD —
D1_MDQ16 Data C8 I/O GVDD —
D1_MDQ17 Data D12 I/O GVDD —
D1_MDQ18 Data E9 I/O GVDD —
D1_MDQ19 Data E10 I/O GVDD —
D1_MDQ20 Data C11 I/O GVDD —
D1_MDQ21 Data C10 I/O GVDD —
D1_MDQ22 Data E6 I/O GVDD —
D1_MDQ23 Data E7 I/O GVDD —
D1_MDQ24 Data F7 I/O GVDD —
D1_MDQ25 Data F11 I/O GVDD —
D1_MDQ26 Data H10 I/O GVDD —
D1_MDQ27 Data J10 I/O GVDD —
D1_MDQ28 Data F10 I/O GVDD —
D1_MDQ29 Data F8 I/O GVDD —
D1_MDQ30 Data H7 I/O GVDD —
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor10
D1_MDQ31 Data H9 I/O GVDD —
D1_MDQ32 Data AC7 I/O GVDD —
D1_MDQ33 Data AC6 I/O GVDD —
D1_MDQ34 Data AF6 I/O GVDD —
D1_MDQ35 Data AF7 I/O GVDD —
D1_MDQ36 Data AB5 I/O GVDD —
D1_MDQ37 Data AB6 I/O GVDD —
D1_MDQ38 Data AE5 I/O GVDD —
D1_MDQ39 Data AE6 I/O GVDD —
D1_MDQ40 Data AG5 I/O GVDD —
D1_MDQ41 Data AH9 I/O GVDD —
D1_MDQ42 Data AJ9 I/O GVDD —
D1_MDQ43 Data AJ10 I/O GVDD —
D1_MDQ44 Data AG8 I/O GVDD —
D1_MDQ45 Data AG7 I/O GVDD —
D1_MDQ46 Data AJ6 I/O GVDD —
D1_MDQ47 Data AJ7 I/O GVDD —
D1_MDQ48 Data AL9 I/O GVDD —
D1_MDQ49 Data AL8 I/O GVDD —
D1_MDQ50 Data AN10 I/O GVDD —
D1_MDQ51 Data AN11 I/O GVDD —
D1_MDQ52 Data AK8 I/O GVDD —
D1_MDQ53 Data AK7 I/O GVDD —
D1_MDQ54 Data AN7 I/O GVDD —
D1_MDQ55 Data AN8 I/O GVDD —
D1_MDQ56 Data AT9 I/O GVDD —
D1_MDQ57 Data AR10 I/O GVDD —
D1_MDQ58 Data AT13 I/O GVDD —
D1_MDQ59 Data AR13 I/O GVDD —
D1_MDQ60 Data AP9 I/O GVDD —
D1_MDQ61 Data AR9 I/O GVDD —
D1_MDQ62 Data AR12 I/O GVDD —
D1_MDQ63 Data AP12 I/O GVDD —
D1_MECC0 Error Correcting Code K9 I/O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 11
D1_MECC1 Error Correcting Code J5 I/O GVDD —
D1_MECC2 Error Correcting Code L10 I/O GVDD —
D1_MECC3 Error Correcting Code M10 I/O GVDD —
D1_MECC4 Error Correcting Code J8 I/O GVDD —
D1_MECC5 Error Correcting Code J7 I/O GVDD —
D1_MECC6 Error Correcting Code L7 I/O GVDD —
D1_MECC7 Error Correcting Code L9 I/O GVDD —
D1_MAPAR_ERR Address Parity Error N8 I GVDD 40
D1_MAPAR_OUT Address Parity Out Y7 O GVDD —
D1_MDM0 Data Mask A16 O GVDD —
D1_MDM1 Data Mask D14 O GVDD —
D1_MDM2 Data Mask D11 O GVDD —
D1_MDM3 Data Mask G11 O GVDD —
D1_MDM4 Data Mask AD7 O GVDD —
D1_MDM5 Data Mask AH8 O GVDD —
D1_MDM6 Data Mask AL11 O GVDD —
D1_MDM7 Data Mask AT10 O GVDD —
D1_MDM8 Data Mask K8 O GVDD —
D1_MDQS0 Data Strobe C16 I/O GVDD —
D1_MDQS1 Data Strobe G14 I/O GVDD —
D1_MDQS2 Data Strobe D9 I/O GVDD —
D1_MDQS3 Data Strobe G9 I/O GVDD —
D1_MDQS4 Data Strobe AD5 I/O GVDD —
D1_MDQS5 Data Strobe AH6 I/O GVDD —
D1_MDQS6 Data Strobe AM10 I/O GVDD —
D1_MDQS7 Data Strobe AT12 I/O GVDD —
D1_MDQS8 Data Strobe K6 I/O GVDD —
D1_MDQS0 Data Strobe B16 I/O GVDD —
D1_MDQS1 Data Strobe F14 I/O GVDD —
D1_MDQS2 Data Strobe D8 I/O GVDD —
D1_MDQS3 Data Strobe G8 I/O GVDD —
D1_MDQS4 Data Strobe AD4 I/O GVDD —
D1_MDQS5 Data Strobe AH5 I/O GVDD —
D1_MDQS6 Data Strobe AM9 I/O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor12
D1_MDQS7 Data Strobe AT11 I/O GVDD —
D1_MDQS8 Data Strobe K5 I/O GVDD —
D1_MBA0 Bank Select AA8 O GVDD —
D1_MBA1 Bank Select Y10 O GVDD —
D1_MBA2 Bank Select M8 O GVDD —
D1_MA00 Address Y9 O GVDD —
D1_MA01 Address U6 O GVDD —
D1_MA02 Address U7 O GVDD —
D1_MA03 Address U9 O GVDD —
D1_MA04 Address U10 O GVDD —
D1_MA05 Address T8 O GVDD —
D1_MA06 Address T9 O GVDD —
D1_MA07 Address R8 O GVDD —
D1_MA08 Address R7 O GVDD —
D1_MA09 Address P6 O GVDD —
D1_MA10 Address AA7 O GVDD —
D1_MA11 Address P7 O GVDD —
D1_MA12 Address N6 O GVDD —
D1_MA13 Address AE8 O GVDD —
D1_MA14 Address M7 O GVDD —
D1_MA15 Address L6 O GVDD —
D1_MWE Write Enable AB8 O GVDD —
D1_MRAS Row Address Strobe AA10 O GVDD —
D1_MCAS Column Address Strobe AC10 O GVDD —
D1_MCS0 Chip Select AC9 O GVDD —
D1_MCS1 Chip Select AE9 O GVDD —
D1_MCS2 Chip Select AB9 O GVDD —
D1_MCS3 Chip Select AF9 O GVDD —
D1_MCKE0 Clock Enable P10 O GVDD —
D1_MCKE1 Clock Enable R10 O GVDD —
D1_MCKE2 Clock Enable P9 O GVDD —
D1_MCKE3 Clock Enable N9 O GVDD —
D1_MCK0 Clock W6 O GVDD —
D1_MCK1 Clock V6 O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 13
D1_MCK2 Clock V8 O GVDD —
D1_MCK3 Clock W9 O GVDD —
D1_MCK0 Clock Complements W5 O GVDD —
D1_MCK1 Clock Complements V5 O GVDD —
D1_MCK2 Clock Complements V9 O GVDD —
D1_MCK3 Clock Complements W8 O GVDD —
D1_MODT0 On Die Termination AD10 O GVDD —
D1_MODT1 On Die Termination AG10 O GVDD —
D1_MODT2 On Die Termination AD8 O GVDD —
D1_MODT3 On Die Termination AF10 O GVDD —
D1_MDIC0 Driver Impedance Calibration T6 I/O GVDD 16
D1_MDIC1 Driver Impedance Calibration AA5 I/O GVDD 16
DDR SDRAM Memory interface 2
D2_MDQ00 Data C13 I/O GVDD —
D2_MDQ01 Data A12 I/O GVDD —
D2_MDQ02 Data B9 I/O GVDD —
D2_MDQ03 Data A8 I/O GVDD —
D2_MDQ04 Data A13 I/O GVDD —
D2_MDQ05 Data B13 I/O GVDD —
D2_MDQ06 Data B10 I/O GVDD —
D2_MDQ07 Data A9 I/O GVDD —
D2_MDQ08 Data A7 I/O GVDD —
D2_MDQ09 Data D6 I/O GVDD —
D2_MDQ10 Data A4 I/O GVDD —
D2_MDQ11 Data B4 I/O GVDD —
D2_MDQ12 Data C7 I/O GVDD —
D2_MDQ13 Data B7 I/O GVDD —
D2_MDQ14 Data C5 I/O GVDD —
D2_MDQ15 Data D5 I/O GVDD —
D2_MDQ16 Data B1 I/O GVDD —
D2_MDQ17 Data B3 I/O GVDD —
D2_MDQ18 Data D3 I/O GVDD —
D2_MDQ19 Data E1 I/O GVDD —
D2_MDQ20 Data A3 I/O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor14
D2_MDQ21 Data A2 I/O GVDD —
D2_MDQ22 Data D1 I/O GVDD —
D2_MDQ23 Data D2 I/O GVDD —
D2_MDQ24 Data F4 I/O GVDD —
D2_MDQ25 Data F5 I/O GVDD —
D2_MDQ26 Data H4 I/O GVDD —
D2_MDQ27 Data H6 I/O GVDD —
D2_MDQ28 Data E4 I/O GVDD —
D2_MDQ29 Data E3 I/O GVDD —
D2_MDQ30 Data H3 I/O GVDD —
D2_MDQ31 Data H1 I/O GVDD —
D2_MDQ32 Data AG4 I/O GVDD —
D2_MDQ33 Data AG2 I/O GVDD —
D2_MDQ34 Data AJ3 I/O GVDD —
D2_MDQ35 Data AJ1 I/O GVDD —
D2_MDQ36 Data AF4 I/O GVDD —
D2_MDQ37 Data AF3 I/O GVDD —
D2_MDQ38 Data AH1 I/O GVDD —
D2_MDQ39 Data AJ4 I/O GVDD —
D2_MDQ40 Data AL6 I/O GVDD —
D2_MDQ41 Data AL5 I/O GVDD —
D2_MDQ42 Data AN4 I/O GVDD —
D2_MDQ43 Data AN5 I/O GVDD —
D2_MDQ44 Data AK5 I/O GVDD —
D2_MDQ45 Data AK4 I/O GVDD —
D2_MDQ46 Data AM6 I/O GVDD —
D2_MDQ47 Data AM7 I/O GVDD —
D2_MDQ48 Data AN1 I/O GVDD —
D2_MDQ49 Data AP3 I/O GVDD —
D2_MDQ50 Data AT1 I/O GVDD —
D2_MDQ51 Data AT2 I/O GVDD —
D2_MDQ52 Data AM1 I/O GVDD —
D2_MDQ53 Data AN2 I/O GVDD —
D2_MDQ54 Data AR3 I/O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 15
D2_MDQ55 Data AT3 I/O GVDD —
D2_MDQ56 Data AP5 I/O GVDD —
D2_MDQ57 Data AT5 I/O GVDD —
D2_MDQ58 Data AP8 I/O GVDD —
D2_MDQ59 Data AT8 I/O GVDD —
D2_MDQ60 Data AR4 I/O GVDD —
D2_MDQ61 Data AT4 I/O GVDD —
D2_MDQ62 Data AR7 I/O GVDD —
D2_MDQ63 Data AT7 I/O GVDD —
D2_MECC0 Error Correcting Code J1 I/O GVDD —
D2_MECC1 Error Correcting Code K3 I/O GVDD —
D2_MECC2 Error Correcting Code M5 I/O GVDD —
D2_MECC3 Error Correcting Code N5 I/O GVDD —
D2_MECC4 Error Correcting Code J4 I/O GVDD —
D2_MECC5 Error Correcting Code J2 I/O GVDD —
D2_MECC6 Error Correcting Code L3 I/O GVDD —
D2_MECC7 Error Correcting Code L4 I/O GVDD —
D2_MAPAR_ERR Address Parity Error N2 I GVDD —
D2_MAPAR_OUT Address Parity Out Y1 O GVDD —
D2_MDM0 Data Mask B12 O GVDD —
D2_MDM1 Data Mask B6 O GVDD —
D2_MDM2 Data Mask C4 O GVDD —
D2_MDM3 Data Mask G3 O GVDD —
D2_MDM4 Data Mask AG1 O GVDD —
D2_MDM5 Data Mask AL3 O GVDD —
D2_MDM6 Data Mask AP2 O GVDD —
D2_MDM7 Data Mask AP6 O GVDD —
D2_MDM8 Data Mask K2 O GVDD —
D2_MDQS0 Data Strobe A10 I/O GVDD —
D2_MDQS1 Data Strobe A5 I/O GVDD —
D2_MDQS2 Data Strobe C2 I/O GVDD —
D2_MDQS3 Data Strobe G6 I/O GVDD —
D2_MDQS4 Data Strobe AH2 I/O GVDD —
D2_MDQS5 Data Strobe AM4 I/O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor16
D2_MDQS6 Data Strobe AR1 I/O GVDD —
D2_MDQS7 Data Strobe AR6 I/O GVDD —
D2_MDQS8 Data Strobe L1 I/O GVDD —
D2_MDQS0 Data Strobe A11 I/O GVDD —
D2_MDQS1 Data Strobe A6 I/O GVDD —
D2_MDQS2 Data Strobe C1 I/O GVDD —
D2_MDQS3 Data Strobe G5 I/O GVDD —
D2_MDQS4 Data Strobe AH3 I/O GVDD —
D2_MDQS5 Data Strobe AM3 I/O GVDD —
D2_MDQS6 Data Strobe AP1 I/O GVDD —
D2_MDQS7 Data Strobe AT6 I/O GVDD —
D2_MDQS8 Data Strobe K1 I/O GVDD —
D2_MBA0 Bank Select AA3 O GVDD —
D2_MBA1 Bank Select AA1 O GVDD —
D2_MBA2 Bank Select M1 O GVDD —
D2_MA00 Address Y4 O GVDD —
D2_MA01 Address U1 O GVDD —
D2_MA02 Address U4 O GVDD —
D2_MA03 Address T1 O GVDD —
D2_MA04 Address T2 O GVDD —
D2_MA05 Address T3 O GVDD —
D2_MA06 Address R1 O GVDD —
D2_MA07 Address R4 O GVDD —
D2_MA08 Address R2 O GVDD —
D2_MA09 Address P1 O GVDD —
D2_MA10 Address AA2 O GVDD —
D2_MA11 Address P3 O GVDD —
D2_MA12 Address N1 O GVDD —
D2_MA13 Address AC4 O GVDD —
D2_MA14 Address N3 O GVDD —
D2_MA15 Address M2 O GVDD —
D2_MWE Write Enable AB2 O GVDD —
D2_MRAS Row Address Strobe AB1 O GVDD —
D2_MCAS Column Address Strobe AC3 O GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 17
D2_MCS0 Chip Select AC1 O GVDD —
D2_MCS1 Chip Select AE1 O GVDD —
D2_MCS2 Chip Select AB3 O GVDD —
D2_MCS3 Chip Select AE2 O GVDD —
D2_MCKE0 Clock Enable R5 O GVDD —
D2_MCKE1 Clock Enable T5 O GVDD —
D2_MCKE2 Clock Enable P4 O GVDD —
D2_MCKE3 Clock Enable M4 O GVDD —
D2_MCK0 Clock W3 O GVDD —
D2_MCK1 Clock V3 O GVDD —
D2_MCK2 Clock V1 O GVDD —
D2_MCK3 Clock W2 O GVDD —
D2_MCK0 Clock Complements W4 O GVDD —
D2_MCK1 Clock Complements V4 O GVDD —
D2_MCK2 Clock Complements V2 O GVDD —
D2_MCK3 Clock Complements W1 O GVDD —
D2_MODT0 On Die Termination AD2 O GVDD —
D2_MODT1 On Die Termination AF1 O GVDD —
D2_MODT2 On Die Termination AD1 O GVDD —
D2_MODT3 On Die Termination AE3 O GVDD —
D2_MDIC0 Driver Impedance Calibration AA4 I/O GVDD 16
D2_MDIC1 Driver Impedance Calibration Y6 I/O GVDD 16
Local bus controller interface
LAD00 Muxed Data/Address K26 I/O BVDD 3
LAD01 Muxed Data/Address L26 I/O BVDD 3
LAD02 Muxed Data/Address J26 I/O BVDD 3
LAD03 Muxed Data/Address H25 I/O BVDD 3
LAD04 Muxed Data/Address F25 I/O BVDD 3
LAD05 Muxed Data/Address H24 I/O BVDD 3
LAD06 Muxed Data/Address G24 I/O BVDD 3
LAD07 Muxed Data/Address G23 I/O BVDD 3
LAD08 Muxed Data/Address E23 I/O BVDD 3
LAD09 Muxed Data/Address D23 I/O BVDD 3
LAD10 Muxed Data/Address J22 I/O BVDD 3
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor18
LAD11 Muxed Data/Address G22 I/O BVDD 3
LAD12 Muxed Data/Address F19 I/O BVDD 3
LAD13 Muxed Data/Address J18 I/O BVDD 3
LAD14 Muxed Data/Address K18 I/O BVDD 3
LAD15 Muxed Data/Address J17 I/O BVDD 3
LAD16 Muxed Data/Address J25 I/O BVDD 3
LAD17 Muxed Data/Address G25 I/O BVDD 3
LAD18 Muxed Data/Address H23 I/O BVDD 3,35
LAD19 Muxed Data/Address F22 I/O BVDD 3,35
LAD20 Muxed Data/Address H22 I/O BVDD 3,35
LAD21 Muxed Data/Address E21 I/O BVDD 3,35
LAD22 Muxed Data/Address F21 I/O BVDD 3,35
LAD23 Muxed Data/Address H21 I/O BVDD 3
LAD24 Muxed Data/Address K21 I/O BVDD 3
LAD25 Muxed Data/Address G20 I/O BVDD 3,35
LAD26 Muxed Data/Address J20 I/O BVDD 32
LAD27 Muxed Data/Address D26 I/O BVDD —
LAD28 Muxed Data/Address E18 I/O BVDD —
LAD29 Muxed Data/Address F18 I/O BVDD —
LAD30 Muxed Data/Address J15 I/O BVDD —
LAD31 Muxed Data/Address F17 I/O BVDD —
LDP0 Data Parity J24 I/O BVDD —
LDP1 Data Parity K23 I/O BVDD —
LDP2 Data Parity H17 I/O BVDD —
LDP3 Data Parity H16 I/O BVDD —
LA27 Address K20 O BVDD —
LA28 Address G19 O BVDD 35
LA29 Address H19 O BVDD 35
LA30 Address J19 O BVDD 35
LA31 Address G18 O BVDD 35
LCS0 Chip Selects D19 O BVDD 5
LCS1 Chip Selects D20 O BVDD 5
LCS2 Chip Selects E20 O BVDD 5
LCS3 Chip Selects D21 O BVDD 5
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 19
LCS4 Chip Selects D22 O BVDD 5
LCS5 Chip Selects B23 O BVDD 5
LCS6 Chip Selects F24 O BVDD 5
LCS7 Chip Selects G26 O BVDD 5
LWE0 Write Enable D24 O BVDD —
LWE1 Write Enable A24 O BVDD —
LWE2 Write Enable J16 O BVDD —
LWE3 Write Enable K15 O BVDD —
LBCTL Buffer Control C22 O BVDD —
LALE Address Latch Enable A23 I/O BVDD —
LGPL0/LFCLE UPM General Purpose Line 0/
LFCLE—FCM
B25 O BVDD 3, 4
LGPL1/LFALE UPM General Purpose Line 1/
LFALE—FCM
E25 O BVDD 3, 4
LGPL2/LOE/LFRE UPM General Purpose Line 2/
LOE_B—Output Enable
D25 O BVDD 3, 4
LGPL3/LFWP UPM General Purpose LIne 3/
LFWP_B—FCM
H26 O BVDD 3, 4
LGPL4/LGTA/LUPWAIT/LPBSE UPM General Purpose Line 4/
LGTA_B—FCM
C25 I/O BVDD 39
LGPL5 UPM General Purpose Line 5 /
Amux
E26 O BVDD 3, 4
LCLK0 Local Bus Clock C24 O BVDD —
LCLK1 Local Bus Clock C23 O BVDD —
DMA
DMA1_DREQ0/GPIO18 DMA1 Channel 0 Request AP21 I OVDD 26
DMA1_DACK0/GPIO19 DMA1 Channel 0 Acknowledge AL19 O OVDD 26
DMA1_DDONE0 DMA1 Channel 0 Done AN21 O OVDD 27
DMA2_DREQ0/GPIO20/ALT_MDVAL DMA2 Channel 0 Request AJ20 I OVDD 26
DMA2_DACK0/EVT7/ALT_MDSRCID0 DMA2 Channel 0 Acknowledge AG19 O OVDD 26
DMA2_DDONE0/EVT8/ALT_MDSRCID1 DMA2 Channel 0 Done AP20 O OVDD 26
USB Port 1
USB1_UDP USB1 PHY Data Plus AT27 I/O USB_VDD_
3P3 —
USB1_UDM USB1 PHY Data Minus AT26 I/O USB_VDD_
3P3 —
USB1_VBUS_CLMP USB1 PHY VBUS Divided Signal AK25 I USB_VDD_
3P3 38
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor20
USB1_UID USB1 PHY ID Detect AK24 I USB1_VDD
_1P8
_DECAP
—
USB1_DRVVBUS/GPIO04 USB1 5V Supply Enable AH21 O OVDD 26,38
USB1_PWRFAULT/GPIO05 USB1 Power Fault AJ21 I OVDD 26,38
USB_CLKIN USB PHY Clock Input AM24 I OVDD —
USB Port 2
USB2_UDP USB2 PHY Data Plus AP27 I/O USB_VDD_
3P3 —
USB2_UDM USB2 PHY Data Minus AP26 I/O USB_VDD_
3P3 —
USB2_VBUS_CLMP USB2 PHY VBUS Divided Signal AK26 I USB_VDD_
3P3 38
USB2_UID USB2 PHY ID Detect AK27 I USB2_VDD
_1P8
_DECAP
—
USB2_DRVVBUS/GPIO06 USB2 5V Supply Enable AK21 O OVDD 26,38
USB2_PWRFAULT/GPIO07 USB2 Power Fault AG20 O OVDD 26,38
Programmable Interrupt controller
IRQ00 External Interrupts AJ16 I OVDD —
IRQ01 External Interrupts AH16 I OVDD —
IRQ02 External Interrupts AK12 I OVDD —
IRQ03/GPIO21 External Interrupts AJ15 I OVDD 26
IRQ04/GPIO22 External Interrupts AH17 I OVDD 26
IRQ05/GPIO23 External Interrupts AJ13 I OVDD 26
IRQ06/GPIO24 External Interrupts AG17 I OVDD 26
IRQ07/GPIO25 External Interrupts AM13 I OVDD 26
IRQ08/GPIO26 External Interrupts AG13 I OVDD 26
IRQ09/GPIO27 External Interrupts AK11 I OVDD 26
IRQ10/GPIO28 External Interrupts AH14 I OVDD 26
IRQ11/GPIO29 External Interrupts AL12 I OVDD 26
IRQ_OUT/EVT9 Interrupt Output AK14 O OVDD 1, 2, 26
Trust
TMP_DETECT Tamper Detect AN19 I OVDD 27
LP_TMP_DETECT Low Power Tamper Detect AE28 I VDD_LP —
eSDHC
SDHC_CMD Command/Response AG23 I/O CVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 21
SDHC_DAT0 Data AP24 I/O CVDD —
SDHC_DAT1 Data AT24 I/O CVDD —
SDHC_DAT2 Data AM23 I/O CVDD —
SDHC_DAT3 Data AG22 I/O CVDD —
SDHC_DAT4/SPI_CS0 Data AN29 I/O CVDD 26, 31
SDHC_DAT5/SPI_CS1 Data AJ28 I/O CVDD 26, 31
SDHC_DAT6/SPI_CS2 Data AR29 I/O CVDD 26, 31
SDHC_DAT7/SPI_CS3 Data AM29 I/O CVDD 26, 31
SDHC_CLK Host to Card Clock AL23 O CVDD —
SDHC_CD/IIC3_SCL/GPIO16 Card Detection AK13 I OVDD 26,27,31
SDHC_WP/IIC3_SDA/GPIO17 Card Write Protection AM14 I OVDD 26,27,31
eSPI
SPI_MOSI Master Out Slave In AT29 I/O CVDD —
SPI_MISO Master In Slave Out AH28 I CVDD —
SPI_CLK eSPI clock AK29 O CVDD —
SPI_CS0/SDHC_DAT4 eSPI chip select AN29 O CVDD 26
SPI_CS1/SDHC_DAT5 eSPI chip select AJ28 O CVDD 26
SPI_CS2/SDHC_DAT6 eSPI chip select AR29 O CVDD 26
SPI_CS3/SDHC_DAT7 eSPI chip select AM29 O CVDD 26
IEEE 1588
TSEC_1588_CLK_IN Clock In AL35 I LVDD —
TSEC_1588_TRIG_IN1 Trigger In 1 AL36 I LVDD —
TSEC_1588_TRIG_IN2/EC1_RX_ER Trigger In 2 AK36 I LVDD —
TSEC_1588_ALARM_OUT1 Alarm Out 1 AJ36 O LVDD —
TSEC_1588_ALARM_OUT2/EC1_COL/GPIO30 Alarm Out 2 AK35 O LVDD 26
TSEC_1588_CLK_OUT Clock Out AM30 O LVDD —
TSEC_1588_PULSE_OUT1 Pulse Out1 AL30 O LVDD —
TSEC_1588_PULSE_OUT2/EC1_CRS/GPIO31 Pulse Out2 AJ34 O LVDD 26
Ethernet Management interface 1
EMI1_MDC Management Data Clock AJ33 O LVDD —
EMI1_MDIO Management Data In/Out AL32 I/O LVDD —
Ethernet Management interface 2
EMI2_MDC Management Data Clock AK30 O 1.2 V 2, 18, 22
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor22
EMI2_MDIO Management Data In/Out AJ30 I/O 1.2 V 2, 18, 22
Ethernet Reference Clock
EC1_GTX_CLK125/
EC1_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
AK34 I LVDD 27
EC2_GTX_CLK125/
EC2_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
AL33 I LVDD 27
Ethernet External Timestamping
EC_XTRNL_TX_STMP1 External Timestamp Transmit 1 AM31 I LVDD —
EC_XTRNL_RX_STMP1 External Timestamp Receive 1 AK32 I LVDD —
EC_XTRNL_TX_STMP2/EC2_COL External Timestamp Transmit 2 AJ31 I LVDD —
EC_XTRNL_RX_STMP2/EC2_CRS External Timestamp Receive 2 AK31 I LVDD —
Three-Speed Ethernet controller 1
EC1_TXD3 Transmit Data AP36 O LVDD 35
EC1_TXD2 Transmit Data AT34 O LVDD 35
EC1_TXD1 Transmit Data AR34 O LVDD 35
EC1_TXD0 Transmit Data AT35 O LVDD 35
EC1_TX_EN Transmit Enable AR36 O LVDD 15
EC1_GTX_CLK/
EC1_TX_ER
Transmit Clock Out (RGMII)
Transmit Error (MII)
AP35 O LVDD 26
EC1_RXD3 Receive Data AM33 I LVDD 27
EC1_RXD2 Receive Data AN34 I LVDD 27
EC1_RXD1 Receive Data AN35 I LVDD 27
EC1_RXD0 Receive Data AN36 I LVDD 27
EC1_RX_DV Receive Data Valid AM34 I LVDD 27
EC1_RX_CLK Receive Clock AM36 I LVDD 27
EC1_RX_ER/TSEC_1588_TRIG_IN2 Receive Error (MII) AK36 I LVDD —
EC1_COL/GPIO30/TSEC_1588_ALARM_OUT2 Collision Detect (MII) AK35 O LVDD 26
EC1_CRS/GPIO31/TSEC_1588_PULSE_OUT2 Carrier Sense (MII) AJ34 O LVDD 26
Three-Speed Ethernet controller 2
EC2_TXD3 Transmit Data AT31 O LVDD 35
EC2_TXD2 Transmit Data AP30 O LVDD 35
EC2_TXD1 Transmit Data AR30 O LVDD 35
EC2_TXD0 Transmit Data AT30 O LVDD 35
EC2_TX_EN Transmit Enable AR31 O LVDD 15
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 23
EC2_GTX_CLK/
EC2_TX_ER
Transmit Clock Out (RGMII)
Transmit Error (MII)
AN31 O LVDD 26
EC2_RXD3 Receive Data AP33 I LVDD 27
EC2_RXD2 Receive Data AN32 I LVDD 27
EC2_RXD1 Receive Data AP32 I LVDD 26, 27
EC2_RXD0 Receive Data AT32 I LVDD 26, 27
EC2_RX_DV Receive Data Valid AR33 I LVDD 27
EC2_RX_CLK Receive Clock AT33 I LVDD 27
EC2_RX_ER Receive Error (MII) AH29 I LVDD —
EC2_COL/EC_XTRNL_TX_STMP2 Collision Detect (MII) AJ31 O LVDD 26
EC2_CRS/EC_XTRNL_RX_STMP2 Carrier Sense (MII) AK31 O LVDD 26
UART
UART1_SOUT/GPIO8 Transmit Data AL22 O OVDD 26
UART2_SOUT/GPIO9 Transmit Data AJ22 O OVDD 26
UART1_SIN/GPIO10 Receive Data AR23 I OVDD 26
UART2_SIN/GPIO11 Receive Data AN23 I OVDD 26
UART1_RTS/UART3_SOUT/GPIO12 Ready to Send AM22 O OVDD 26
UART2_RTS/UART4_SOUT/GPIO13 Ready to Send AK23 O OVDD 26
UART1_CTS/UART3_SIN/GPIO14 Clear to Send AP22 I OVDD 26
UART2_CTS/UART4_SIN/GPIO15 Clear to Send AH23 I OVDD 26
I2C interface
IIC1_SCL Serial Clock AH15 I/O OVDD 2, 14
IIC1_SDA Serial Data AN14 I/O OVDD 2, 14
IIC2_SCL Serial Clock AM15 I/O OVDD 2, 14
IIC2_SDA Serial Data AL14 I/O OVDD 2, 14
IIC3_SCL/SDHC_CD/GPIO16 Serial Clock AK13 I/O OVDD 2, 14, 27
IIC3_SDA/SDHC_WP/GPIO17 Serial Data AM14 I/O OVDD 2, 14, 27
IIC4_SCL/EVT5Serial Clock AG14 I/O OVDD 2, 14
IIC4_SDA/EVT6 Serial Data AL15 I/O OVDD 2, 14
SerDes (x20) PCIe, Aurora, 10GE, 1GE, SATA
SD_TX19 Transmit Data (positive) AG25 O XVDD —
SD_TX18 Transmit Data (positive) AB28 O XVDD —
SD_TX17 Transmit Data (positive) AG31 O XVDD —
SD_TX16 Transmit Data (positive) AE31 O XVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor24
SD_TX15 Transmit Data (positive) AB33 O XVDD —
SD_TX14 Transmit Data (positive) AA31 O XVDD —
SD_TX13 Transmit Data (positive) Y29 O XVDD —
SD_TX12 Transmit Data (positive) W31 O XVDD —
SD_TX11 Transmit Data (positive) T30 O XVDD —
SD_TX10 Transmit Data (positive) P31 O XVDD —
SD_TX09 Transmit Data (positive) N33 O XVDD —
SD_TX08 Transmit Data (positive) M31 O XVDD —
SD_TX07 Transmit Data (positive) K31 O XVDD —
SD_TX06 Transmit Data (positive) J33 O XVDD —
SD_TX05 Transmit Data (positive) G33 O XVDD —
SD_TX04 Transmit Data (positive) D34 O XVDD —
SD_TX03 Transmit Data (positive) F31 O XVDD —
SD_TX02 Transmit Data (positive) H30 O XVDD —
SD_TX01 Transmit Data (positive) F29 O XVDD —
SD_TX00 Transmit Data (positive) H28 O XVDD —
SD_TX19 Transmit Data (negative) AG26 O XVDD —
SD_TX18 Transmit Data (negative) AB29 O XVDD —
SD_TX17 Transmit Data (negative) AG32 O XVDD —
SD_TX16 Transmit Data (negative) AE32 O XVDD —
SD_TX15 Transmit Data (negative) AB34 O XVDD —
SD_TX14 Transmit Data (negative) AA32 O XVDD —
SD_TX13 Transmit Data (negative) Y30 O XVDD —
SD_TX12 Transmit Data (negative) W32 O XVDD —
SD_TX11 Transmit Data (negative) T31 O XVDD —
SD_TX10 Transmit Data (negative) P32 O XVDD —
SD_TX09 Transmit Data (negative) N34 O XVDD —
SD_TX08 Transmit Data (negative) M32 O XVDD —
SD_TX07 Transmit Data (negative) K32 O XVDD —
SD_TX06 Transmit Data (negative) J34 O XVDD —
SD_TX05 Transmit Data (negative) F33 O XVDD —
SD_TX04 Transmit Data (negative) E34 O XVDD —
SD_TX03 Transmit Data (negative) E31 O XVDD —
SD_TX02 Transmit Data (negative) G30 O XVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 25
SD_TX01 Transmit Data (negative) E29 O XVDD —
SD_TX00 Transmit Data (negative) G28 O XVDD —
SD_RX19 Receive Data (positive) AF27 I XVDD —
SD_RX18 Receive Data (positive) AD29 I XVDD —
SD_RX17 Receive Data (positive) AG36 I XVDD —
SD_RX16 Receive Data (positive) AF34 I XVDD —
SD_RX15 Receive Data (positive) AC36 I XVDD —
SD_RX14 Receive Data (positive) AA36 I XVDD —
SD_RX13 Receive Data (positive) Y34 I XVDD —
SD_RX12 Receive Data (positive) W36 I XVDD —
SD_RX11 Receive Data (positive) T34 I XVDD —
SD_RX10 Receive Data (positive) P36 I XVDD —
SD_RX09 Receive Data (positive) M36 I XVDD —
SD_RX08 Receive Data (positive) L34 I XVDD —
SD_RX07 Receive Data (positive) K36 I XVDD —
SD_RX06 Receive Data (positive) H36 I XVDD —
SD_RX05 Receive Data (positive) F36 I XVDD —
SD_RX04 Receive Data (positive) D36 I XVDD —
SD_RX03 Receive Data (positive) A31 I XVDD —
SD_RX02 Receive Data (positive) C30 I XVDD —
SD_RX01 Receive Data (positive) A29 I XVDD —
SD_RX00 Receive Data (positive) C28 I XVDD —
SD_RX19 Receive Data (negative) AF28 I XVDD —
SD_RX18 Receive Data (negative) AE29 I XVDD —
SD_RX17 Receive Data (negative) AG35 I XVDD —
SD_RX16 Receive Data (negative) AF33 I XVDD —
SD_RX15 Receive Data (negative) AC35 I XVDD —
SD_RX14 Receive Data (negative) AA35 I XVDD —
SD_RX13 Receive Data (negative) Y33 I XVDD —
SD_RX12 Receive Data (negative) W35 I XVDD —
SD_RX11 Receive Data (negative) T33 I XVDD —
SD_RX10 Receive Data (negative) P35 I XVDD —
SD_RX09 Receive Data (negative) M35 I XVDD —
SD_RX08 Receive Data (negative) L33 I XVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor26
SD_RX07 Receive Data (negative) K35 I XVDD —
SD_RX06 Receive Data (negative) H35 I XVDD —
SD_RX05 Receive Data (negative) F35 I XVDD —
SD_RX04 Receive Data (negative) C36 I XVDD —
SD_RX03 Receive Data (negative) B31 I XVDD —
SD_RX02 Receive Data (negative) D30 I XVDD —
SD_RX01 Receive Data (negative) B29 I XVDD —
SD_RX00 Receive Data (negative) D28 I XVDD —
SD_REF_CLK1 SerDes Bank 1 PLL Reference
Clock
A35 I XVDD —
SD_REF_CLK1 SerDes Bank 1 PLL Reference
Clock Complement
B35 I XVDD —
SD_REF_CLK2 SerDes Bank 2 PLL Reference
Clock
V34 I XVDD —
SD_REF_CLK2 SerDes Bank 2 PLL Reference
Clock Complement
V33 I XVDD —
SD_REF_CLK3 SerDes Bank 3 PLL Reference
Clock
AC32 I XVDD —
SD_REF_CLK3 SerDes Bank 3 PLL Reference
Clock Complement
AC31 I XVDD —
SD_REF_CLK4 SerDes Bank 4 PLL Reference
Clock
U28 I XVDD —
SD_REF_CLK4 SerDes Bank 4 PLL Reference
Clock Complement
V28 I XVDD —
General-Purpose Input/Output
GPIO00 General Purpose Input / Output AL21 I/O OVDD —
GPIO01 General Purpose Input / Output AK22 I/O OVDD —
GPIO02 General Purpose Input / Output AM20 I/O OVDD —
GPIO03 General Purpose Input / Output AN20 I/O OVDD —
GPIO04/USB1_DRVVBUS General Purpose Input / Output AH21 I/O OVDD —
GPIO05/USB1_PWRFAULT General Purpose Input / Output AJ21 I/O OVDD —
GPIO06/USB2_DRVVBUS General Purpose Input / Output AK21 I/O OVDD —
GPIO07/USB2_PWRFAULT General Purpose Input / Output AG20 I/O OVDD —
GPIO08/UART1_SOUT General Purpose Input / Output AL22 I/O OVDD —
GPIO09/UART2_SOUT General Purpose Input / Output AJ22 I/O OVDD —
GPIO10/UART1_SIN General Purpose Input / Output AR23 I/O OVDD —
GPIO11/UART2_SIN General Purpose Input / Output AN23 I/O OVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 27
GPIO12/UART1_RTS/UART3_SOUT General Purpose Input / Output AM22 I/O OVDD —
GPIO13/UART2_RTS/UART4_SOUT General Purpose Input / Output AK23 I/O OVDD —
GPIO14/UART1_CTS/UART3_SIN General Purpose Input / Output AP22 I/O OVDD —
GPIO15/UART2_CTS/UART4_SIN General Purpose Input / Output AH23 I/O OVDD —
GPIO16/IIC3_SCL/SDHC_CD General Purpose Input / Output AK13 I/O OVDD 27
GPIO17/IIC3_SDA/SDHC_WP General Purpose Input / Output AM14 I/O OVDD 27
GPIO18/DMA1_DREQ0 General Purpose Input / Output AP21 I/O OVDD —
GPIO19/DMA1_DACK0 General Purpose Input / Output AL19 I/O OVDD —
GPIO20/DMA2_DREQ0/ALT_MDVAL General Purpose Input / Output AJ20 I/O OVDD —
GPIO21/IRQ3 General Purpose Input / Output AJ15 I/O OVDD —
GPIO22/IRQ4 General Purpose Input / Output AH17 I/O OVDD —
GPIO23/IRQ5 General Purpose Input / Output AJ13 I/O OVDD —
GPIO24/IRQ6 General Purpose Input / Output AG17 I/O OVDD —
GPIO25/IRQ7 General Purpose Input / Output AM13 I/O OVDD —
GPIO26/IRQ8 General Purpose Input / Output AG13 I/O OVDD —
GPIO27/IRQ9 General Purpose Input / Output AK11 I/O OVDD —
GPIO28/IRQ10 General Purpose Input / Output AH14 I/O OVDD —
GPIO29/IRQ11 General Purpose Input / Output AL12 I/O OVDD —
GPIO30/TSEC_1588_ALARM_OUT2/EC1_COL General Purpose Input / Output AK35 I/O LVDD 25
GPIO31/TSEC_1588_PULSE_OUT2/EC1_CRS General Purpose Input / Output AJ34 I/O LVDD 25
System Control
PORESET Power On Reset AP17 I OVDD —
HRESET Hard Reset AR17 I/O OVDD 1, 2
RESET_REQ Reset Request AT16 O OVDD 35
CKSTP_OUT Checkstop Out AM19 O OVDD 1, 2
Debug
EVT0 Event 0 AJ17 I/O OVDD 20
EVT1 Event 1 AK17 I/O OVDD —
EVT2 Event 2 AN16 I/O OVDD —
EVT3 Event 3 AK16 I/O OVDD —
EVT4 Event 4 AM16 I/O OVDD —
EVT5/IIC4_SCL Event 5 AG14 I/O OVDD —
EVT6/IIC4_SDA Event 6 AL15 I/O OVDD —
EVT7/DMA2_DACK0/ALT_MSRCID0 Event 7 AG19 I/O OVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor28
EVT8/DMA2_DDONE0/ALT_MSRCID1 Event 8 AP20 I/O OVDD —
EVT9/IRQ_OUT Event 9 AK14 I/O OVDD —
MDVAL Debug Data Valid AR15 O OVDD —
MSRCID0 Debug Source ID 0 AH20 O OVDD 4,20,35
MSRCID1 Debug Source ID 1 AJ19 O OVDD —
MSRCID2 Debug Source ID 2 AH18 O OVDD —
ALT_MDVAL/DMA2_DREQ0/GPIO20 Alternate Debug Data Valid AJ20 O OVDD 26
ALT_MSRCID0/DMA2_DACK0/EVT7 Alternate Debug Source ID 0 AG19 O OVDD 26
ALT_MSRCID1/DMA2_DDONE0/EVT8 Alternate Debug Source ID 1 AP20 O OVDD 26
CLK_OUT Clock Out AK20 O OVDD 6
Clock
RTC Real Time Clock AN24 I OVDD —
SYSCLK System Clock AT23 I OVDD —
JTAG
TCK Test Clock AR22 I OVDD —
TDI Test Data In AN17 I OVDD 7
TDO Test Data Out AP15 O OVDD 6
TMS Test Mode Select AR20 I OVDD 7
TRST Test Reset AR19 I OVDD 7
DFT
SCAN_MODE Scan Mode AL17 I OVDD 12
TEST_SEL Test Mode Select AT21 I OVDD 28
TEST_SEL2 Test Mode Select 2 AP11 I OVDD 44
Power Management
ASLEEP Asleep AR21 O OVDD 35
Input/Output Voltage Select
IO_VSEL0 I/O Voltage Select AL18 I OVDD 30
IO_VSEL1 I/O Voltage Select AP18 I OVDD 30
IO_VSEL2 I/O Voltage Select AK18 I OVDD 30
IO_VSEL3 I/O Voltage Select AM18 I OVDD 30
IO_VSEL4 I/O Voltage Select AH19 I OVDD 30
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 29
Core Voltage ID Signals
VID_VDD_CA_CB0 Core voltage ID 0 AT14 O OVDD 42
VID_VDD_CA_CB1 Core voltage ID 1 AP14 O OVDD 42
VID_VDD_CA_CB2 Core voltage ID 2 AN13 O OVDD 42
VID_VDD_CA_CB3 Core voltage ID 3 AM12 O OVDD 42
Power and Ground Signals
GND Ground C3 — — —
GND Ground B5 — — —
GND Ground F3 — — —
GND Ground E5 — — —
GND Ground D7 — — —
GND Ground C9 — — —
GND Ground B11 — — —
GND Ground J3 — — —
GND Ground H5 — — —
GND Ground G7 — — —
GND Ground G17 — — —
GND Ground F9 — — —
GND Ground E11 — — —
GND Ground D13 — — —
GND Ground C15 — — —
GND Ground K19 — — —
GND Ground B20 — — —
GND Ground B22 — — —
GND Ground E19 — — —
GND Ground L22 — — —
GND Ground J23 — — —
GND Ground A22 — — —
GND Ground L20 — — —
GND Ground A26 — — —
GND Ground A18 — — —
GND Ground E17 — — —
GND Ground F23 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor30
GND Ground J27 — — —
GND Ground F27 — — —
GND Ground G21 — — —
GND Ground K25 — — —
GND Ground B18 — — —
GND Ground L18 — — —
GND Ground J21 — — —
GND Ground M27 — — —
GND Ground G13 — — —
GND Ground F15 — — —
GND Ground H11 — — —
GND Ground J9 — — —
GND Ground K7 — — —
GND Ground L5 — — —
GND Ground M3 — — —
GND Ground R3 — — —
GND Ground P5 — — —
GND Ground N7 — — —
GND Ground M9 — — —
GND Ground V25 — — —
GND Ground R9 — — —
GND Ground T7 — — —
GND Ground U5 — — —
GND Ground U3 — — —
GND Ground Y3 — — —
GND Ground Y5 — — —
GND Ground W7 — — —
GND Ground V10 — — —
GND Ground AA9 — — —
GND Ground AB7 — — —
GND Ground AC5 — — —
GND Ground AD3 — — —
GND Ground AD9 — — —
GND Ground AE7 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 31
GND Ground AF5 — — —
GND Ground AG3 — — —
GND Ground AG9 — — —
GND Ground AH7 — — —
GND Ground AJ5 — — —
GND Ground AK3 — — —
GND Ground AN3 — — —
GND Ground AM5 — — —
GND Ground AL7 — — —
GND Ground AK9 — — —
GND Ground AJ11 — — —
GND Ground AH13 — — —
GND Ground AR5 — — —
GND Ground AP7 — — —
GND Ground AN9 — — —
GND Ground AM11 — — —
GND Ground AL13 — — —
GND Ground AK15 — — —
GND Ground AG18 — — —
GND Ground AR11 — — —
GND Ground AP13 — — —
GND Ground AN15 — — —
GND Ground AM17 — — —
GND Ground AK19 — — —
GND Ground AF13 — — —
GND Ground AR18 — — —
GND Ground AB27 — — —
GND Ground AP19 — — —
GND Ground AH22 — — —
GND Ground AM21 — — —
GND Ground AL29 — — —
GND Ground AR16 — — —
GND Ground AT22 — — —
GND Ground AP23 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor32
GND Ground AR32 — — —
GND Ground AK28 — — —
GND Ground AE27 — — —
GND Ground L16 — — —
GND Ground AP34 — — —
GND Ground AJ32 — — —
GND Ground AN30 — — —
GND Ground AH34 — — —
GND Ground AT36 — — —
GND Ground AL34 — — —
GND Ground AM32 — — —
GND Ground AE26 — — —
GND Ground AC26 — — —
GND Ground AA26 — — —
GND Ground W26 — — —
GND Ground U26 — — —
GND Ground R26 — — —
GND Ground N26 — — —
GND Ground M11 — — —
GND Ground P11 — — —
GND Ground T11 — — —
GND Ground V11 — — —
GND Ground Y11 — — —
GND Ground AB11 — — —
GND Ground AD11 — — —
GND Ground AE12 — — —
GND Ground AC12 — — —
GND Ground AA12 — — —
GND Ground W12 — — —
GND Ground U12 — — —
GND Ground R12 — — —
GND Ground N12 — — —
GND Ground M13 — — —
GND Ground P13 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 33
GND Ground T13 — — —
GND Ground V13 — — —
GND Ground Y13 — — —
GND Ground AB13 — — —
GND Ground AD13 — — —
GND Ground AE14 — — —
GND Ground AC14 — — —
GND Ground AA14 — — —
GND Ground W14 — — —
GND Ground U14 — — —
GND Ground R14 — — —
GND Ground N14 — — —
GND Ground L14 — — —
GND Ground M15 — — —
GND Ground P15 — — —
GND Ground T15 — — —
GND Ground V15 — — —
GND Ground Y15 — — —
GND Ground AB15 — — —
GND Ground AD15 — — —
GND Ground AF15 — — —
GND Ground W16 — — —
GND Ground AC16 — — —
GND Ground AA16 — — —
GND Ground AE16 — — —
GND Ground U16 — — —
GND Ground R16 — — —
GND Ground N16 — — —
GND Ground M17 — — —
GND Ground P17 — — —
GND Ground T17 — — —
GND Ground N18 — — —
GND Ground R18 — — —
GND Ground U18 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor34
GND Ground Y17 — — —
GND Ground AB17 — — —
GND Ground AD17 — — —
GND Ground AF17 — — —
GND Ground W18 — — —
GND Ground AC18 — — —
GND Ground AA18 — — —
GND Ground AE18 — — —
GND Ground AF19 — — —
GND Ground AD19 — — —
GND Ground AB19 — — —
GND Ground Y19 — — —
GND Ground V19 — — —
GND Ground T19 — — —
GND Ground P19 — — —
GND Ground M19 — — —
GND Ground N20 — — —
GND Ground R20 — — —
GND Ground U20 — — —
GND Ground AE20 — — —
GND Ground AA20 — — —
GND Ground AC20 — — —
GND Ground W20 — — —
GND Ground AF21 — — —
GND Ground AD21 — — —
GND Ground AB21 — — —
GND Ground Y21 — — —
GND Ground V21 — — —
GND Ground T21 — — —
GND Ground P21 — — —
GND Ground M21 — — —
GND Ground AE22 — — —
GND Ground AC22 — — —
GND Ground AA22 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 35
GND Ground W22 — — —
GND Ground U22 — — —
GND Ground R22 — — —
GND Ground N22 — — —
GND Ground AF23 — — —
GND Ground AD23 — — —
GND Ground AB23 — — —
GND Ground Y23 — — —
GND Ground V23 — — —
GND Ground T23 — — —
GND Ground P23 — — —
GND Ground M23 — — —
GND Ground L24 — — —
GND Ground N24 — — —
GND Ground R24 — — —
GND Ground U24 — — —
GND Ground W24 — — —
GND Ground AA24 — — —
GND Ground AC24 — — —
GND Ground AE24 — — —
GND Ground AF25 — — —
GND Ground AD25 — — —
GND Ground AB25 — — —
GND Ground Y25 — — —
GND Ground P27 — — —
GND Ground V17 — — —
GND Ground T25 — — —
GND Ground P25 — — —
GND Ground M25 — — —
GND Ground T27 — — —
GND Ground V27 — — —
GND Ground Y27 — — —
GND Ground AD27 — — —
GND Ground L12 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor36
GND Ground AG16 — — —
GND Ground W15 — — —
GND Ground W19 — — —
GND Ground AA19 — — —
GND Ground Y20 — — —
GND Ground AB14 — — —
GND Ground AA21 — — —
GND Ground Y16 — — —
GND Ground AA15 — — —
GND Ground AC15 — — —
GND Ground AA17 — — —
GND Ground AC17 — — —
GND Ground W17 — — —
GND Ground Y18 — — —
GND Ground AB18 — — —
GND Ground AB16 — — —
GND Ground AC19 — — —
GND Ground AB20 — — —
XGND SerDes Transceiver GND AA30 — — —
XGND SerDes Transceiver GND AB32 — — —
XGND SerDes Transceiver GND AC30 — — —
XGND SerDes Transceiver GND AC34 — — —
XGND SerDes Transceiver GND AD30 — — —
XGND SerDes Transceiver GND AD31 — — —
XGND SerDes Transceiver GND AF32 — — —
XGND SerDes Transceiver GND AG30 — — —
XGND SerDes Transceiver GND D33 — — —
XGND SerDes Transceiver GND E28 — — —
XGND SerDes Transceiver GND E30 — — —
XGND SerDes Transceiver GND F32 — — —
XGND SerDes Transceiver GND G29 — — —
XGND SerDes Transceiver GND G31 — — —
XGND SerDes Transceiver GND H29 — — —
XGND SerDes Transceiver GND H32 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 37
XGND SerDes Transceiver GND H34 — — —
XGND SerDes Transceiver GND J29 — — —
XGND SerDes Transceiver GND J31 — — —
XGND SerDes Transceiver GND K28 — — —
XGND SerDes Transceiver GND K29 — — —
XGND SerDes Transceiver GND L29 — — —
XGND SerDes Transceiver GND L32 — — —
XGND SerDes Transceiver GND M30 — — —
XGND SerDes Transceiver GND N29 — — —
XGND SerDes Transceiver GND N30 — — —
XGND SerDes Transceiver GND N32 — — —
XGND SerDes Transceiver GND P29 — — —
XGND SerDes Transceiver GND P34 — — —
XGND SerDes Transceiver GND R30 — — —
XGND SerDes Transceiver GND R32 — — —
XGND SerDes Transceiver GND U29 — — —
XGND SerDes Transceiver GND U31 — — —
XGND SerDes Transceiver GND V29 — — —
XGND SerDes Transceiver GND V31 — — —
XGND SerDes Transceiver GND W30 — — —
XGND SerDes Transceiver GND Y32 — — —
XGND SerDes Transceiver GND AH31 — — —
XGND SerDes Transceiver GND Y28 — — —
SGND SerDes Core Logic GND A28 — — —
SGND SerDes Core Logic GND A32 — — —
SGND SerDes Core Logic GND A36 — — —
SGND SerDes Core Logic GND AA34 — — —
SGND SerDes Core Logic GND AB36 — — —
SGND SerDes Core Logic GND AD35 — — —
SGND SerDes Core Logic GND AE34 — — —
SGND SerDes Core Logic GND AF36 — — —
SGND SerDes Core Logic GND AG33 — — —
SGND SerDes Core Logic GND B30 — — —
SGND SerDes Core Logic GND B34 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor38
SGND SerDes Core Logic GND C29 — — —
SGND SerDes Core Logic GND C33 — — —
SGND SerDes Core Logic GND D31 — — —
SGND SerDes Core Logic GND D35 — — —
SGND SerDes Core Logic GND E35 — — —
SGND SerDes Core Logic GND G34 — — —
SGND SerDes Core Logic GND G36 — — —
SGND SerDes Core Logic GND J35 — — —
SGND SerDes Core Logic GND K33 — — —
SGND SerDes Core Logic GND L36 — — —
SGND SerDes Core Logic GND M34 — — —
SGND SerDes Core Logic GND N35 — — —
SGND SerDes Core Logic GND R33 — — —
SGND SerDes Core Logic GND R36 — — —
SGND SerDes Core Logic GND T35 — — —
SGND SerDes Core Logic GND U34 — — —
SGND SerDes Core Logic GND V36 — — —
SGND SerDes Core Logic GND W33 — — —
SGND SerDes Core Logic GND Y35 — — —
SGND SerDes Core Logic GND AH35 — — —
SGND SerDes Core Logic GND AH33 — — —
SGND SerDes Core Logic GND AF29 — — —
AGND_SRDS1 SerDes PLL1 GND B33 — — —
AGND_SRDS2 SerDes PLL2 GND T36 — — —
AGND_SRDS3 SerDes PLL3 GND AE36 — — —
AGND_SRDS4 SerDes PLL4 GND T28 — — —
SENSEGND_PL1 Platform GND Sense 1 AF12 — — 8
SENSEGND_PL2 Platform GND Sense 2 K27 — — 8
SENSEGND_CA Core Group A GND Sense K17 — — 8
USB1_AGND USB1 PHY Transceiver GND AH24 — — —
USB1_AGND USB1 PHY Transceiver GND AJ24 — — —
USB1_AGND USB1 PHY Transceiver GND AL25 — — —
USB1_AGND USB1 PHY Transceiver GND AM25 — — —
USB1_AGND USB1 PHY Transceiver GND AR25 — — —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 39
USB1_AGND USB1 PHY Transceiver GND AR26 — — —
USB1_AGND USB1 PHY Transceiver GND AR27 — — —
USB1_AGND USB1 PHY Transceiver GND AR28 — — —
USB1_AGND USB1 PHY Transceiver GND AT25 — — —
USB1_AGND USB1 PHY Transceiver GND AT28 — — —
USB2_AGND USB2 PHY Transceiver GND AH27 — — —
USB2_AGND USB2 PHY Transceiver GND AL28 — — —
USB2_AGND USB2 PHY Transceiver GND AM28 — — —
USB2_AGND USB2 PHY Transceiver GND AN25 — — —
USB2_AGND USB2 PHY Transceiver GND AN26 — — —
USB2_AGND USB2 PHY Transceiver GND AN27 — — —
USB2_AGND USB2 PHY Transceiver GND AN28 — — —
USB2_AGND USB2 PHY Transceiver GND AP25 — — —
USB2_AGND USB2 PHY Transceiver GND AP28 — — —
OVDD General I/O Supply AN22 — OVDD —
OVDD General I/O Supply AJ14 — OVDD —
OVDD General I/O Supply AJ18 — OVDD —
OVDD General I/O Supply AL16 — OVDD —
OVDD General I/O Supply AJ12 — OVDD —
OVDD General I/O Supply AN18 — OVDD —
OVDD General I/O Supply AG21 — OVDD —
OVDD General I/O Supply AL20 — OVDD —
OVDD General I/O Supply AT15 — OVDD —
OVDD General I/O Supply AJ23 — OVDD —
OVDD General I/O Supply AP16 — OVDD —
OVDD General I/O Supply AR24 — OVDD —
CVDD eSPI & eSDHC Supply AG24 — CVDD —
CVDD eSPI & eSDHC Supply AJ29 — CVDD —
CVDD eSPI & eSDHC Supply AP29 — CVDD —
GVDD DDR Supply B2 — GVDD —
GVDD DDR Supply B8 — GVDD —
GVDD DDR Supply B14 — GVDD —
GVDD DDR Supply C18 — GVDD —
GVDD DDR Supply C12 — GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor40
GVDD DDR Supply C6 — GVDD —
GVDD DDR Supply D4 — GVDD —
GVDD DDR Supply D10 — GVDD —
GVDD DDR Supply D16 — GVDD —
GVDD DDR Supply E14 — GVDD —
GVDD DDR Supply E8 — GVDD —
GVDD DDR Supply E2 — GVDD —
GVDD DDR Supply F6 — GVDD —
GVDD DDR Supply F12 — GVDD —
GVDD DDR Supply AR8 — GVDD —
GVDD DDR Supply G4 — GVDD —
GVDD DDR Supply G10 — GVDD —
GVDD DDR Supply G16 — GVDD —
GVDD DDR Supply H14 — GVDD —
GVDD DDR Supply H8 — GVDD —
GVDD DDR Supply H2 — GVDD —
GVDD DDR Supply J6 — GVDD —
GVDD DDR Supply K10 — GVDD —
GVDD DDR Supply K4 — GVDD —
GVDD DDR Supply L2 — GVDD —
GVDD DDR Supply L8 — GVDD —
GVDD DDR Supply M6 — GVDD —
GVDD DDR Supply N4 — GVDD —
GVDD DDR Supply N10 — GVDD —
GVDD DDR Supply P8 — GVDD —
GVDD DDR Supply P2 — GVDD —
GVDD DDR Supply R6 — GVDD —
GVDD DDR Supply T10 — GVDD —
GVDD DDR Supply T4 — GVDD —
GVDD DDR Supply J12 — GVDD —
GVDD DDR Supply U2 — GVDD —
GVDD DDR Supply U8 — GVDD —
GVDD DDR Supply V7 — GVDD —
GVDD DDR Supply AK10 — GVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 41
GVDD DDR Supply W10 — GVDD —
GVDD DDR Supply AA6 — GVDD —
GVDD DDR Supply AR2 — GVDD —
GVDD DDR Supply Y2 — GVDD —
GVDD DDR Supply Y8 — GVDD —
GVDD DDR Supply AC2 — GVDD —
GVDD DDR Supply AD6 — GVDD —
GVDD DDR Supply AE10 — GVDD —
GVDD DDR Supply AE4 — GVDD —
GVDD DDR Supply AF2 — GVDD —
GVDD DDR Supply AF8 — GVDD —
GVDD DDR Supply AB4 — GVDD —
GVDD DDR Supply AB10 — GVDD —
GVDD DDR Supply AC8 — GVDD —
GVDD DDR Supply AG6 — GVDD —
GVDD DDR Supply AH10 — GVDD —
GVDD DDR Supply AH4 — GVDD —
GVDD DDR Supply AJ2 — GVDD —
GVDD DDR Supply AJ8 — GVDD —
GVDD DDR Supply AR14 — GVDD —
GVDD DDR Supply AK6 — GVDD —
GVDD DDR Supply AL4 — GVDD —
GVDD DDR Supply AL10 — GVDD —
GVDD DDR Supply AM2 — GVDD —
GVDD DDR Supply AM8 — GVDD —
GVDD DDR Supply AP10 — GVDD —
GVDD DDR Supply AN12 — GVDD —
GVDD DDR Supply AN6 — GVDD —
GVDD DDR Supply AP4 — GVDD —
BVDD Local Bus Supply B24 — BVDD —
BVDD Local Bus Supply K22 — BVDD —
BVDD Local Bus Supply F20 — BVDD —
BVDD Local Bus Supply F26 — BVDD —
BVDD Local Bus Supply E24 — BVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor42
BVDD Local Bus Supply E22 — BVDD —
BVDD Local Bus Supply K24 — BVDD —
BVDD Local Bus Supply H20 — BVDD —
BVDD Local Bus Supply H18 — BVDD —
SVDD SerDes Core Logic Supply A30 — SVDD —
SVDD SerDes Core Logic Supply A34 — SVDD —
SVDD SerDes Core Logic Supply AA33 — SVDD —
SVDD SerDes Core Logic Supply AB35 — SVDD —
SVDD SerDes Core Logic Supply AD36 — SVDD —
SVDD SerDes Core Logic Supply AE33 — SVDD —
SVDD SerDes Core Logic Supply AF35 — SVDD —
SVDD SerDes Core Logic Supply AG34 — SVDD —
SVDD SerDes Core Logic Supply B28 — SVDD —
SVDD SerDes Core Logic Supply B32 — SVDD —
SVDD SerDes Core Logic Supply B36 — SVDD —
SVDD SerDes Core Logic Supply C31 — SVDD —
SVDD SerDes Core Logic Supply C34 — SVDD —
SVDD SerDes Core Logic Supply C35 — SVDD —
SVDD SerDes Core Logic Supply D29 — SVDD —
SVDD SerDes Core Logic Supply E36 — SVDD —
SVDD SerDes Core Logic Supply F34 — SVDD —
SVDD SerDes Core Logic Supply G35 — SVDD —
SVDD SerDes Core Logic Supply J36 — SVDD —
SVDD SerDes Core Logic Supply K34 — SVDD —
SVDD SerDes Core Logic Supply L35 — SVDD —
SVDD SerDes Core Logic Supply M33 — SVDD —
SVDD SerDes Core Logic Supply N36 — SVDD —
SVDD SerDes Core Logic Supply R34 — SVDD —
SVDD SerDes Core Logic Supply R35 — SVDD —
SVDD SerDes Core Logic Supply U33 — SVDD —
SVDD SerDes Core Logic Supply V35 — SVDD —
SVDD SerDes Core Logic Supply W34 — SVDD —
SVDD SerDes Core Logic Supply Y36 — SVDD —
SVDD SerDes Core Logic Supply AH36 — SVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 43
S1VDD SerDes Core Logic Supply AC29 — SVDD —
S1VDD SerDes Core Logic Supply AG28 — SVDD —
XVDD SerDes Transceiver Supply AA29 — XVDD —
XVDD SerDes Transceiver Supply AB30 — XVDD —
XVDD SerDes Transceiver Supply AB31 — XVDD —
XVDD SerDes Transceiver Supply AC33 — XVDD —
XVDD SerDes Transceiver Supply AD32 — XVDD —
XVDD SerDes Transceiver Supply AE30 — XVDD —
XVDD SerDes Transceiver Supply AF31 — XVDD —
XVDD SerDes Transceiver Supply E32 — XVDD —
XVDD SerDes Transceiver Supply E33 — XVDD —
XVDD SerDes Transceiver Supply F28 — XVDD —
XVDD SerDes Transceiver Supply F30 — XVDD —
XVDD SerDes Transceiver Supply G32 — XVDD —
XVDD SerDes Transceiver Supply H31 — XVDD —
XVDD SerDes Transceiver Supply H33 — XVDD —
XVDD SerDes Transceiver Supply J28 — XVDD —
XVDD SerDes Transceiver Supply J30 — XVDD —
XVDD SerDes Transceiver Supply J32 — XVDD —
XVDD SerDes Transceiver Supply K30 — XVDD —
XVDD SerDes Transceiver Supply L30 — XVDD —
XVDD SerDes Transceiver Supply L31 — XVDD —
XVDD SerDes Transceiver Supply M29 — XVDD —
XVDD SerDes Transceiver Supply N31 — XVDD —
XVDD SerDes Transceiver Supply P30 — XVDD —
XVDD SerDes Transceiver Supply P33 — XVDD —
XVDD SerDes Transceiver Supply R29 — XVDD —
XVDD SerDes Transceiver Supply R31 — XVDD —
XVDD SerDes Transceiver Supply T29 — XVDD —
XVDD SerDes Transceiver Supply T32 — XVDD —
XVDD SerDes Transceiver Supply U30 — XVDD —
XVDD SerDes Transceiver Supply V30 — XVDD —
XVDD SerDes Transceiver Supply V32 — XVDD —
XVDD SerDes Transceiver Supply W29 — XVDD —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor44
XVDD SerDes Transceiver Supply Y31 — XVDD —
XVDD SerDes Transceiver Supply AH32 — XVDD —
X1VDD SerDes Transceiver Supply AG27 — XVDD —
VDD_LL SerDes B4 Logic supply AC28 — VDD_PL 43
LVDD Ethernet Controller 1 and 2 Supply AK33 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AP31 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AL31 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AN33 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AJ35 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AR35 — LVDD —
LVDD Ethernet Controller 1 and 2 Supply AM35 — LVDD —
POVDD Fuse Programming Override
Supply
AT 1 7 — P OV DD 33
VDD_PL Platform Supply M26 — VDD_PL —
VDD_PL Platform Supply P26 — VDD_PL —
VDD_PL Platform Supply T26 — VDD_PL —
VDD_PL Platform Supply V26 — VDD_PL —
VDD_PL Platform Supply Y26 — VDD_PL —
VDD_PL Platform Supply AB26 — VDD_PL —
VDD_PL Platform Supply AD26 — VDD_PL —
VDD_PL Platform Supply N11 — VDD_PL —
VDD_PL Platform Supply R11 — VDD_PL —
VDD_PL Platform Supply W11 — VDD_PL —
VDD_PL Platform Supply AA11 — VDD_PL —
VDD_PL Platform Supply AE11 — VDD_PL —
VDD_PL Platform Supply M12 — VDD_PL —
VDD_PL Platform Supply P12 — VDD_PL —
VDD_PL Platform Supply T12 — VDD_PL —
VDD_PL Platform Supply V12 — VDD_PL —
VDD_PL Platform Supply Y12 — VDD_PL —
VDD_PL Platform Supply AB12 — VDD_PL —
VDD_PL Platform Supply AD12 — VDD_PL —
VDD_PL Platform Supply AE13 — VDD_PL —
VDD_PL Platform Supply AE15 — VDD_PL —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 45
VDD_PL Platform Supply V16 — VDD_PL —
VDD_PL Platform Supply AE17 — VDD_PL —
VDD_PL Platform Supply L11 — VDD_PL —
VDD_PL Platform Supply AE19 — VDD_PL —
VDD_PL Platform Supply U11 — VDD_PL —
VDD_PL Platform Supply AC11 — VDD_PL —
VDD_PL Platform Supply V20 — VDD_PL —
VDD_PL Platform Supply AE21 — VDD_PL —
VDD_PL Platform Supply V22 — VDD_PL —
VDD_PL Platform Supply U13 — VDD_PL —
VDD_PL Platform Supply R27 — VDD_PL —
VDD_PL Platform Supply U23 — VDD_PL —
VDD_PL Platform Supply W23 — VDD_PL —
VDD_PL Platform Supply AA27 — VDD_PL —
VDD_PL Platform Supply AC27 — VDD_PL —
VDD_PL Platform Supply AE23 — VDD_PL —
VDD_PL Platform Supply M24 — VDD_PL —
VDD_PL Platform Supply P24 — VDD_PL —
VDD_PL Platform Supply T24 — VDD_PL —
VDD_PL Platform Supply V24 — VDD_PL —
VDD_PL Platform Supply Y24 — VDD_PL —
VDD_PL Platform Supply AB24 — VDD_PL —
VDD_PL Platform Supply AD24 — VDD_PL —
VDD_PL Platform Supply N25 — VDD_PL —
VDD_PL Platform Supply R25 — VDD_PL —
VDD_PL Platform Supply U25 — VDD_PL —
VDD_PL Platform Supply W25 — VDD_PL —
VDD_PL Platform Supply AA25 — VDD_PL —
VDD_PL Platform Supply AC25 — VDD_PL —
VDD_PL Platform Supply N27 — VDD_PL —
VDD_PL Platform Supply U27 — VDD_PL —
VDD_PL Platform Supply W28 — VDD_PL —
VDD_PL Platform Supply AE25 — VDD_PL —
VDD_PL Platform Supply AF24 — VDD_PL —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor46
VDD_PL Platform Supply AF22 — VDD_PL —
VDD_PL Platform Supply AF20 — VDD_PL —
VDD_PL Platform Supply AF16 — VDD_PL —
VDD_PL Platform Supply W13 — VDD_PL —
VDD_PL Platform Supply AF18 — VDD_PL —
VDD_PL Platform Supply V14 — VDD_PL —
VDD_PL Platform Supply V18 — VDD_PL —
VDD_PL Platform Supply L13 — VDD_PL —
VDD_PL Platform Supply L15 — VDD_PL —
VDD_PL Platform Supply L17 — VDD_PL —
VDD_PL Platform Supply L19 — VDD_PL —
VDD_PL Platform Supply L21 — VDD_PL —
VDD_PL Platform Supply L23 — VDD_PL —
VDD_PL Platform Supply L25 — VDD_PL —
VDD_PL Platform Supply AF14 — VDD_PL —
VDD_PL Platform Supply N23 — VDD_PL —
VDD_PL Platform Supply R23 — VDD_PL —
VDD_PL Platform Supply AA23 — VDD_PL —
VDD_PL Platform Supply AC23 — VDD_PL —
VDD_PL Platform Supply U21 — VDD_PL —
VDD_PL Platform Supply W21 — VDD_PL —
VDD_PL Platform Supply U15 — VDD_PL —
VDD_PL Platform Supply AC21 — VDD_PL —
VDD_PL Platform Supply AD22 — VDD_PL —
VDD_PL Platform Supply M22 — VDD_PL —
VDD_PL Platform Supply N13 — VDD_PL —
VDD_PL Platform Supply AC13 — VDD_PL —
VDD_PL Platform Supply P22 — VDD_PL —
VDD_PL Platform Supply T22 — VDD_PL —
VDD_PL Platform Supply Y22 — VDD_PL —
VDD_PL Platform Supply AB22 — VDD_PL —
VDD_PL Platform Supply AA13 — VDD_PL —
VDD_PL Platform Supply R13 — VDD_PL —
VDD_PL Platform Supply M14 — VDD_PL —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 47
VDD_PL Platform Supply U17 — VDD_PL —
VDD_PL Platform Supply U19 — VDD_PL —
VDD_PL Platform Supply T14 — VDD_PL —
VDD_PL Platform Supply AD14 — VDD_PL —
VDD_PL Platform Supply AD16 — VDD_PL —
VDD_PL Platform Supply AD18 — VDD_PL —
VDD_PL Platform Supply AD20 — VDD_PL —
VDD_PL Platform Supply Y14 — VDD_PL —
VDD_CA Core/L2 Group A Supply T20 — VDD_CA —
VDD_CA Core/L2 Group A Supply P20 — VDD_CA —
VDD_CA Core/L2 Group A Supply R21 — VDD_CA —
VDD_CA Core/L2 Group A Supply R19 — VDD_CA —
VDD_CA Core/L2 Group A Supply P14 — VDD_CA —
VDD_CA Core/L2 Group A Supply N19 — VDD_CA —
VDD_CA Core/L2 Group A Supply M20 — VDD_CA —
VDD_CA Core/L2 Group A Supply N21 — VDD_CA —
VDD_CA Core/L2 Group A Supply M16 — VDD_CA —
VDD_CA Core/L2 Group A Supply N15 — VDD_CA —
VDD_CA Core/L2 Group A Supply P16 — VDD_CA —
VDD_CA Core/L2 Group A Supply T16 — VDD_CA —
VDD_CA Core/L2 Group A Supply R17 — VDD_CA —
VDD_CA Core/L2 Group A Supply T18 — VDD_CA —
VDD_CA Core/L2 Group A Supply R15 — VDD_CA —
VDD_CA Core/L2 Group A Supply N17 — VDD_CA —
VDD_CA Core/L2 Group A Supply M18 — VDD_CA —
VDD_CA Core/L2 Group A Supply P18 — VDD_CA —
VDD_LP Low Power Security Monitor
Supply
AD28 — VDD_LP —
AVDD_CC1 Core Cluster PLL1 Supply A20 — — 13
AVDD_CC2 Core Cluster PLL2 Supply AT18 — — 13
AVDD_PLAT Platform PLL Supply AT20 — — 13
AVDD_DDR DDR PLL Supply A19 — — 13
AVDD_FM FMan PLL Supply AT19 — — 13
AVDD_SRDS1 SerDes PLL1 Supply A33 — — 13
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor48
AVDD_SRDS2 SerDes PLL2 Supply U36 — — 13
AVDD_SRDS3 SerDes PLL3 Supply AE35 — — 13
AVDD_SRDS4 SerDes PLL4 Supply R28 — — 13
SENSEVDD_PL1 Platform Vdd Sense AF11 — — 8
SENSEVDD_PL2 Platform Vdd Sense L27 — — 8
SENSEVDD_CA Core Group A Vdd Sense K16 — — 8
USB1_VDD_3P3 USB1 PHY Transceiver 3.3V
Supply
AL24 — — —
USB1_VDD_3P3 USB1 PHY Transceiver 3.3V
Supply
AJ25 — — —
USB2_VDD_3P3 USB2 PHY Transceiver 3.3V
Supply
AJ26 — — —
USB2_VDD_3P3 USB2 PHY Transceiver 3.3V
Supply
AJ27 — — —
USB1_VDD_1P0 USB1 PHY PLL 1.0V Supply AH25 — — —
USB2_VDD_1P0 USB2 PHY PLL 1.0V Supply AH26 — — —
Analog Signals
MVREF SSTL_1.5/1.35 Reference Voltage B19 I GVDD/2 —
SD_IMP_CAL_TX SerDes transmitter Impedance
Calibration
AF30 I 200Ω
(±1%) to
XVDD
23
SD1_IMP_CAL_TX SerDes transmitter Impedance
Calibration
AA28 I 200Ω
(±1%) to
XVDD
23
SD_IMP_CAL_RX SerDes receiver Impedance
Calibration
B27 I 200Ω
(±1%) to
SVDD
24
SD1_IMP_CAL_RX SerDes receiver Impedance
Calibration
AF26 I 200Ω
(±1%) to
SVDD
24
TEMP_ANODE Temperature Diode Anode C21 — internal
diode
9
TEMP_CATHODE Temperature Diode Cathode B21 — internal
diode
9
USB1_IBIAS_REXT USB PHY1 Reference Bias Current
Generation
AM26 — — 36
USB2_IBIAS_REXT USB PHY2 Reference Bias Current
Generation
AM27 — — 36
USB1_VDD_1P8_DECAP USB1 PHY 1.8V Output to External
Decap
AL26 — — 37
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 49
USB2_VDD_1P8_DECAP USB2 PHY 1.8V Output to External
Decap
AL27 — — 37
No Connection Pins
NC_A27 No Connection A27 — — 11
NC_B26 No Connection B26 — — 11
NC_C19 No Connection C19 — — 11
NC_C20 No Connection C20 — — 11
NC_C26 No Connection C26 — — 11
NC_C27 No Connection C27 — — 11
NC_D18 No Connection D18 — — 11
NC_D27 No Connection D27 — — 11
NC_E16 No Connection E16 — — 11
NC_E27 No Connection E27 — — 11
NC_G27 No Connection G27 — — 11
NC_H12 No Connection H12 — — 11
NC_H13 No Connection H13 — — 11
NC_H15 No Connection H15 — — 11
NC_H27 No Connection H27 — — 11
NC_J11 No Connection J11 — — 11
NC_J13 No Connection J13 — — 11
NC_J14 No Connection J14 — — 11
NC_K11 No Connection K11 — — 11
NC_K12 No Connection K12 — — 11
NC_K13 No Connection K13 — — 11
NC_K14 No Connection K14 — — 11
NC_W27 No Connection W27 — — 11
NC_AG15 No Connection AG15 — — 11
Reserved Pins
Reserve_A21 — A21 — — 41
Reserve_A25 — A25 — — 11
Reserve_C32 — C32 — — 11
Reserve_D32 — D32 — — 11
Reserve_F1 — F1 — — 11
Reserve_F2 — F2 — — 11
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Pin assignments and reset states
Freescale Semiconductor50
Reserve_G1 — G1 — — 11
Reserve_G2 — G2 — — 11
Reserve_L28 — L28 — GND 21
Reserve_M28 — M28 — GND 21
Reserve_N28 — N28 — GND 21
Reserve_P28 — P28 — GND 21
Reserve_U32 — U32 — — 11
Reserve_U35 — U35 — — 11
Reserve_AD33 — AD33 — — 11
Reserve_AD34 — AD34 — — 11
Reserve_AG11 — AG11 — GND 21
Reserve_AG12 — AG12 — GND 21
Reserve_AG26 — AG26 — — 11
Reserve_AG29 — AG29 — — 11
Reserve_AH11 — AH11 — GND 21
Reserve_AH12 — AH12 — GND 21
Reserve_AH30 — AH30 — — 11
Reserve_AK1 — AK1 — — 11
Reserve_AK2 — AK2 — — 11
Reserve_AL1 — AL1 — — 11
Reserve_AL2 — AL2 — — 11
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 51
Notes:
1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD.
2. This pin is an open drain signal.
3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ resistor. However, if the signal is
intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then
a pull up or active driver is needed.
4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
5. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BVDD, to ensure no random chip select assertion due
to possible noise, and so forth.
6. This output is actively driven during reset rather than being three-stated during reset.
7. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair
to be used by the voltage regulators with remote sense function.
9. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding
that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device.
11. Do not connect.
12. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OVDD for normal device operation.
13. Independent supplies derived from board VDD_PL (Core clusters, Platform, DDR) or SVDD (SerDes).
14. Recommend a pull-up resistor of 1-kΩ be placed on this pin to OVDD if I2C interface is used.
15. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
driven.
16. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 40.2-Ω (half-strength mode) precision 1% resistor and
Dn_MDIC[1] is connected to GVDD through an 40.2-Ω (half-strength mode) precision 1% resistor. These pins are used for
automatic calibration of the DDR3 and DDR3L IOs.
18. These pins should be pulled up to 1.2V through a 180Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for
EM2_MDIO.
20. Pin has a weak internal pull-up.
21. These pins should be pulled to ground (GND).
22. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage
levels. LVDD must be powered to use this interface.
23. This pin requires a 200-Ω pull-up to XVDD.
24. This pin requires a 200-Ω pull-up to SVDD.
25. This GPIO pin is on LVDD power plane, not OVDD.
26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined
by the RCW.
27. See Section 3.6, “Connection recommendations,” for additional details on this signal.
28. This signal must be pulled low to GND.
30. Warning, incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default
setting.”
31. SDHC_DAT[4:7] require CVDD = 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.
32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XVDD pin.
Incorrect voltage select settings can lead to irreversible device damage.
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor52
2 Electrical characteristics
This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications,
some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other electrical characteristics.
2.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings.
33. See Section 2.2, “Power-up sequencing and Section 5, “Security fuse processor,” for additional details on this signal.
35. Pin must NOT be pulled down by a resistor or the component it is connected to during power-on reset.
36. This pin should be connected to GND through a 10kΩ ± 0.1% resistor with a low temperature coefficient of ≤ 25ppm/°C for
bias generation.
37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in
Section 3.6.4.2, “USBn_VDD_1P8_DECAP capacitor options.”
38. A divider network is required on this signal. See Section 3.6.4.1, “USB divider network.”
39. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is
required.
40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect.
42. The VDD_VID_CA_CB pins are inputs at POR. If a voltage regulator is connected directly to the VID_VDD_CA_CB pins,
customers need to put weak pull-ups or pull-downs on their board so that their voltage regulator drives a guaranteed-to-work
voltage with the cores configured to run at a safe frequency for that voltage. This is needed so that a working voltage can be
applied until the operating voltage is determined (for example, so that PLLs can begin to lock, and so on, during this time frame
or while the voltage is ramping). The safe boot voltage for the chip is 1.1 V. Note that the P5021 does not require VID to meet
it's performance and power envelope. All power rails should be fixed at the operating values specified in Ta b l e 3 .
“Recommended operating conditions.”
43. VDD_LL should be connected directly to VDD_PL.
44. Normally tied to GND. See the applicable migration application note if moving from P3041 (AN4395) or P5020/P5010
(AN4400).
Table 2. Absolute maximum operating conditions1
Parameter Symbol Maximum value Unit Notes
Core group A (core 0,1) supply voltage VDD_CA –0.3 to 1.32 V 9,11
Platform supply voltage VDD_PL –0.3 to 1.1 V 9,10,
11
PLL supply voltage (core, platform, DDR) AVDD –0.3 to 1.1 V —
PLL supply voltage (SerDes, filtered from SVDD)AV
DD_SRDS –0.3 to 1.1 V —
Table 1. Pins listed by bus (continued)
Signal Signal description Package
pin number
Pin
type
Power
supply Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 53
Fuse programming override supply POVDD –0.3 to 1.65 V 1
DUART, I2C, DMA, MPIC, GPIO, system control and power
management, clocking, debug, I/O voltage select, and JTAG I/O
voltage
OVDD –0.3 to 3.63 V —
eSPI, eSHDC CVDD –0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V—
DDR3 and DDR3L DRAM I/O voltage GVDD –0.3 to 1.65 V —
Enhanced local bus I/O voltage BVDD –0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V—
Core power supply for SerDes transceivers SVDD –0.3 to 1.1 V —
Pad power supply for SerDes transceivers XVDD –0.3 to 1.98
–0.3 to 1.65
V—
Ethernet I/O, Ethernet management interface 1 (EMI1), 1588, GPIO LVDD –0.3 to 3.63
–0.3 to 2.75
V3
Ethernet management interface 2 (EMI2) — –0.3 to 1.32 V 8
USB PHY Transceiver supply voltage USB_VDD_3P3 –0.3 to 3.63 V —
USB PHY PLL supply voltage USB_VDD_1P0 –0.3 to 1.1 V —
Low-power security monitor supply VDD_LP –0.3 to 1.1 V —
Table 2. Absolute maximum operating conditions1 (continued)
Parameter Symbol Maximum value Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor54
Input voltage7DDR3 and DDR3L DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 7
DDR3 and DDR3L DRAM reference MVREF –0.3 to (GVDD/2+ 0.3) V 2, 7
Ethernet signals (except EMI2) LVIN –0.3 to (LVDD + 0.3) V 3, 7
eSPI, eSHDC CVIN –0.3 to (CVDD + 0.3) V 4, 7
Enhanced local bus signals BVIN –0.3 to (BVDD + 0.3) V 5, 7
DUART, I2C, DMA, MPIC, GPIO, system
control and power management, clocking,
debug, I/O voltage select, and JTAG I/O
voltage
OVIN –0.3 to (OVDD + 0.3) V 6, 7
SerDes signals XVIN –0.4 to (XVDD + 0.3) V 7
USB PHY transceiver signals USB_VIN_3P3 –0.3 to
(USB_VDD_3P3 + 0.3)
V7
Ethernet management interface 2 (EMI2)
signals
— –0.3 to (1.2 + 0.3) V 7
Storage junction temperature range Tstg –55 to 150 °C—
Notes:
1. Functional operating conditions are given in Ta b le 3 . Absolute maximum ratings are stress ratings only; functional operation
at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to
the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
4. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
6. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
7. (C,X,B,G,L,O)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 7.
8. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels.
LVDD must be powered to use this interface.
9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
10. Implementation may choose either VDD_PL pin for feedback loop. If the platform and core groups are supplied by a single
regulator, it is recommended that VDD_CA be used.
11. VDD_PL voltage must not exceed VDD_CA.
Table 2. Absolute maximum operating conditions1 (continued)
Parameter Symbol Maximum value Unit Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 55
2.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this device. Note that proper device operation outside these
conditions is not guaranteed.
Table 3. Recommended operating conditions
Parameter Symbol Recommended
value Unit Notes
Core group A (core 0,1) supply voltage VDD_CA 1.1 ± 50mV (core
frequency ≤
2000 MHz)
1.2V ± 30mV (core
frequency >
2000 MHz)
V1,6
Platform supply voltage VDD_PL 1.0 ± 50mV V 1,6
PLL supply voltage (core, platform, DDR, FMan) AVDD 1.0 ± 50mV V —
PLL supply voltage (SerDes) AVDD_SRDS 1.0 ± 50mV V —
Fuse programming override supply POVDD 1.5 ± 75mV V 2
DUART, I2C, DMA, MPIC, GPIO, system control and power
management, clocking, debug, I/O voltage select, and JTAG I/O
voltage
OVDD 3.3 ± 165mV V —
eSPI, eSDHC CVDD 3.3 ± 165mV
2.5 ± 125mV
1.8 ± 90mV
V—
DDR DRAM I/O voltage DDR3 GVDD 1.5 ± 75mV V —
DDR3L 1.35 ± 67mV
Enhanced local bus I/O voltage BVDD 3.3 ± 165mV
2.5 ± 125mV
1.8 ± 90mV
V—
Main power supply for internal circuitry of SerDes and pad power
supply for SerDes receiver
SVDD 1.0 + 50mV
1.0 – 30mV
V—
Pad power supply for SerDes transmitter XVDD 1.8 ± 90mV
1.5 ± 75mV
V—
Ethernet I/O, Ethernet Management interface 1 (EMI1), 1588, GPIO LVDD 3.3 ± 165mV
2.5 ± 125mV
V3
USB PHY transceiver supply voltage USB_VDD_3P3 3.3 ± 165mV V —
USB PHY PLL supply voltage USB_VDD_1P0 1.0 ± 50mV V —
Low-power security monitor supply VDD_LP 1.0 ± 50mV V —
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor56
Input voltage DDR3 and DDR3L DRAM
signals
MVIN GND to GVDD V7
DDR3 and DDR3L DRAM
reference
MVREF GVDD/2 ± 1% V 7
Ethernet signals (except EMI2) LVIN GND to LVDD V7
eSPI, eSHDC CVIN GND to CVDD V7
Enhanced local bus signals BVIN GND to BVDD V7
DUART, I2C, DMA, MPIC, GPIO,
system control and power
management, clocking, debug,
I/O voltage select, and JTAG I/O
voltage
OVIN GND to OVDD V7
SerDes signals SVIN GND to SVDD V7
USB PHY Transceiver signals USB_VIN_3P3 GND to
USB_VDD_3P3
V7
Ethernet Management interface
2 (EMI2) signals
— GND to 1.2V V 4, 7
Operating Temperature range Normal Operation TA,
TJ
TA = 0 (min) to
TJ = 105 (max)
(90 (max) core
frequency > 2000
MHz)
°C—
Extended Temperature TA,
TJ
TA = -40 (min) to
TJ = 105 (max)
°C—
Secure Boot Fuse Programming TA,
TJ
TA = 0 (min) to
TJ = 70 (max)
°C2
Notes:
1. VDD_PL voltage must not exceed VDD_CA.
2. POVDD must be supplied 1.5 V and the chip must operate in the specified fuse programming temperature range only
during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the
power sequencing constraints shown in Section 2.2, “Power-up sequencing.”
3. Selecting RGMII limits LVDD to 2.5V.
4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage
levels. LVDD must be powered to use this interface.6. Supply voltage specified at the voltage sense pin. Voltage input
pins must be regulated to provide specified voltage at the sense pin.
7. All input signals must increase/decrease monotonically throughout the entire rise/fall duration.
Table 3. Recommended operating conditions (continued)
Parameter Symbol Recommended
value Unit Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 57
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
Figure 7. Overshoot/Undershoot voltage for BVDD/GVDD/LVDD/OVDD
The core and platform voltages must always be provided at nominal 1.0 V or 1.2 V. See Table 3 for the actual recommended
core voltage conditions. Voltage to the processor interface I/Os is provided through separate sets of supply pins and must be
provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage.
CVDD, BVDD, OVDD, and LVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type
specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MVREF signal
(nominally set to GVDD/2) as is appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
GND
GND – 0.3V
GND – 0.7 V Not to Exceed 10%
Nominal C/X/B/G/L/OVDD + 20%
C/X/B/G/L/OVDD
C/X/B/G/L/OVDD + 5%
of tCLOCK
tCLOCK refers to the clock period associated with the respective interface:
VIH
VIL
Note:
For I2C, tCLOCK refers to SYSCLK.
For DDR GVDD, tCLOCK refers to Dn_MCK.
For eSPI CVDD, tCLOCK refers to SPI_CLK.
For eLBC BVDD, tCLOCK refers to LCLK.
For SerDes XVDD, tCLOCK refers to SD_REF_CLK.
For dTSEC LVDD, tCLOCK refers to EC_GTX_CLK125.
For JTAG OVDD, tCLOCK refers to TCK.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor58
2.1.3 Output driver characteristics
This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates.
2.2 Power-up sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1. Bring up OVDD, LVDD, BVDD, CVDD, and USB_VDD_3P3. Drive POVDD = GND.
— PORESET input must be driven asserted and held during this step
— IO_VSEL inputs must be driven during this step and held stable during normal operation.
—USB_V
DD_3P3 rise time (10% to 90%) has a minimum of 350 μs.
2. Bring up VDD_PL, VDD_CA, SVDD, AVDD (cores, platform, DDR, SerDes) and USB_VDD_1P0. VDD_PL and
USB_VDD_1P0 must be ramped up simultaneously.
3. Bring up GVDD and XVDD.
4. Negate PORESET input as long as the required assertion/hold time has been met per Table 15.
5. For secure boot fuse programming: After negation of PORESET, drive POVDD = 1.5 V after a required minimum
delay per Table 5. After fuse programming is completed, it is required to return POVDD = GND before the system is
power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in
Table 5. See Section 5, “Security fuse processor,” for additional details.
WARNING
Only two secure boot fuse programming events are permitted per lifetime of a device.
No activity other than that required for secure boot fuse programming is permitted while
POVDD driven to any voltage above GND, including the reading of the fuse block. The
reading of the fuse block may only occur while POVDD = GND.
Table 4. Output drive capability
Driver type Output impedance (Ω)(Nominal) supply
voltage Notes
Local bus interface utilities signals 45
45
45
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
—
DDR3 signal 20 (full-strength mode)
40 (half-strength mode)
GVDD = 1.5 V 1
DDR3L signal 20 (full-strength mode)
40 (half-strength mode)
GVDD = 1.35 V 1
eTSEC/10/100 signals 45
45
LVDD = 3.3 V
LVDD = 2.5 V
—
DUART, system control, JTAG 45 OVDD = 3.3 V —
I2C45OV
DD = 3.3 V —
eSPI and SD/MMC 45
45
45
CVDD = 3.3 V
CVDD = 2.5 V
CVDD = 1.8 V
—
Note:
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min).
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 59
WARNING
Only 100,000 POR cycles are permitted per lifetime of a device.
WARNING
While VDD is ramping, current may be supplied from VDD through the P5021 to GVDD.
Nevertheless, GVDD from an external supply should follow the sequencing described
above.
All supplies must be at their stable values within 75 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
This figure provides the POVDD timing diagram.
Figure 8. POVDD timing diagram
This table provides information on the power-down and power-up sequence parameters for POVDD.
To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the
DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required.
Table 5. POVDD timing 5
Driver type Min Max Unit Notes
tPOVDD_DELAY 100 — SYSCLKs 1
tPOVDD_PROG 0—μs2
tPOVDD_VDD 0—μs3
tPOVDD_RST 0—μs4
Notes:
1. Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90%
OVDD to 10% POVDD ramp up.
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD
is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to
any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD =
GND. After fuse programming is completed, it is required to return POVDD = GND.
3. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded to minimum 10%
POVDD before VDD_PL is at 90% VDD.
4. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD
before PORESET assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
t
POVDD_PROG
t
POVDD_DELAY
POVDD
VDD_PL
PORESET
t
POVDD_RST
Fuse programming
1
90%
OV
DD
10% POV
DD
10% POV
DD
90% V
DD_PL
t
POVDD_VDD
NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.
90%
OV
DD
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor60
WARNING
Incorrect voltage select settings can lead to irreversible device damage. See Section 3.2,
“Supply power default setting.”
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA, or
VDD_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero
during power-up, and extra current may be drawn by the device.
2.3 Power-down requirements
The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
If performing secure boot fuse programming per Section 2.2, “Power-up sequencing,” it is required that POVDD = GND before
the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in
Table 5.
VDD_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only
after USB_VDD_3P3 is below 1.65 V.
2.4 Power characteristics
This table shows the power dissipations of the VDD_CA, SVDD, and VDD_PL supply for various operating platform clock
frequencies versus the core and DDR clock frequencies for the chip.
Table 6. Power dissipation
Power
Mode
Core
freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MHz)
FM freq
(MHz)
VDD_PL,
SVDD
(V)
VDD_CA
(V)
Junction
temp
(°C)
Core
and plat-
form
power1
(W)
VDD_PL
power
(W)
VDD_CA
power
(W)
SVDD
power
(W)
Note
Typical
2200 800 1600 600 1.0 1.2
65 23 — — — —
Thermal
90
33 ————
Maximum 34 17 15 15 2.2
Typical
2000 700 1333 600 1.0 1.1
65 21 — — — —
Thermal
105
30 ————
Maximum 31 16 13 13 2.2
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 61
This table shows the estimated power dissipation on the AVDD and AVDD_SRDS supplies for the chip’s PLLs, at allowable
voltage levels.
Typical
1800 600 1200 450 1.0 1.1
65 20 — — — —
Thermal
105
29 ————
Maximum 30 15 13 13 2.2
Notes:
1. Combined power of VDD_PL, VDD_CA, SVDD with both DDR controllers and all SerDes banks active. Does not include I/O
power.
2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with
90% activity factor.
3. Typical power based on nominal processed device.
4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform
at 100% activity factor.
5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at
90% activity factor.
6. Maximum power provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
Table 7. AVDD power dissipation
AVDDs Typical Maximum Unit Notes
AVDD_DDR 515mW1
AVDD_CC1 515mW
AVDD_CC2 515mW
AVDD_PLAT 515mW
AVDD_FM 515mW
AVDD_SRDS1 —36mW2
AVDD_SRDS2 —36mW
AVDD_SRDS3 —36mW
AVDD_SRDS4 —36mW
USB_VDD_1P0 — 10 mW 3
VDD_LP —5mW
Note:
1. VDD_CA = 1.2 V, TA = 80°C, TJ = 105°C
2. VDD_PL, SVDD = 1.0 V, TA = 80°C, TJ = 105°C
3. USB_VDD_1P0, VDD_LP = 1.0 V, TA = 80°C, TJ = 105°C
Table 6. Power dissipation (continued)
Power
Mode
Core
freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MHz)
FM freq
(MHz)
VDD_PL,
SVDD
(V)
VDD_CA
(V)
Junction
temp
(°C)
Core
and plat-
form
power1
(W)
VDD_PL
power
(W)
VDD_CA
power
(W)
SVDD
power
(W)
Note
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor62
This table shows the estimated power dissipation on the POVDD supply for the chip, at allowable voltage levels.
This table shows the estimated power dissipation on the VDD_LP supply for the chip, at allowable voltage levels.
2.5 Thermal
This table shows the thermal characteristics for the chip.
Table 8. POVDD power dissipation
Supply Maximum Unit Notes
POVDD 450 mW 1
Note:
1. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature
range per Ta b l e 3 .
Table 9. VDD_LP Power Dissipation
Supply Maximum Unit Note
VDD_LP (P5021 on, 105C) 1.5 mW 1
VDD_LP (P5021 off, 70C) 195 uW 2
VDD_LP (P5021 off, 40C) 132 uW 2
Note:
1. VDD_LP = 1.0 V, TJ = 105°C.
2. When P5021 is off, VDD_LP may be supplied by battery power to the Zeroizable Master Key and other Trust Architecture
state. Board should implement a PMIC which switches VDD_LP to battery when P5021 is powered down. See P5040
Reference Manual Trust Architecture chapter for more information.
Table 10. Package thermal characteristics 6
Rating Board Symbol Value Unit Notes
Junction to ambient, natural convection Single-layer board (1s) RΘJA 14 °C/W 1, 2
Junction to ambient, natural convection Four-layer board (2s2p) RΘJA 10 °C/W 1, 2
Junction to ambient (at 200 ft./min.) Single-layer board (1s) RΘJMA 9°C/W 1, 2
Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RΘJMA 7°C/W 1, 2
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 63
2.6 Input clocks
This section discusses the system clock timing specifications for DC and AC power, spread spectrum sources, real time clock
timing, and dTSEC gigabit Ethernet reference clocks AC timing.
2.6.1 System clock (SYSCLK) timing specifications
This table provides the system clock (SYSCLK) DC specifications.
Junction to board — RΘJB 3°C/W 3
Junction to case top — RΘJCtop 0.44 °C/W 4
Junction to lid top — RΘJClid 0.17 °C/W 5
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid top temperature is used here for the reference case temperature. The reported value does not include the thermal
resistance of the interface layer between the package and cold plate.
5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal
resistance of the interface layer between the package and cold plate.
6. Reference Section 3.8, “Thermal management information,” for additional details.
Table 11. SYSCLK DC electrical characteristics (OVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 2.0 — — V 1
Input low voltage VIL ——0.8V1
Input current (OVIN= 0 V or OVIN =
OVDD)
IIN ——±40μA2
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Ta bl e 3 .
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 10. Package thermal characteristics (continued)6
Rating Board Symbol Value Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor64
This table provides the system clock (SYSCLK) AC timing specifications.
2.6.2 Spread-spectrum sources recommendations
Spread-spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in Table 13 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns;
the chip is compatible with spread spectrum sources if the recommendations listed in Table 13 are observed.
CAUTION
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which
the processor is operated at its maximum rated core/platform/DDR frequency should avoid
violating the stated limits by using down-spreading only.
Table 12. SYSCLK AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter/Condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 100 — 166 MHz 1, 2
SYSCLK cycle time tSYSCLK 6 — 10 ns 1, 2
SYSCLK duty cycle tKHK / tSYSCLK 40 — 60 % 2
SYSCLK slew rate — 1 — 4 V/ns 3
SYSCLK peak period jitter — — — 150 ps —
SYSCLK jitter phase noise — — — 500 KHz 4
AC Input Swing Limits at 3.3 V OVDD ΔVAC 1.9 — — V —
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from ±0.3 ΔVAC at center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
Table 13. Spread-spectrum clock source recommendations
For recommended operating conditions, see Ta b l e 3.
Parameter Min Max Unit Notes
Frequency modulation — 60 kHz —
Frequency spread — 1.0 % 1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Ta b l e 1 2 .
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 65
2.6.3 Real time clock timing
The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an
input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse
width of the RTC signal should be greater than 16× the period of the platform clock with a 50% duty cycle. There is no minimum
RTC frequency; RTC may be grounded if not needed.
2.6.4 dTSEC gigabit Ethernet reference clock timing
This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications.
2.6.5 Other input clocks
A description of the overall clocking of this device is available in the applicable chip reference manual in the form of a clock
subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device,
such as SerDes, Ethernet Management, eSDHC, Local bus, see the specific interface section.
2.7 RESET initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the
RESET initialization AC timing specifications.
Table 14. EC_GTX_CLK125 AC timing specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
EC_GTX_CLK125 frequency tG125 —125—MHz—
EC_GTX_CLK125 cycle time tG125 —8—ns—
EC_GTX_CLK125 rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
tG125R/tG125F ——
0.75
1.0
ns 1
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII
tG125H/tG125
47
—
53
%2
EC_GTX_CLK125 jitter — — — ± 150 ps 2
Note:
1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LVDD.
2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty
cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the dTSEC
GTX_CLK. See Section 2.12.2.3, “RGMII AC timing specifications,” for duty cycle for 10Base-T and 100Base-T reference
clock.
Table 15. RESET initialization timing specifications
Parameter Min Max Unit1Notes
Required assertion time of PORESET 1—ms3
Required input assertion time of HRESET 32 — SYSCLKs 1, 2
Input setup time for POR configurations with respect to negation of
PORESET
4 — SYSCLKs 1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor66
This table provides the PLL lock times.
2.8 Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate
specifications.
2.9 DDR3 and DDR3L SDRAM controller
This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note
that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GVDD(typ) voltage is 1.35 V when
interfacing to DDR3L SDRAM.
NOTE
When operating at DDR data rates of 1600 MT/s only one dual-ranked module per memory
controller is supported.
Input hold time for all POR configurations with respect to negation of
PORESET
2 — SYSCLKs 1
Maximum valid-to-high impedance time for actively driven POR
configurations with respect to negation of PORESET
— 5 SYSCLKs 1
Notes:
1. SYSCLK is the primary clock input for the chip.
2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device
releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in
Section 4.4.1 “Power-On Reset Sequence,” of the applicable chip reference manual.
3. PORESET must be driven asserted before the core and platform power supplies are powered up , see Section 2.2, “Power-up
sequencing.”
Table 16. PLL lock times
Parameter Min Max Unit Notes
PLL lock times — 100 μs—
Table 17. Power supply ramp rate
Parameter Min Max Unit Notes
Required ramp rate for all voltage supplies (including OVDD/CVDD/
GVDD/BVDD/SVDD/XVDD/LVDD all VDD supplies, MVREF and all AVDD supplies.)
— 36000 V/s 1, 2
Notes:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Ta b l e 3 ).
Table 15. RESET initialization timing specifications (continued)
Parameter Min Max Unit1Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 67
2.9.1 DDR3 and DDR3L SDRAM interface DC electrical characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
Table 18. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Note
I/O reference voltage MVREF 0.49 ×GVDD 0.51 × GVDD V2, 3, 4
Input high voltage VIH MVREF + 0.100 GVDD V5
Input low voltage VIL GND MVREF –0.100 V 5
I/O leakage current IOZ –50 50 μA6
Notes:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC
level of MVREF
.
4. The voltage regulator for MVREF must meet the specifications stated in Ta b l e 2 1 .
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Note
I/O reference voltage MVREF 0.49 ×GVDD 0.51 × GVDD V2, 3, 4
Input high voltage VIH MVREF + 0.090 GVDD V5
Input low voltage VIL GND MVREF –0.090 V 5
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor68
This table provides the DDR controller interface capacitance for DDR3 and DDR3L.
This table provides the current draw characteristics for MVREF.
I/O leakage current IOZ –50 50 μA6
Output high current (VOUT = 0.641 V) IOH —–23.3mA7, 8
Output low current (VOUT = 0.641 V) IOL 23.3 — mA 7, 8
Notes:
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC
level of MVREF
.
4. The voltage regulator for MVREF must meet the specifications stated in Ta b l e 2 1 .
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
7. Refer to the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at GVDD = 1.283 V
Table 20. DDR3 and DDR3L SDRAM Capacitance
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF 1, 2
Delta input/output capacitance: DQ, DQS, DQS CDIO — 0.5 pF 1, 2
Notes:
1. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA =25°C, V
OUT = GVDD/2,
VOUT (peak-to-peak) = 0.150 V.
2. This parameter is sampled. GVDD = 1.35 V – 0.067 V ÷ + 0.100 V (for DDR3L), f = 1 MHz, TA =25°C, V
OUT = GVDD/2,
VOUT (peak-to-peak) = 0.167 V.
Table 21. Current Draw Characteristics for MVREF
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Notes
Current draw for DDR3 SDRAM for MVREF MVREF — 1250 μA—
Current draw for DDR3L SDRAM for MVREF MVREF — 1250 μA—
Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1 (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Note
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 69
2.9.2 DDR3 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 and DDR3L memories. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
2.9.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 22. DDR3 SDRAM interface input AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
AC input low voltage >1200 MT/s data rate VILAC — MVREF – 0.150 V —
≤1200 MT/s data rate MVREF – 0.175
AC input high voltage >1200 MT/s data rate VIHAC MVREF + 0.150 — V —
≤1200 MT/s data rate MVREF + 0.175
Table 23. DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
AC input low voltage >1067 MT/s data rate VILAC — MVREF – 0.135 V —
≤1067 MT/sdata rate MVREF – 0.160
AC input high voltage >1067 MT/s data rate VIHAC MVREF + 0.135 — V —
≤1067 MT/s data rate MVREF + 0.160
Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS—MDQ/MECC tCISKEW ps 1
1600 MT/s data rate –112 112
1333 MT/s data rate –125 125
1200 MT/s data rate –147.5 147.5
1066 MT/s data rate –170 170
800 MT/s data rate –200 200
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor70
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram
Tolerated Skew for MDQS—MDQ/MECC tDISKEW ps 2
1600 MT/s data rate –200 200
1333 MT/s data rate –250 250
1200 MT/s data rate –275 275
1066 MT/s data rate –300 300
800 MT/s data rate –425 425
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =±(T÷4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Notes
MCK[n]
MCK[n] tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1D0
tDISKEW
tDISKEW
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 71
2.9.2.2 DDR3 and DDDR3L SDRAM interface output AC timing specifications
This table contains the output AC timing targets for the DDR3 SDRAM interface.
Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol1Min Max Unit Notes
MCK[n] cycle time tMCK 1.25 2.5 ns 2
ADDR/CMD output setup with respect to MCK tDDKHAS ns 3
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
800 MT/s data rate 0.917 —
ADDR/CMD output hold with respect to MCK tDDKHAX ns 3
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
800 MT/s data rate 0.917 —
MCS[n] output setup with respect to MCK tDDKHCS ns 3
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
800 MT/s data rate 0.917 —
MCS[n] output hold with respect to MCK tDDKHCX ns 3
1600 MT/sdata rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/sdata rate 0.744 —
800 MT/s data rate 0.917 —
MCK to MDQS Skew tDDKHMH ns 4
>1066 MT/s data rate –0.245 0.245
800 MT/s data rate –0.375 0.375
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor72
NOTE
For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
ps 5
1600 MT/s data rate 200 —
1333 MT/s data rate 250 —
1200 MT/s data rate 275 —
1066 MT/s data rate 300 —
800 MT/s data rate 375 —
MDQ/MECC/MDM output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
ps 5
1600 MT/s data rate 200 —
1333 MT/s data rate 250 —
1200 MT/s data rate 275 —
1066 MT/s data rate 300 —
800 MT/s data rate 375 —
MDQS preamble tDDKHMP 0.9 × tMCK —ns—
MDQS post-amble tDDKHME 0.4 × tMCK 0.6 × tMCK ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the applicable chip reference manual for a description and explanation of
the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol1Min Max Unit Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 73
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement
(tDDKHMH).
Figure 10. tDDKHMH timing diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
Figure 11. DDR3 and DDR3L output timing diagram
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKHMH(max)
tDDKHMH(min)
MDQS[n]
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX, tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMH
tDDKHMP
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor74
This figure provides the AC test load for the DDR3 and DDR3L controller bus.
Figure 12. DDR3 and DDR3L controller bus AC test load
2.10 eSPI
This section describes the DC and AC electrical specifications for the eSPI interface.
2.10.1 eSPI DC electrical characteristics
This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3 V.
This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 2.5 V.
Table 26. eSPI DC electrical characteristics (CVDD = 3.3 V)1,2
For recommended operating conditions, see Tab l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8V 1
Input current (VIN = 0 V or VIN = CVDD)I
IN —±40μA2
Output high voltage
(CVDD = min, IOH = –2 mA)
VOH 2.4 — V —
Output low voltage
(CVDD = min, IOL = 2 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Ta b l e 3 .
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 27. eSPI DC electrical characteristics (CVDD = 2.5 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7 V 1
Input current (VIN = 0 V or VIN = CVDD)I
IN —±40μA2
Output high voltage
(CVDD = min, IOH = –1 mA)
VOH 2.0 — V —
Output low voltage
(CVDD = min, IOL = 1 mA)
VOL —0.4 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Ta b le 3 .
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Output Z0 = 50 Ω
RL = 50 Ω
GVDD/2
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 75
This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8 V.
2.10.2 eSPI AC timing specifications
This table provides the eSPI input and output AC timing specifications.
Table 28. eSPI DC electrical characteristics (CVDD = 1.8 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL —0.6V1
Input current (VIN = 0 V or VIN = CVDD)I
IN —±40μA2
Output high voltage
(CVDD = min, IOH = –0.5 mA)
VOH 1.35 — V —
Output low voltage
(CVDD = min, IOL = 0.5 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Ta b le 3 .
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 29. eSPI AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol1Min Max Unit Note
SPI_MOSI output—Master data (internal clock) hold time tNIKHOX 2.36 +
(tPLATFORM_CLK *SP
MODE[HO_ADJ])
—
—
ns 2, 3
SPI_MOSI output—Master data (internal clock) delay tNIKHOV — 5.24 +
(tPLATFORM_CLK *
SPMODE[HO_ADJ])
ns 2, 3
SPI_CS outputs—Master data (internal clock) hold time tNIKHOX2 0—ns2
SPI_CS outputs—Master data (internal clock) delay tNIKHOV2 —6.0ns2
eSPI inputs—Master data (internal clock) input setup time tNIIVKH 5—ns—
eSPI inputs—Master data (internal clock) input hold time tNIIXKH 0—ns—
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid
(V).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
3. See the applicable chip reference manual for details on the SPMODE register.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor76
This figure provides the AC test load for the eSPI.
Figure 13. eSPI AC test load
This figure represents the AC timing from Table 29 in master mode (internal clock). Note that although timing specifications
generally refer to the rising edge of the clock, this figure also applies when the falling edge is the active edge. Also, note that
the clock edge is selectable on eSPI.
Figure 14. eSPI AC timing in master mode (Internal Clock) diagram
2.11 DUART
This section describes the DC and AC electrical specifications for the DUART interface.
2.11.1 DUART DC electrical characteristics
This table provides the DC electrical characteristics for the DUART interface.
Table 30. DUART DC electrical characteristics (OVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2—V1
Input low voltage VIL —0.8V1
Output Z0 = 50 ΩCVDD/2
RL = 50 Ω
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO1
Output Signals:
SPIMOSI1
tNIIVKH
tNIKHOX
Output Signals:
SPI_CS[0:3]1
tNIKHOV2
t
NIKHOX2
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 77
2.11.2 DUART AC electrical specifications
This table provides the AC timing parameters for the DUART interface.
2.12 Ethernet: data path three-speed Ethernet (dTSEC),
management interface, IEEE Std 1588
This section provides the AC and DC electrical characteristics for the data path three-speed Ethernet controller, the Ethernet
management interface, and the IEEE Std 1588 interface.
2.12.1 SGMII timing specifications
See Section 2.20.8, “SGMII interface.”
2.12.2 MII and RGMII timing specifications
This section discusses the electrical characteristics for the MII and RGMII interfaces.
Input current (OVIN = 0 V or OVIN = OVDD)I
IN — ±40 μA2
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —
Output low voltage (OVDD = min, IOL = 2 mA) VOL —0.4V—
Notes:
1. The symbol OVIN, in this case, represents the OVIN symbol referenced in Ta bl e 3 .
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 31. DUART AC timing specifications
For recommended operating conditions, see Ta bl e 3.
Parameter Value Unit Notes
Minimum baud rate fPLAT/(2*1,048,576) baud 1
Maximum baud rate fPLAT/(2*16) baud 1,2
Oversample rate 16 — 3
Notes:
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
Table 30. DUART DC electrical characteristics (OVDD = 3.3 V) (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor78
2.12.2.1 MII and RGMII DC electrical characteristics
This table shows the MII DC electrical characteristics when operating at LVDD = 3.3 V supply.
This table shows the MII and RGMII DC electrical characteristics when operating at LVDD = 2.5 V supply.
2.12.2.2 MII AC timing specifications
This section describes the MII transmit and receive AC timing specifications.
Table 32. MII DC electrical characteristics (LVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.90V—
Input high current (VIN = LVDD)I
IH —40μA2
Input low current (VIN = GND) IIL –600 — μA2
Output high voltage (LVDD = min, IOH = –4.0 mA) VOH 2.4 LVDD + 0.3 V —
Output low voltage (LVDD = min, IOL = 4.0 mA) VOL GND 0.50 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3 .
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Ta b l e 2 and Ta b l e 3 .
Table 33. MII and RGMII DC electrical characteristics (LVDD = 2.5 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7V1
Input current (LVIN = 0 V or LVIN = LVDD)I
IH —±40μA2
Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.0 — V —
Output low voltage (LVDD =min, I
OL = 1.0 mA) VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3 .
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Ta b l e 2 and Ta b l e 3 .
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 79
This table provides the MII transmit AC timing specifications.
This figure shows the MII transmit AC timing diagram.
Figure 15. MII transmit AC timing diagram
This table provides the MII receive AC timing specifications.
Table 34. MII transmit AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit
TX_CLK clock period 10 Mbps tMTX 399.96 400 400.04 ns
TX_CLK clock period 100 Mbps tMTX 39.996 40 40.004 ns
TX_CLK duty cycle tMTXH/tMTX 35 — 65 %
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 0 — 25 ns
TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns
TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns
Table 35. MII Receive AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit
RX_CLK clock period 10 Mbps tMRX 399.96 400 400.04 ns
RX_CLK clock period 100 Mbps tMRX 39.996 40 40.004 ns
RX_CLK duty cycle tMRXH/tMRX 35 — 65 %
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns
RX_CLK clock rise (20%-80%) tMRXR 1.0 — 4.0 ns
RX_CLK clock fall time (80%-20%) tMRXF 1.0 — 4.0 ns
Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor80
This figure provides the AC test load for eTSEC.
Figure 16. eTSEC AC test load
This figure shows the MII receive AC timing diagram.
Figure 17. MII Receive AC timing diagram
2.12.2.3 RGMII AC timing specifications
This table presents the RGMII AC timing specifications.
Table 36. RGMII AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol1Min Typ Max Unit Notes
Data to clock output skew (at transmitter) tSKRGT_TX –500 0 500 ps 5
Data to clock input skew (at receiver) tSKRGT_RX 1.0 — 2.6 ns 2
Clock period duration tRGT 7.2 8.0 8.8 ns 3
Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4
Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % —
Rise time (20%–80%) tRGTR — — 0.75 ns —
Output Z0 = 50 ΩLVDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 81
This figure shows the RGMII AC timing and multiplexing diagrams.
Figure 18. RGMII AC timing and multiplexing diagrams
2.12.3 Ethernet management interface
This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces. EMI1 is the PHY management interface
controlled by the MDIO controller associated with Frame Manager 1 1GMAC-1. EMI2 is the XAUI PHY management interface
controlled by the MDIO controller associated with Frame Manager 1 10GMAC-0.
Fall time (20%–80%) tRGTF — — 0.75 ns —
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.
Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The tSKRGT_RX specification implies that PC board design requires clocks to be routed such that an additional trace delay of
greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay
inside their chip. If so, additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speeds transitioned
between.
5. The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.
Table 36. RGMII AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol1Min Typ Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor82
2.12.3.1 Ethernet management interface 1 DC electrical characteristics
The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the
Ethernet management interface is provided in this table.
The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the
Ethernet management interface 1 is provided in Table 37.
2.12.3.2 Ethernet management interface 2 DC electrical characteristics
Ethernet management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.
LVDD must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and EMI2_MDC are provided
in this section.
Table 37. Ethernet management Interface 1 DC electrical characteristics (LVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Note
Input high voltage VIH 2.0 — V 2
Input low voltage VIL —0.9 V 2
Input high current (LVDD = Max, VIN = 2.1 V) IIH —40μA1
Input low current (LVDD = Max, VIN = 0.5 V) IIL –600 — μA1
Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V —
Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL —0.4 V —
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Ta b l e 2 and Ta b l e 3 .
2. The min VIL and max VIH values are based on the respective LVIN values found in Ta bl e 3 .
Table 38. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5 V)
For recommended operating conditions, see Ta bl e 3 .
Parameter Symbol Min Max Unit Note
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7 V 1
Input current (LVIN = 0 V or LVIN = LVDD)I
IH —±40μA2
Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V —
Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL —0.4 V —
Note:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Ta b le 3 .
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Max Unit Note
Input high voltage VIH 0.84 — V —
Input low voltage VIL —0.36V—
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 83
2.12.3.3 Ethernet management interface 1 AC timing specifications
This table provides the Ethernet management interface 1 AC timing specifications.
2.12.3.4 Ethernet management interface 2 AC electrical characteristics
This table provides the Ethernet management interface 2 AC timing specifications.
Output low voltage (IOL = 100 μA) VOL —0.2V—
Output low current (VOL = 0.2 V) IOL 4—mA—
Input capacitance CIN —10pF—
Table 40. Ethernet management interface 1 AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol1Min Typ Max Unit Note
MDC frequency fMDC ——2.5MHz2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO delay tMDKHDX (16 ×tplb_clk) – 6 — (16 × tplb_clk) + 6 ns 3, 4
MDIO to MDC setup time tMDDVKH 8——ns—
MDIO to MDC hold time tMDDXKH 0——ns—
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)
reaching the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods
±6 ns. For example, with a frame manager clock of 333 MHz, the min/max delay is 48 ns ± 6 ns. Similarly, if the frame
manager clock is 400 MHz, the min/max delay is 40 ns ± 6 ns.
4. tplb_clk is the frame manager clock period.
Table 41. Ethernet management interface 2 AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter/Condition Symbol1Min Typ Max Unit Note
MDC frequency fMDC ——2.5MHz2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO delay tMDKHDX (0.5 ×(1/fMDC)) – 6 — (0.5 ×(1/fMDC)) + 6 ns 3
MDIO to MDC setup time tMDDVKH 8——ns—
Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) (continued)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Max Unit Note
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor84
This figure shows the Ethernet management interface timing diagram.
Figure 19. Ethernet management interface timing diagram
2.12.4 eTSEC IEEE Std 1588 timing specifications
This section discusses the electrical characteristics for the eTSEC IEEE Std 1588 interfaces.
2.12.4.1 eTSEC IEEE Std 1588 DC electrical characteristics
This table shows eTSEC IEEE Std 1588 DC electrical characteristics when operating at LVDD = 3.3 V supply.
MDIO to MDC hold time tMDDXKH 0——ns—
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach
the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data
clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns.
Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 2
Input low voltage VIL —0.9 V 2
Input high current (LVDD = Max, VIN = 2.1 V) IIH —40μA1
Table 41. Ethernet management interface 2 AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter/Condition Symbol1Min Typ Max Unit Note
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
MDIO
(Input)
(Output)
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 85
2.12.4.2 eTSEC IEEE Std 1588 AC specifications
This table provides the IEEE 1588 AC timing specifications.
Input low current (LVDD = Max, VIN = 0.5 V) IIL –600 — μA1
Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V —
Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL —0.4 V —
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Tab l e 2 and Ta b l e 3 .
2. The min VIL and max VIH values are based on the respective LVIN values found in Ta bl e 3 .
Table 43. eTSEC IEEE 1588 AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Unit Notes
TSEC_1588_CLK clock period tT1588CLK 3.3 — TRX_CLK ×7ns 1, 2
TSEC_1588_CLK duty cycle tT1588CLKH/
tT1588CLK
40 50 60 % 3
TSEC_1588_CLK peak-to-peak jitter tT1588CLKINJ — — 250 ps —
Rise time eTSEC_1588_CLK (20%–80%) tT1588CLKINR 1.0 — 2.0 ns —
Fall time eTSEC_1588_CLK (80%–20%) tT1588CLKINF 1.0 — 2.0 ns —
TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2×tT1588CLK ——ns—
TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/
tT1588CLKOUT
30 50 70 % —
TSEC_1588_PULSE_OUT tT1588OV 0.5 — 3.0 ns —
TSEC_1588_TRIG_IN pulse width tT1588TRIGH 2×tT1588CLK_MAX ——ns2
Notes:
1.TRX_CLK is the maximum clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated
Processor Reference Manual for a description of TMR_CTRL registers.
2. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK be 2800, 280, and 56 ns, respectively.
3. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated
Processor Reference Manual for a description of TMR_CTRL registers.
Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V) (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor86
This figure shows the data and command output AC timing diagram.
Figure 20. eTSEC IEEE 1588 output AC timing
This figure shows the data and command input AC timing diagram.
Figure 21. eTSEC IEEE 1588 input AC timing
2.13 USB
This section provides the AC and DC electrical specifications for the USB interface.
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
tT1588OV
tT1588CLKOUT
tT1588CLKOUTH
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it
is counted starting at the falling edge.
TSEC_1588_TRIG_IN
tT1588TRIGH
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 87
2.13.1 USB DC electrical characteristics
This table provides the DC electrical characteristics for the USB interface at USB_VDD_3P3 = 3.3 V.
2.13.2 USB AC electrical specifications
This table provides the USB clock input (USBn_CLKIN) AC timing specifications.
This figure provides the USB AC test load.
Figure 22. USB AC test load
2.14 Enhanced local bus interface (eLBC)
This section describes the DC and AC electrical specifications for the enhanced local bus interface.
Table 44. USB DC electrical characteristics (USB_VDD_3P3 = 3.3 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Notes
Input high voltage1VIH 2.0 — V 1
Input low voltage VIL —0.8V1
Input current (USB_VIN_3P3 = 0 V or USB_VIN_3P3 =
USB_VDD_3P3)
IIN —±40 μA2
Output high voltage (USB_VDD_3P3 = min, IOH = –2 mA) VOH 2.8 — V —
Output low voltage (USB_VDD_3P3 = min, IOL = 2 mA) VOL —0.3V—
Notes:
1. The min VILand max VIH values are based on the respective min and max USB_VIN_3P3 values found in Ta bl e 3 .
2. The symbol USB_VIN_3P3, in this case, represents the USB_VIN_3P3 symbol referenced in Section 2.1.2, “Recommended
operating conditions.”
Table 45. USBn_CLKIN AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter/Condition Conditions Symbol Min Typ Max Unit
Frequency range — fUSB_CLK_IN —24—MHz
Clock frequency tolerance — tCLK_TOL –0.005 0 0.005 %
Reference clock duty cycle Measured at 1.6 V tCLK_DUTY 40 50 60 %
Total input jitter/time interval
error
Peak-to-peak value measured with a
second-order high-pass filter of 500 kHz
bandwidth
tCLK_PJ —— 5 ps
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor88
2.14.1 Enhanced local bus DC electrical characteristics
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 3.3 V.
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 2.5 V.
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 1.8 V.
Table 46. Enhanced local bus DC electrical characteristics (BVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8V 1
Input current (VIN = 0 V or VIN = BVDD)I
IN —±40μA2
Output high voltage
(BVDD = min, IOH = –2 mA)
VOH 2.4 — V —
Output low voltage
(BVDD = min, IOL = 2 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Ta b l e 3 .
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 47. Enhanced local bus DC electrical characteristics (BVDD = 2.5 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7V1
Input current (VIN = 0 V or VIN = BVDD)I
IN —±40μA2
Output high voltage
(BVDD = min, IOH = –1 mA)
VOH 2.0 — V —
Output low voltage
(BVDD = min, IOL = 1 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Ta bl e 3
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL —0.6V1
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 89
2.14.2 Enhanced local bus AC timing specifications
This section describes the AC timing specifications for the enhanced local bus interface.
2.14.2.1 Test condition
This figure provides the AC test load for the enhanced local bus.
Figure 23. Enhanced local bus AC test load
2.14.2.2 Local bus AC timing specification
All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the
LCLKs to latch the data.
All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are relative
to the falling edge of LCLKs.
This table describes the timing specifications of the local bus interface.
Input current (VIN = 0 V or VIN = BVDD)I
IN —±40μA2
Output high voltage
(BVDD = min, IOH = –0.5 mA)
VOH 1.35 — V —
Output low voltage
(BVDD = min, IOL = 0.5 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Ta bl e 3 .
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 49. Enhanced local bus timing specifications
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol1Min Max Unit Notes
Local bus cycle time tLBK 10 — ns —
Local bus duty cycle tLBKH/tLBK 45 55 % —
LCLK[n] skew to LCLK[m] tLBKSKEW —150 ps2
Input setup
(except LGTA/LUPWAIT/LFRB)
tLBIVKH 6— ns—
Input hold
(except LGTA/LUPWAIT/LFRB)
tLBIXKH 1— ns—
Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) (continued)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Max Unit Notes
Output Z0 = 50 ΩBVDD/2
RL = 50 Ω
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor90
Input setup
(for LGTA/LUPWAIT/LFRB)
tLBIVKL 6— ns—
Input hold
(for LGTA/LUPWAIT/LFRB)
tLBIXKL 1— ns—
Output delay
(Except LALE)
tLBKLOV —1.5 ns—
Output hold
(Except LALE)
tLBKLOX -3.5 — ns 5
Local bus clock to output high impedance
for LAD/LDP
tLBKLOZ —2 ns3
LALE output negation to LAD/LDP output
transition (LATCH hold time)
tLBONOT 2 platform clock
cycles—1ns
(LBCR[AHD]=1)
—ns4
4 platform clock
cycles—1ns
(LBCR[AHD]=0)
—
Notes:
1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.
2. Skew measured between different LCLKs at BVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not
the external LCLK. LCLK cycle = eLBC controller clock cycle X LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to
0 and eLBC runs at maximum hold time.
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
Table 49. Enhanced local bus timing specifications (continued)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol1Min Max Unit Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 91
This figure shows the AC timing diagram of the local bus interface.
Figure 24. Enhanced local bus signals
Figure 25 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the local bus AC timing data is used directly for all three controllers.
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKLOV
.
Output Signals
tLBKLOX
LCLK[m]
Input Signals
LALE
tLBIXKH
tLBIVKH
tLBIVKL
tLBIXKL
Input Signal
tLBONOT
(LGTA/LUPWAIT/LFRB)
(Except LGTA/LUPWAIT/LFRB)
(Except LALE)
LAD
(address phase)
LAD/LDP
(data phase)
tLBKLOZ
tLBKLOV
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor92
This figure shows how the local bus AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.
Figure 25. GPCM Output timing diagram
2.15 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
2.15.1 eSDHC DC electrical characteristics
This table provides the DC electrical characteristics for the eSDHC interface.
Table 50. eSDHC interface DC electrical characteristics
For recommended operating conditions, see Ta b l e 3 .
Characteristic Symbol Condition Min Max Unit Notes
Input high voltage VIH —0.625×CVDD —V1
Input low voltage VIL — — 0.25 ×CVDD V1
Input/output leakage current IIN/IOZ —–5050μA—
Output high voltage VOH IOH = –100 μA at
CVDD min
0.75 × CVDD —V—
tarcs +t
LBKLOV
LCLK
LAD[0:31]
LBCTL
tLBONOT
LCS_B
LGPL2/LOE_B
address
taddr
taoe +t
LBKLOV
LWE_B
tawcs +t
LBKLOV
tLBONOT
address
taddr
tawe +t
LBKLOV
tLBKLOX
t
rc
toen
read data write data
twen
twc
write
read
LALE
1taddr is programmable and determined by LCRR[EADC] and ORx[EAD].
2tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the applicable chip reference manual.
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 93
2.15.2 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 26 and Figure 27.
Output low voltage VOL IOL = 100μA at
CVDD min
—0.125 × CVDD V—
Output high voltage VOH IOH = –100 μA at
CVDD min
CVDD –0.2 — V 2
Output low voltage VOL IOL = 2 mA at
CVDD min
—0.3V2
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Tab l e 3 .
2. Open drain mode for MMC cards only.
Table 51. eSDHC AC timing specifications
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol1Min Max Unit Notes
SD_CLK clock frequency:
SD Full speed/high speed mode
MMC Full speed/high speed mode
fSHSCK
0 25/50
20/52
MHz 2, 4
SD_CLK clock low time—Full-speed/High-speed mode tSHSCKL 10/7 — ns 4
SD_CLK clock high time—Full-speed/High-speed mode tSHSCKH 10/7 — ns 4
SD_CLK clock rise and fall times tSHSCKR/
tSHSCKF
—3ns4
Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIVKH 5 — ns 3, 4, 5
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 2.5 — ns 4, 5
Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV –3 3 ns 4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD card and 0–20 MHz for an MMC card. In high-speed
mode, the clock frequency value can be 0–50 MHz for an SD card and 0–52 MHz for an MMC card.
3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not
exceed 1 ns. For any high speed or default speed mode SD card, the oneway routing delay between Host and Card on
SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.
4. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST +C
CARD ≤ 40 pF
5. The parameter values apply to both full speed and high speed modes.
Table 50. eSDHC interface DC electrical characteristics (continued)
For recommended operating conditions, see Ta b l e 3 .
Characteristic Symbol Condition Min Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor94
This figure provides the eSDHC clock input timing diagram.
Figure 26. eSDHC clock input timing diagram
This figure provides the data and command input/output timing diagram.
Figure 27. eSDHC data and command input/output timing diagram referenced to clock
2.16 Multicore programmable interrupt controller (MPIC)
specifications
This section describes the DC and AC electrical specifications for the multicore programmable interrupt controller.
2.16.1 MPIC DC specifications
This table provides the DC electrical characteristics for the MPIC interface.
Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8 V 1
Input current (OVIN = 0 V or OVIN = OVDD)I
IN —±40 μA2
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —
eSDHC
tSHSCKR
External Clock VMVMVM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode tSHSCKL tSHSCKH
VM = Midpoint Voltage (OVDD/2)
SD_CK
External Clock
SD_DAT/CMD
VM VM VM VM
Inputs
SD_DAT/CMD
Outputs
tSHSIVKH tSHSIXKH
tSHSKHOV
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 95
2.16.2 MPIC AC timing specifications
This table provides the MPIC input and output AC timing specifications.
2.17 JTAG controller
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface.
2.17.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics.
Output low voltage (OVDD = min, IOL = 2 mA) VOL —0.4 V —
Notes:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Ta b l e 3
Table 53. MPIC Input AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Characteristic Symbol Min Max Unit Notes
MPIC inputs—minimum pulse width tPIWID 3 — SYSCLKs 1
Notes:
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs should be synchronized before use by any
external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode
Table 54. JTAG DC electrical characteristics (OVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8 V 1
Input current (OVIN = 0 V or OVIN = OVDD)I
IN —±40 μA2
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —
Output low voltage (OVDD = min, IOL = 2 mA) VOL —0.4 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3 .
2. The symbol VIN, in this case, represents the OVIN symbol found in Ta b l e 3 .
Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V) (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor96
2.17.2 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31.
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 28. AC test load for the JTAG interface
Table 55. JTAG AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol1Min Max Unit Notes
JTAG external clock frequency of operation fJTG 033.3MHz—
JTAG external clock cycle time tJTG 30 — ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —
JTAG external clock rise and fall times tJTGR/tJTGF 02ns—
TRST assert time tTRST 25 — ns 2
Input setup times tJTDVKH
14
—ns—
Boundary-scan USB only
Boundary-scan except USB 4
TMS 4
TDI 5
Input hold times tJTDXKH 10 — ns —
Output valid times tJTKLDV —
Boundary-scan data 15 ns 3
TDO 10 ns —
Output hold times tJTKLDX 0—ns3
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to
the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must
be added for trace lengths, vias, and connectors in the system.
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 97
This figure provides the JTAG clock input timing diagram.
Figure 29. JTAG clock input timing diagram
This figure provides the TRST timing diagram.
Figure 30. TRST timing diagram
This figure provides the boundary-scan timing diagram.
Figure 31. Boundary-scan timing diagram
2.18 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
JTAG
tJTKHKL tJTGR
External Clock VMVMVM
tJTG tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM VM
tTRST
VM = Midpoint Voltage (OVDD/2)
VM VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDV
Input
Data Valid
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor98
2.18.1 I2C DC electrical characteristics
This table provides the DC electrical characteristics for the I2C interfaces.
2.18.2 I2C AC electrical specifications
This table provides the AC timing parameters for the I2C interfaces.
Table 56. I2C DC electrical characteristics (OVDD = 3.3 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8V1
Output low voltage (OVDD = min, IOL = 2 mA) VOL 00.4V2
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL 050ns3
Input current each I/O pin (input voltage is between
0.1 ×OVDD and 0.9 × OVDD(max)
II–40 40 μA4
Capacitance for each I/O pin CI010pF—
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Ta b l e 3 .
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the applicable chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
Table 57. I2C AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol1Min Max Unit Notes
SCL clock frequency fI2C 0400kHz2
Low period of the SCL clock tI2CL 1.3 — μs—
High period of the SCL clock tI2CH 0.6 — μs—
Setup time for a repeated START condition tI2SVKH 0.6 — μs—
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
tI2SXKL 0.6 — μs—
Data setup time tI2DVKH 100 — ns —
Data input hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
—
0
—
—
μs3
Data output delay time tI2OVKL —0.9μs4
Setup time for STOP condition tI2PVKH 0.6 — μs—
Bus free time between a STOP and START condition tI2KHDX 1.3 — μs—
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 99
This figure provides the AC test load for the I2C.
Figure 32. I2C AC test load
This figure shows the AC timing diagram for the I2C bus.
Figure 33. I2C bus AC timing diagram
Noise margin at the LOW level for each connected
device (including hysteresis)
VNL 0.1 × OVDD —V—
Noise margin at the HIGH level for each connected
device (including hysteresis)
VNH 0.2 × OVDD —V—
Capacitive load for each bus line Cb — 400 pF —
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When
the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are
balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time
is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter,
application note AN2919 referred to in note 2 above is recommended.
4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
Table 57. I2C AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol1Min Max Unit Notes
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
SrS
SDA
SCL
tI2SXKL
tI2CL
tI2CH
tI2DXKL,tI2OVKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
PS
tI2KHDX
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor100
2.19 GPIO
This section describes the DC and AC electrical characteristics for the GPIO interface.
2.19.1 GPIO DC electrical characteristics
This table provides the DC electrical characteristics for GPIO pins operating at 3.3 V.
This table provides the DC electrical characteristics for GPIO pins operating at LVDD = 2.5 V.
Table 58. GPIO DC electrical characteristics (LVDD or OVDD = 3.3 V)
For recommended operating conditions, see Ta bl e 3 .
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 — V 1
Input low voltage VIL —0.8 V 1
Input current (OVIN = 0 V or OVIN = OVDD)I
IN —±40μA2
Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V —
Output low voltage (OVDD = min, IOL = 2 mA) VOL —0.4 V —
Notes:
1. The min VILand max VIH values are based on the min and max L/OVIN respective values found in Ta b l e 3 .
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Table 59. GPIO DC electrical characteristics (LVDD = 2.5 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7V1
Input current (VIN = 0 V or VIN = LVDD)I
IN —±40μA2
Output high voltage
(LVDD = min, IOH = –2 mA)
VOH 2.0 — V —
Output low voltage
(LVDD = min, IOH = 2 mA)
VOL —0.4V—
Notes:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Ta b l e 3 .
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 101
2.19.2 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications.
This figure provides the AC test load for the GPIO.
Figure 34. GPIO AC test load
2.20 High-speed serial interfaces (HSSI)
The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, XAUI, Aurora and SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference
clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.20.1 Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
Table 60. GPIO Input AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Unit Notes
GPIO inputs—minimum pulse width tPIWID 20 ns 1
Trust inputs—minimum pulse width tTIWID 3 SYSCLK 2
Note:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
2. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least tTIWID to ensure proper
operation. For low power trust input pin LP_TMP_DETECT, the voltage is VDD_LP and see Table 3 .for the voltage
requirement.
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor102
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This
figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn) or a receiver input (SD_RXn and SD_RXn).
Each signal swings between A volts and B volts where A > B.
Figure 35. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that
the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:
Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn, SD_TXn, SD_RXn and
SD_RXn each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s
single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of
the two complementary output voltages: VSD_TXn – VSD_TXn. The VOD value can be either
positive or negative.
Differential Input Voltage, VID (or Differential Input Swing):
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complementary input voltages: VSD_RXn – VSD_RXn. The VID value can be either positive or
negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as the differential peak voltage, VDIFFp = |A – B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p = 2 ×VDIFFp = 2 ×|(A – B)| volts, which is twice the differential swing in amplitude, or
twice of the differential peak. For example, the output differential peak-peak voltage can also be
calculated as VTX-DIFFp-p = 2 ×|VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TXn, for
example) from the non-inverting signal (SD_TXn, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
Differential Swing, VID or VOD = A – B
A Volts
B Volts
SD_TXn or
SD_RXn
SD_TXn or
SD_RXn
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2 ×VDIFFp (not shown)
Vcm = (A + B)/2
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 103
waveform is not referenced to ground. See Figure 40, “Differential measurement points for rise
and fall time,” as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(V
SD_TXn+V
SD_TXn)÷2 = (A + B) ÷2, which is the arithmetic mean of the two
complementary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has
the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.
In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.
The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.20.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2
and SD_REF_CLK2 for SerDes bank2, SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3, and SD_REF_CLK4 and
SD_REF_CLK4 for SerDes bank4.
SerDes banks 1–4 may be used for various combinations of the following IP blocks based on the RCW Configuration field
SRDS_PRTCL:
• SerDes bank 1: PEX1/2/3, SGMII (1.25 Gbps only) or Aurora.
• SerDes bank 2: SGMII (1.25 or 3.125 GBaud) or XAUI.
• SerDes bank 3: SATA, or XAUI.
• SerDes bank 4: SATA
The following sections describe the SerDes reference clock requirements and provide application information.
2.20.2.1 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks.
Figure 36. Receiver of SerDes reference clocks
Input
Amp
50 Ω
50 Ω
SD_REF_CLKn
SD_REF_CLKn
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor104
The characteristics of the clock signals are as follows:
• The SerDes transceivers core power supply voltage requirements (SVDD) are as specified in Section 2.1.2,
“Recommended operating conditions.”
• The SerDes reference clock receiver reference circuit structure is as follows:
—The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in Figure 36.
Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-Ω termination to SGND
followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and
single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50 Ω to SGND DC or the drive
strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
2.20.2.2 DC-level requirement for SerDes reference clocks
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver
characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) as between 100 mV and 400 mV. Figure 37 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
Figure 37. Differential reference clock input DC requirements (external DC-coupled)
SD_REF_CLKn
SD_REF_CLKn
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 105
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock
receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing
below and above the common mode voltage (SGND). Figure 38 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Figure 38. Differential reference clock input DC requirements (external AC-coupled)
• Single-Ended Mode
— The reference clock can also be single-ended. The SD_REF_CLKn input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLKn either left unconnected or
tied to ground.
— The SD_REF_CLKn input average voltage must be between 200 and 400 mV. Figure 39 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SD_REF_CLKn) through the same source impedance as the clock input (SD_REF_CLKn) in use.
Figure 39. Single-ended reference clock input DC requirements
SD_REF_CLKn
SD_REF_CLKn
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD_REF_CLKn
SD_REF_CLKn
400 mV < SD_REF_CLKn Input Amplitude < 800 mV
0V
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor106
2.20.2.3 AC requirements for SerDes reference clocks
This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be
guaranteed by the customer’s application design.
Figure 40. Differential measurement points for rise and fall time
Table 61. SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit Notes
SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 100/125 — MHz 1
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance
tCLK_TOL –350 — 350 ppm —
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle
tCLK_DUTY 40 50 60 % 4
SD_REF_CLK/SD_REF_CLK max deterministic
peak-peak jitter at 10-6 BER
tCLK_DJ — — 42 ps —
SD_REF_CLK/SD_REF_CLK total reference clock
jitter at 10-6 BER (peak-to-peak jitter at refClk input)
tCLK_TJ — — 86 ps 2
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1—4V/ns3
Differential input high voltage VIH 200 — — mV 4
Differential input low voltage VIL — — –200 mV 4
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Rise-Fall
Matching
——20%5, 6
Notes:
1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 40.
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 41.
VIH = +200 mV
VIL = –200 mV
0.0 V
SD_REF_CLKn –
SD_REF_CLKn
Fall Edge RateRise Edge Rate
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 107
Figure 41. Single-ended measurement points for rise and fall time matching
2.20.2.4 Spread-spectrum clock
SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock and the industry protocol specifications supports it. For better
results, a source without significant unintended modulation should be used.
SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
SD_REF_CLK4/SD_REF_CLK4 are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 42. SerDes transmitter and receiver reference circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application
usage:
•Section 2.20.4, “PCI Express”
•Section 2.20.5, “XAUI”
•Section 2.20.6, “Aurora”
•Section 2.20.7, “Seri al ATA (SATA )
•Section 2.20.8, “SGMII interface”
Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard
requirements.
SDn_REF_CLK SDn_REF_CLKSDn_REF_CLK
SDn_REF_CLKSDn_REF_CLK
VCROSS MEDIAN VCROSS MEDIAN
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN – 100 mV
TFALL TRISE
50 Ω
50 ΩReceiver
Transmitter
SD_TXn
SD_TXnSD_RXn
SD_RXn
50 Ω
50 Ω
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor108
2.20.4 PCI Express
This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.
2.20.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
2.20.4.2 PCI Express clocking requirements for SD_REF_CLKn and
SD_REF_CLKn
SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations
based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.4.3 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.3.1 PCI Express DC physical layer transmitter specifications
This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications
(XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3 .
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p 800 — 1200 mV VTX-DIFFp-p = 2 ×|VTX-D+ – VTX-D-| See Note 1.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
DC differential transmitter
impedance
ZTX-DIFF-DC 80 100 120 ΩTransmitter DC differential mode low Impedance
Transmitter DC impedance ZTX-DC 40 50 60 ΩRequired transmitter D+ as well as D– DC
Impedance during all states
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 109
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
2.20.4.4 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications
(XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p 800 — 1200 mV VTX-DIFFp-p = 2 ×|VTX-D+ – VTX-D-| See Note 1.
Low Power differential
peak-to-peak output voltage
VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 ×|VTX-D+ – VTX-D-| See Note 1.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
DC differential transmitter
impedance
ZTX-DIFF-DC 80 100 120 ΩTransmitter DC differential mode low
impedance
Transmitter DC Impedance ZTX-DC 40 50 60 ΩRequired transmitter D+ as well as D– DC
impedance during all states
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak voltage VRX-DIFFp-p 120 — 1200 mV VRX-DIFFp-p = 2 ×|VRX-D+ – VRX-D-|
See Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 ΩReceiver DC differential mode
impedance.
See Note 2
DC input impedance ZRX-DC 40 50 60 ΩRequired receiver D+ as well as D–
DC Impedance (50 ±20%
tolerance).
See Notes 1 and 2.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor110
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 k — — ΩRequired receiver D+ as well as D–
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Electrical idle detect threshold VRX-IDLE-DET-DIFFp-p 65 — 175 mV VRX-IDLE-DET-DIFFp-p =
2×|VRX-D+ – VRX-D–|
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.
Table 65. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (XVDD = 1.5V or 1.8V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak voltage VRX-DIFFp-p 120 — 1200 V VRX-DIFFp-p = 2 ×|VRX-D+ – VRX-D–|
See Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 ΩReceiver DC Differential mode
impedance. See Note 2
DC input impedance ZRX-DC 40 50 60 ΩRequired receiver D+ as well as D–
DC Impedance (50 ±20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 — — kΩRequired receiver D+ as well as D–
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Electrical idle detect threshold VRX-IDLE-DET-DIFFp-p 65 — 175 mV VRX-IDLE-DET-DIFFp-p =
2×|VRX-D+ –V
RX-D–|
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.
Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V)
(continued)
Parameter Symbol Min Typ Max Units Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 111
2.20.4.5 PCI Express AC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.5.1 PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 66. PCI Express 2.0 (2.5 GT/s) differential transmitter Output AC specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Units Notes
Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum transmitter eye
width
TTX-EYE 0.75 — — UI The maximum transmitter jitter can be derived
as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
Does not include spread spectrum or RefCLK
jitter. Includes device random jitter at 10-12.
See Notes 2 and 3.
Maximum time between the
jitter median and maximum
deviation from the median
TTX-EYE-MEDIAN-
to-
MAX-JITTER
— — 0.125 UI Jitter is defined as the measurement variation
of the crossing points (VTX-DIFFp-p = 0 V) in
relation to a recovered transmitter UI. A
recovered transmitter UI is calculated over
3500 consecutive unit intervals of sample
data. Jitter is measured using all edges of the
250 consecutive UI in the center of the 3500 UI
used for calculating the transmitter UI.
See Notes 2 and 3.
AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself.
See Note 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of
the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not
the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor112
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
2.20.4.5.2 PCI Express AC physical layer receiver specifications
This section discusses the PCI Express AC physical layer receiver specifications 2.5 GT/s, and 5 GT/s.
Table 67. PCI Express 2.0 (5 GT/s) differential transmitter Output AC specifications
For recommended operating conditions, see Ta bl e 3 .
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum transmitter eye width TTX-EYE 0.75 — — UI The maximum transmitter jitter can be
derived as:
TTX-MAX-JITTER =1–T
TX-EYE =0.25 UI.
See Notes 2 and 3.
Transmitter RMS deterministic
jitter > 1.5 MHz
TTX-HF-DJ-DD — — 0.15 ps —
Transmitter RMS deterministic
jitter < 1.5 MHz
TTX-LF-RMS — 3.0 — ps Reference input clock RMS jitter (< 1.5 MHz)
at pin < 1 ps
AC coupling capacitor CTX 75 — 200 nF All transmitters must be AC coupled. The AC
coupling is required either within the media
or within the transmitting component itself.
See Note 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of
the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not
the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 113
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 68. PCI Express 2.0 (2.5 GT/s) differential receiver Input AC specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum receiver eye width TRX-EYE 0.4 — — UI The maximum interconnect media and
transmitter jitter that can be tolerated by the
receiver can be derived as
TRX-MAX-JITTER =1 – T
RX-EYE= 0.6 UI.
See Notes 2 and 3.
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-
to-MAX-JITTER
— — 0.3 UI Jitter is defined as the measurement
variation of the crossing points
(VRX-DIFFp-p = 0 V) in relation to a recovered
transmitter UI. A recovered transmitter UI is
calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the transmitter UI.
See Notes 2, 3 and 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used
as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It should be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter
UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
4. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor114
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
2.20.4.6 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 43.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.
Figure 43. Test/Measurement load
Table 69. PCI Express 2.0 (5 GT/s) differential receiver Input AC specifications
For recommended operating conditions, see Tabl e 3.
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 400 ps ±300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Max receiver inherent timing
error
TRX-TJ-CC — — 0.4 UI The maximum inherent total timing error for
common RefClk receiver architecture
Maximum time between the
jitter median and maximum
deviation from the median
TRX-TJ-DC — — 0.34 UI Max receiver inherent total timing error
Max receiver inherent
deterministic timing error
TRX-DJ-DD-CC — — 0.30 UI The maximum inherent deterministic timing
error for common RefClk receiver
architecture
Max receiver inherent
deterministic timing error
TRX-DJ-DD-DC — — 0.24 UI The maximum inherent deterministic timing
error for common RefClk receiver
architecture
Note:
1. No test load is necessarily associated with this value.
Transmitter
silicon
+ package
C = CTX
C = CTX
R = 50 ΩR = 50 Ω
D+ package pin
D– package pin
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 115
2.20.5 XAUI
This section describes the DC and AC electrical specifications for the XAUI bus.
2.20.5.1 XAUI DC electrical characteristics
This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver.
2.20.5.1.1 DC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations
based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.
For more information on these specifications, see Section 2.20.2.2, “DC-level requirement for SerDes reference clocks.”
2.20.5.1.2 XAUI transmitter DC electrical characteristics
This table defines the XAUI transmitter DC electrical characteristics.
2.20.5.1.3 XAUI receiver DC electrical characteristics
This table defines the XAUI receiver DC electrical characteristics.
2.20.5.2 XAUI AC timing specifications
This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver.
Table 70. XAUI transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typical Max Unit Notes
Output voltage VO–0.40 — 2.30 V 1
Differential output voltage VDIFFPP 800 — 1600 mV p-p —
Note:
1. Absolute output voltage limit
Table 71. XAUI receiver DC timing specifications (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 900 1600 mV p-p 1
Note:
1. Measured at the receiver.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor116
2.20.5.2.1 AC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may
be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported
on SerDes bank 1.
2.20.5.2.2 XAUI transmitter AC timing specifications
This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.
Table 72. XAUI AC SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typ Max Unit Notes
SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 125/
156.25
—MHz—
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance
tCLK_TOL –100 — 100 ppm —
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle
tCLK_DUTY 40 50 60 % 2
SD_REF_CLK/SD_REF_CLK cycle to cycle jitter
(period jitter at refClk input)
tCLK_CJ — — 100 ps —
SD_REF_CLK/SD_REF_CLK total reference clock
jitter (peak-to-peak phase jitter at refClk input)
tCLK_PJ -50 — 50 ps —
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1—4V/ns1
Differential input high voltage VIH 200 — — mV 2
Differential input low voltage VIL — — –200 mV 2
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Rise-Fall
Matching
——20%3, 4
Notes:
1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn – SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 40.
2. Measurement taken from differential waveform
3. Measurement taken from single-ended waveform
4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 41.
Table 73. XAUI transmitter AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter JD— — 0.17 UI p-p —
Total jitter JT— — 0.35 UI p-p —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 117
2.20.5.2.3 XAUI receiver AC timing specifications
This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.
This figure shows the single-frequency sinusoidal jitter limits.
Figure 44. Single-Frequency Sinusoidal Jitter Limits
Table 74. XAUI receiver AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD0.37 — — UI p-p 1
Combined deterministic and random
jitter tolerance
JDR 0.55 — — UI p-p 1
Total jitter tolerance JT0.65 — — UI p-p 1, 2
Bit error rate BER — — 10–12 ——
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
8.5 UI p-p
0.10 UI p-p
Sinusoidal
jitter
amplitude
22.1 kHz 1.875 MHz 20 MHzFrequency
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor118
2.20.6 Aurora
This section describes the Aurora clocking requirements and AC and DC electrical characteristics.
2.20.6.1 Aurora DC electrical characteristics
This section describes the DC electrical characteristics for Aurora.
2.20.6.1.1 Aurora DC clocking requirements for SD_REF_CLKn and SD_REF_CLKn
Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW
Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2-3.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.6.1.2 Aurora transmitter DC electrical characteristics
This table defines the Aurora transmitter DC electrical characteristics.
2.20.6.1.3 Aurora receiver DC electrical characteristics
This table defines the Aurora receiver DC electrical characteristics for Aurora.
2.20.6.2 Aurora AC timing specifications
This section describes the AC timing specifications for Aurora.
2.20.6.2.1 Aurora AC clocking requirements for SD_REF_CLKn and SD_REF_CLKn
Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW
Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2–3.
Please note that the XAUI clock requirements for SD_REF_CLKn and SD_REF_CLKn are intended to be used within the
clocking guidelines specified by either Section 2.20.2.3, “AC requirements for SerDes reference clocks” or Section 2.20.7.2.1,
“AC requirements for SATA REF_CLK.”
Table 75. Aurora transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3 .
Parameter Symbol Min Typical Max Unit
Differential output voltage VDIFFPP 800 — 1600 mV p-p
Table 76. Aurora receiver DC electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 120 900 1200 mV p-p 1
Note:
1. Measured at receiver
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 119
2.20.6.2.2 Aurora transmitter AC timing specifications
This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.
2.20.6.2.3 Aurora receiver AC timing specifications
This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included.
2.20.7 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface.
2.20.7.1 SATA DC electrical characteristics
This section describes the DC electrical characteristics for SATA.
Table 77. Aurora transmitter AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD— — 0.17 UI p-p
Total jitter JT— — 0.35 UI p-p
Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps
Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps
Table 78. Aurora receiver AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD0.37 — — UI p-p 1
Combined deterministic and random
jitter tolerance
JDR 0.55 — — UI p-p 1
Total jitter tolerance JT0.65 — — UI p-p 1,2
Bit error rate BER — — 10–12 ——
Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps —
Note:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor120
2.20.7.1.1 SATA DC transmitter Output Characteristics
This table provides the DC differential transmitter output DC characteristics for the transmission.
This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission.
2.20.7.1.2 SATA DC receiver Input Characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.
Table 79. Gen1i/1.5G transmitter DC specifications (XVDD = 1.5V or 1.8V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
Transmitter differential output
voltage
VSATA_TXDIFF 400 — 600 mV p-p 1
Transmitter differential pair
impedance
ZSATA_TXDIFFIM 85 100 115 Ω2
Notes:
1. Terminated by 50 Ω load
2. DC impedance
Table 80. Gen 2i/3G transmitter DC specifications (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Units Notes
Transmitter diff output voltage VSATA_TXDIFF 400 — 700 mV p-p 1
Transmitter differential pair
impedance
ZSATA_TXDIFFIM 85 100 115 Ω—
Note:
1. Terminated by 50 Ω load
Table 81. Gen1i/1.5 G receiver Input DC specifications (XVDD = 1.5V or 1.8V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typical Max Units Notes
Differential input voltage VSATA_RXDIFF 240 — 600 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω2
OOB signal detection threshold VSATA_OOB 50 120 240 mV p-p 2
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 121
This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.
2.20.7.2 SATA AC timing specifications
This section discusses the SATA AC timing specifications.
2.20.7.2.1 AC requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design.
Table 82. Gen2i/3 G receiver Input DC specifications (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Units Notes
Differential input voltage VSATA_RXDIFF 275 — 750 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω2
OOB signal detection threshold VSATA_OOB 75 120 240 mV p-p 2
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
Table 83. SATA reference clock input requirements
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Unit Notes
SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 100/125 — MHz 1
SD_REF_CLK/SD_REF_CLK clock frequency tolerance tCLK_TOL –350 — +350 ppm —
SD_REF_CLK/SD_REF_CLK reference clock duty cycle tCLK_DUTY 40 50 60 % 5
SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter (period jitter) tCLK_CJ — — 100 ps 2
SD_REF_CLK/SD_REF_CLK total reference clock jitter, phase jitter
(peak-peak)
tCLK_PJ –50 — +50 ps 2, 3, 4
Notes:
1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.
5. Measurement taken from differential waveform
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor122
This figure shows the reference clock timing waveform.
Figure 45. Reference clock timing waveform
2.20.7.3 AC transmitter Output Characteristics
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
Table 84. Gen1i/1.5 G transmitter AC specifications
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typ Max Units Notes
Channel speed tCH_SPEED —1.5—Gbps—
Unit Interval TUI 666.4333 666.6667 670.2333 ps —
Total jitter data-data 5 UI USATA_TXTJ5UI — — 0.355 UI p-p 1
Total jitter, data-data 250 UI USATA_TXTJ250UI — — 0.47 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_TXDJ5UI — — 0.175 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_TXDJ250UI — — 0.22 UI p-p 1
Note:
1. Measured at transmitter output pins peak to peak phase variation, random data pattern
Table 85. Gen 2i/3 G transmitter AC specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
Channel speed tCH_SPEED —3.0—Gbps—
Unit Interval TUI 333.2167 333.3333 335.1167 ps —
Total jitter fC3dB =f
BAUD ÷10 USATA_TXTJfB/10 ——0.3UI p-p1
Total jitter fC3dB =f
BAUD ÷500 USATA_TXTJfB/500 — — 0.37 UI p-p 1
Total jitter fC3dB =f
BAUD ÷1667 USATA_TXTJfB/1667 — — 0.55 UI p-p 1
TH
TL
Ref_CLK
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 123
2.20.7.4 AC differential receiver Input characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.
This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.
The AC timing specifications do not include RefClk jitter.
Deterministic jitter,
fC3dB =f
BAUD ÷10
USATA_TXDJfB/10 — — 0.17 UI p-p 1
Deterministic jitter,
fC3dB =f
BAUD ÷500
USATA_TXDJfB/500 — — 0.19 UI p-p 1
Deterministic jitter,
fC3dB =f
BAUD ÷1667
USATA_TXDJfB/1667 — — 0.35 UI p-p 1
Note:
1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern
Table 86. Gen 1i/1.5G receiver AC specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typical Max Units Notes
Unit Interval TUI 666.4333 666.6667 670.2333 ps —
Total jitter data-data 5 UI USATA_TXTJ5UI — — 0.43 UI p-p 1
Total jitter, data-data 250 UI USATA_TXTJ250UI — — 0.60 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_TXDJ5UI — — 0.25 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_TXDJ250UI — — 0.35 UI p-p 1
Note:
1. Measured at receiver
Table 87. Gen 2i/3G receiver AC specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typical Max Units Notes
Unit Interval TUI 333.2167 333.3333 335.1167 ps —
Total jitter fC3dB =f
BAUD ÷10 USATA_TXTJfB/10 — — 0.46 UI p-p 1
Total jitter fC3dB =f
BAUD ÷500 USATA_TXTJfB/500 — — 0.60 UI p-p 1
Total jitter fC3dB =f
BAUD ÷1667 USATA_TXTJfB/1667 — — 0.65 UI p-p 1
Table 85. Gen 2i/3 G transmitter AC specifications (continued)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Units Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor124
2.20.8 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 46, where
CTX is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω
output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference
circuit of the SerDes transmitter and receiver is shown in Figure 42.
2.20.8.0.1 SGMII clocking requirements for SD_REF_CLKn and SD_REF_CLKn
When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock
is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII
configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.8.1 SGMII DC electrical characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.20.8.1.1 SGMII transmit DC timing specifications
This table describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical characteristics for 1.25 GBaud.
Transmitter DC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) as shown in Figure 47.
Deterministic jitter, fC3dB =f
BAUD ÷10 USATA_TXDJfB/10 — — 0.35 UI p-p 1
Deterministic jitter, fC3dB =f
BAUD ÷500 USATA_TXDJfB/500 — — 0.42 UI p-p 1
Deterministic jitter, fC3dB =f
BAUD ÷1667 USATA_TXDJfB/1667 — — 0.35 UI p-p 1
Note:
1. Measured at receiver
Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit Notes
Output high voltage VOH — — 1.5 x
|VOD|-max
mV 1
Output low voltage VOL |VOD|-min/2 — — mV 1
Table 87. Gen 2i/3G receiver AC specifications (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typical Max Units Notes
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 125
Output differential voltage2, 3, 4
(XVDD-Typ at 1.5 V and 1.8 V)
|VOD| 320 500.0 725.0 mV B(1-3)TECR(lane)0[AMP_RED]
=0b000000
293.8 459.0 665.6 B(1-3)TECR(lane)0[AMP_RED]
=0b000010
266.9 417.0 604.7 B(1-3)TECR(lane)0[AMP_RED]
=0b000101
240.6 376.0 545.2 B(1-3)TECR(lane)0[AMP_RED]
=0b001000
213.1 333.0 482.9 B(1-3)TECR(lane)0[AMP_RED]
=0b001100
186.9 292.0 423.4 B(1-3)TECR(lane)0[AMP_RED]
=0b001111
160.0 250.0 362.5 B(1-3)TECR(lane)0[AMP_RED]
=0b010011
Output impedance (single-ended) RO40 50 60 Ω—
Notes:
1. This does not align to DC-coupled SGMII.
2. |VOD| = |VSD_TXn– VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.
3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output
differential voltage of 459 mV typical.
4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5 V or 1.8 V, no common mode
offset variation. SerDes transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn.
Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor126
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
Figure 46. 4-wire, AC-coupled, SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.
Figure 47. SGMII transmitter DC measurement circuit
SGMII
SerDes interface
50 Ω
50 Ω
Transmitter
SD_TXnSD_RXn
SD_TXnSD_RXn
Receiver
CTX
CTX
50 Ω
50 Ω
SD_RXn
SD_RXn
Receiver Transmitter
SD_TXn
SD_TXn
CTX
CTX
50 Ω
50 Ω
50 Ω
50 Ω
50
Ω
Transmitter
SD_TXn
SD_TXn50
Ω
VOD
SGMII
SerDes interface
50 Ω
50 Ω
Electrical characteristics
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 127
This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.
2.20.8.1.2 SGMII DC receiver electrical characteristics
This table lists the SGMII DC receiver electrical characteristics for 1.25 GBaud. Source synchronous clocking is not supported.
Clock is recovered from the data.
This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
2.20.8.2 SGMII AC timing specifications
This section discusses the AC timing specifications for the SGMII interface.
Table 89. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typical Max Unit Notes
Output voltage VO–0.40 — 2.30 V 1
Differential output voltage VDIFFPP 800 — 1600 mV p-p —
Note:
1. Absolute output voltage limit
Table 90. SGMII DC receiver electrical characteristics (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Unit Notes
DC Input voltage range — N/A — 1
Input differential voltage REIDL_CTL = 001xx VRX_DIFFp-p 100 — 1200 mV 2, 4
REIDL_CTL = 100xx 175 —
Loss of signal threshold REIDL_CTL = 001xx VLOS 30 — 100 mV 3, 4
REIDL_CTL = 100xx 65 — 175
Receiver differential input impedance ZRX_DIFF 80 — 120 Ω—
Notes:
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See
Section 2.20.4.4, “PCI Express DC physical layer receiver specifications,” and Section 2.20.4.5.2, “PCI Express AC physical
layer receiver specifications,” for further explanation.
4. The REIDL_CTL shown in the table refers to the chip’s SerDes control register B(1-3)GCR(lane)1[REIDL_CTL] bit field.
Table 91. SGMII 2.5x receiver DC timing specifications (XVDD = 1.5 V or 1.8 V)
For recommended operating conditions, see Ta bl e 3.
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 900 1600 mV p-p 1
Note:
1. Measured at the receiver.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Electrical characteristics
Freescale Semiconductor128
2.20.8.2.1 SGMII transmit AC timing specifications
This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include RefClk jitter.
2.20.8.2.2 SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) or at the receiver
inputs (SD_RXn and SD_RXn) respectively, as depicted in this figure.
Figure 48. SGMII AC test/measurement load
2.20.8.2.3 SGMII receiver AC timing specification
This table provides the SGMII receiver AC timing specifications. The AC timing specifications do not include RefClk jitter.
Source synchronous clocking is not supported. Clock is recovered from the data.
Table 92. SGMII transmit AC timing specifications
For recommended operating conditions, see Ta b l e 3 .
Parameter Symbol Min Typ Max Unit Notes
Deterministic jitter JD — — 0.17 UI p-p —
Total jitter JT — — 0.35 UI p-p 1
Unit Interval: 1.25 GBaud UI 800 – 100 ppm 800 800 + 100 ppm ps —
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps —
AC coupling capacitor CTX 10 — 200 nF 2
Notes:
1. See Figure 44 for single frequency sinusoidal jitter measurements.
2. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
Table 93. SGMII receive AC timing specifications
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit Notes
Deterministic jitter tolerance JD 0.37 — — UI p-p 1, 2
Combined deterministic and random jitter tolerance JDR 0.55 — — UI p-p 1, 2
Total jitter tolerance JT 0.65 — — UI p-p 1,2, 3
Transmitter
silicon
+ package
C = CTX
C = CTX
R = 50 ΩR = 50 Ω
D+ package pin
D– package pin
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 129
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 44.
3 Hardware design considerations
3.1 System clocking
This section describes the PLL configuration of the chip.
This device includes nine PLLs, as follows:
• There are two selectable core cluster PLLs which generate a core clock from the externally supplied SYSCLK input.
Core complex 0–1 can select from either CC1 PLL or CC2 PLL. The frequency ratio between the core cluster PLLs
and SYSCLK is selected using the configuration bits as described in Section 3.1.3, “e5500-64 core complex/ FMan to
SYSCLK PLL ratio.” The frequency for each core complex 0–1 is selected using the configuration bits as described
in Table 97.
• The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Platform to SYSCLK PLL ratio.”
• The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or
from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex
PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR controller PLL ratios.”
• The FMan PLL generates the FMan clock from the platform PLL when operating synchronously, or from CC3 PLL
when operating asynchronously. Described in Section 3.1.8, “Frame Manager (FMan) clock select.”
• Each of the four SerDes blocks has a PLL which generate a core clock from their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits
as described in Section 3.1.6, “Frequency options.”
Bit error ratio BER — — 10-12 ——
Unit Interval: 1.25 GBaud UI 800 – 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps 1
Notes:
1. Measured at receiver
2. See the RapidIOTM 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.
3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Table 93. SGMII receive AC timing specifications (continued)
For recommended operating conditions, see Ta b l e 3.
Parameter Symbol Min Typ Max Unit Notes
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor130
3.1.1 Clock ranges
This table provides the clocking specifications for the processor core, platform, memory, and local bus.
Table 94. Processor clocking specifications
Characteristic
Maximum Processor Core Frequency
Unit Notes1800 MHz 2000 MHz 2200 MHz
Min Max Min Max Min Max
Core PLL frequency 1000 1800 1000 2000 1000 2200 MHz 1,4
Core frequency 667 1800 667 2000 667 2200 MHz 4
Platform clock frequency 600 600 600 700 600 800 MHz 1
Memory bus clock frequency 400 600 400 667 400 800 MHz 1,2,5,6
Local bus clock frequency — 75 — 87.5 — 100 MHz 3
FMan frequency 300 450 300 600 300 600 MHz 7
Notes:
1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/DDR3L memory bus clock frequency is limited to min
= 400 MHz.
3. The local bus clock speed on LCLK[0:1] is determined by the platform clock divided by the local bus ratio programmed in
LCRR[CLKDIV]. See the applicable chip reference manual for more information.
4.The core can run at core complex PLL/1 or PLL/2. With a core complex PLL frequency of 1333 MHz, this results in the minimum
allowable core frequency of 667MHz for PLL/2.
5. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform frequency. If the desired DDR data rate is higher than the platform frequency, asynchronous mode
must be used.
6. In asynchronous mode, the memory bus clock speed is dictated by its own PLL.
7. The minimum frequencies for the FMan to support the specified interfaces are: 300 MHz for a 1G interface, 450 MHz for a
10 G interface, 500 MHz for a 10 G interface with PCD and 600 MHz for a 10 G and two 1 G interfaces. The FMAN PLL
frequency range is the same as the Core PLL frequency range.
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 131
3.1.2 Platform to SYSCLK PLL ratio
The allowed platform clock to SYSCLK ratios are shown in this table.
Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the platform bus frequency
because the platform frequency must equal the DDR data rate.
In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency.
3.1.3 e5500-64 core complex/ FMan to SYSCLK PLL ratio
The clock ratio between SYSCLK and each of the two core complex PLLs and FMan PLL is determined at power up by the
binary value of the RCW field CCn_PLL_RAT. (Note: n=1 or 2 are the core complex PLLs, n=3 is the FMan PLL). This table
describes the supported ratios. Note that a core complex/ FMan PLL setting targeting 1 GHz and above must set RCW field
CCn_PLL_CFG = 0b10, for setting targeting below 1 GHz CCn_PLL_CFG=0b00.
This table lists the supported core complex/ FMan to SYSCLK ratios.
Table 95. Platform to SYSCLK PLL ratios
Binary value of
SYS_PLL_RAT Platform:SYSCLK ratio
0_0101 5:1
0_0110 6:1
0_0111 7:1
0_1000 8:1
All Others Reserved
Table 96. Core complex/ FMan PLL to SYSCLK ratios
Binary value of
CCn_PLL_RAT Core cluster:SYSCLK ratio
0_1000 8:1
0_1001 9:1
0_1010 10:1
0_1011 11:1
0_1100 12:1
0_1110 14:1
0_1111 15:1
1_0000 16:1
1_0001 17:1
1_0010 18:1
1_0100 20:1
1_0110 22:1
All Others Reserved
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor132
3.1.4 Core complex PLL select
The clock frequency of each of the core 0–1 complex is determined by the binary value of the RCW field Cn_PLL_SEL. This
table describes the supported ratios for each core complex 0-1, where each individual core complex can select a frequency from
the table.
3.1.5 DDR controller PLL ratios
The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform, depending on
configuration. Both DDR controllers operate at the same frequency configuration.
Table 98 describes the clock ratio between the DDR memory controller PLLs and the externally supplied SYSCLK input
(asynchronous mode) or from the platform clock (synchronous mode).
In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 98. This ratio is determined by
the binary value of the RCW Configuration field MEM_PLL_RAT[10:14]. The corresponding setting for
MEM_PLL_CFG[0:1] is listed in Table 99.
NOTE
The RCW Configuration field DDR_SYNC (bit 184) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios.
Table 97. Core complex [0,1] PLL select
Binary value of Cn_PLL_SEL Core cluster ratio
0000 CC1 PLL /1
0001 CC1 PLL /2
0100 CC2 PLL /1
0101 CC2 PLL/2
All Others Reserved
Note: If CC2 PLL is used by core0 or core1, then CC2 PLL must be operated
at a lower frequency than the CC1 PLL, and its maximum allowed
frequency is 80% of the maximum rated frequency of the core at nominal
voltage.
Table 98. Asynchronous DDR clock ratio
Binary value of MEM_PLL_RAT[10:14] DDR:SYSCLK ratio
0_0101 5:1
0_0110 6:1
0_1000 8:1
0_1001 9:1
0_1010 10:1
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 133
In synchronous mode, the DDR data rate to platform clock ratios supported are listed in this table. This ratio is determined by
the binary value of the RCW Configuration field MEM_PLL_RAT[10:14].
0_1100 12:1
0_1101 13:1
1_0000 16:1
1_0010 18:1
1_0011 19:1
1_0100 20:1
1_1000 24:1
All Others Reserved
Note:
1. RCW[MEM_PLL_CFG] is set dependant on the DDR clock ratio used. See Ta bl e 9 9 for
valid setttings of DDR clock ratio and MEM_PLL_CFG.
Table 99. Supported DDR ratios and RCW MEM_PLL_CFG settings
MEM:SYSCLK
Ratio
SYSCLK (MHz)
100 125 133.3 150
DDR Rate (MT/s)/MEM_PLL_CFG
1 (Sync Mode) Platform Clock/01
6 Reserved 800/11 900/113
8 800/1011000/0111067/01 1200/01
9 900/1021125/0121200/01 1350/01
10 1000/01 1250/01 1333/01 1500/01
12 1200/11 1500/11 1600/11 Reserved
13 1300/11 Reserved
16 1600/11 Reserved
Notes:
1. For MEM SYSYCLK RATIO = 8, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
greater than or equal to 120.9MHz
2. For MEM SYSYCLK RATIO = 9, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
greater than or equal to 107.4MHz
3. Maximum SYSCLK is 161.2MHz when MEM:SYSCLK ratio = 6
Table 98. Asynchronous DDR clock ratio (continued)
Binary value of MEM_PLL_RAT[10:14] DDR:SYSCLK ratio
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor134
3.1.6 Frequency options
This section discusses interface frequency options.
3.1.6.1 SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
3.1.6.2 Minimum platform frequency requirements for high-speed interfaces
The platform clock frequency must be considered for proper operation of high-speed interfaces as described below.
For proper PCI Express operation, the platform clock frequency must be greater than or equal to the values shown in these
figures.
Figure 49. Gen 1 PEX minimum platform frequency
Figure 50. Gen 2 PEX minimum platform frequency
Table 100. Synchronous DDR clock ratio
Binary Value of
MEM_PLL_RAT[10:14] DDR:Platform CLK ratio Set MEM_PLL_CFG=01
for platform CLK freq1
0_0001 1:1 >600 MHz
All Others Reserved —
Note:
1. Set RCW field MEM_PLL_CFG=0b01
Table 101. SYSCLK and platform frequency options
Platform:
SYSCLK
ratio
SYSCLK (MHz)
100 125 133.3 150
Platform frequency (MHz)1
1Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy
removed)
5:1 625 666 750
6:1 600 750 800
7:1 700
8:1 800
527 MHz PCI Express link width()×
16
--------------------------------------------------------------------------------
527 MHz PCI Express link width()×
8
--------------------------------------------------------------------------------
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 135
Note that “PCI Express link width” in the above equation refers to the negotiated link width as the result of PCI Express link
training, which may or may not be the same as the link width POR selection.
3.1.7 SerDes PLL ratio
The clock ratio between each of the four SerDes PLLs and their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field SRDS_RATIO_Bn
as shown in this table. Furthermore, each SerDes lane grouping can be run at a SerDes PLL frequency divider determined by
the binary value of the RCW field SRDS_DIV_Bn as shown in Table 103 and Table 104.
This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios.
This table shows the PLL divider support for each pair of lanes on SerDes Bank 1.
This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2, 3, and 4.
Table 102. SerDes PLL bank n to SD_REF_CLKn ratios
Binary value of
SRDS_RATIO_Bn
SRDS_PLL_n:SD_REF_CLKn ratio
n = 1 (bank 1) n = 2 (bank 2) n = 3 (bank 3) n = 4(bank 4)
001 Reserved 20:1 20:1 Reserved
010 25:1 25:1 25:1 Reserved
011 40:1 40:1 40:1 Reserved
100 50:1 50:1 50:1 Reserved
101 Reserved Reserved 24:1 24:1
110 Reserved Reserved 30:1 30:1
All Others Reserved Reserved Reserved Reserved
Table 103. SerDes bank 1 PLL dividers
Binary value of SRDS_DIV_B1[0:4] SerDes bank 1 PLL divider
0b0 Divide by 1 off Bank 1 PLL
0b1 Divide by 2 off Bank 1 PLL
Note:
1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes,
where the first bit controls configuration of lanes A/B (or 0/1) and
the last bit controls configuration of lanes I/J (or 8/9).
Table 104. SerDes banks 2, 3, and 4 PLL dividers
Binary value of SRDS_DIV_BnSerDes Bank n PLL divider
0b0 Divide by 1 off Bank n PLL
0b1 Divide by 2 off Bank n PLL
Notes:
1. One bit controls all 4 lanes of each bank.
2. n = 2 or 3 (SerDes bank 2 or bank 3)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor136
3.1.8 Frame Manager (FMan) clock select
The Frame Managers (FM) can each be synchronous with or asynchronous to the platform, depending on configuration.
This table describes the clocking options that may be applied to each FM. The clock selection is determined by the binary value
of the RCW Clocking Configuration fields FM1_CLK_SEL and FM2_CLK_SEL.
3.2 Supply power default setting
This chip is capable of supporting multiple power supply levels on its I/O supplies. The I/O voltage select inputs, shown in the
following table, properly configure the receivers and drivers of the I/Os associated with the BVDD, CVDD, and LVDD power
planes, respectively.
WARNING
Incorrect voltage select settings can lead to irreversible device damage.
Table 105. Frame Manager (FMan) clock select
Binary value of FMn_CLK_SEL FM frequency
0b0 Platform Clock Frequency /2
0b1 FMan PLL Frequency /2 1,2
Notes:
1. For asynchronous mode, max frequency see Table 94.
2. For PLL settings, see Ta b l e 9 6 .
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 137
3.3 Power supply design
3.3.1 PLL power supply filtering
Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CCn, AVDD_DDR, AVDD_FM, and AVDD_SRDSn). AVDD_PLAT, AVDD_CCn, AV DD_FM, and AVDD_DDR
voltages must be derived directly from the VDD_PL source through a low frequency filter scheme. AVDD_SRDSn voltages must
be derived directly from the SVDD source through a low frequency filter scheme.
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in
Figure 51, one for each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range.
Table 106. I/O voltage selection
Signals Value
(binary)
VDD voltage selection
BVDD CVDD LVDD
IO_VSEL[0:4]
Default (0_0000)
0_0000 3.3 V 3.3 V 3.3 V
0_0001 3.3 V 3.3 V 2.5 V
0_0011 3.3 V 2.5 V 3.3 V
0_0100 3.3 V 2.5 V 2.5 V
0_0110 3.3 V 1.8 V 3.3 V
0_0111 3.3 V 1.8 V 2.5 V
0_1001 2.5 V 3.3 V 3.3 V
0_1010 2.5 V 3.3 V 2.5 V
0_1100 2.5 V 2.5 V 3.3 V
0_1101 2.5 V 2.5 V 2.5 V
0_1111 2.5 V 1.8 V 3.3 V
1_0000 2.5 V 1.8 V 2.5 V
1_0010 1.8 V 3.3 V 3.3 V
1_0011 1.8 V 3.3 V 2.5 V
1_0101 1.8 V 2.5 V 3.3 V
1_0110 1.8 V 2.5 V 2.5 V
1_1000 1.8 V 1.8 V 3.3 V
1_1001 1.8 V 1.8 V 2.5 V
1_1011 3.3 V 3.3 V 3.3 V
1_1100 3.3 V 3.3 V 3.3 V
1_1101 3.3 V 3.3 V 3.3 V
1_1110 3.3 V 3.3 V 3.3 V
1_1111 3.3 V 3.3 V 3.3 V
All Others Reserved
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor138
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the
footprint, without the inductance of vias.
Figure 51 shows the PLL power supply filter circuit.
Where:
R = 5 Ω ± 5%
C1 = 10μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH
NOTE
A higher capacitance value for C2 may be used to improve the filter as long as the other C2
parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
Voltage for AVDD is defined at the PLL supply filter and not the pin of AVDD.
Figure 51. PLL power supply filter circuit
The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 52. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as
possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed
by two 2.2-µF capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn
to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
Figure 52. SerDes PLL power supply filter circuit
Note the following:
•AV
DD_SRDSn should be a filtered version of SVDD.
• Signals on the SerDes interface are fed from the XVDD power plane.
• Voltage for AVDD_SRDSn is defined at the PLL supply filter and not the pin of AVDD_SRDSn.
• An 0805 sized capacitor is recommended for system initial bring-up.
3.3.2 XVDD power supply filtering
XVDD may be supplied by a linear regulator or sourced by a filtered 1.5 V or 1.8 V voltage source. Systems may design in both
options to allow flexibility to address system noise dependencies.
An example solution for XVDD filtering, where 1.5 V or 1.8 V is sourced from voltage source (for example, GVDD at 1.5 V
when using DDR3, or CVDD at 1.8 V), is illustrated in Figure 53. The component values in this example filter is system
VDD_PL
AV
DD_PLAT
, AV
DD_CC
n
, AV
DD_DDR
C1 C2
GND Low ESL Surface Mount Capacitors
R
AV
DD_FM
2.2 µF10.003 µF
1.0 Ω
AVDD_SRDSn
2.2 µF1
GND
SVDD
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 139
dependent and are still under characterization, component values may need adjustment based on the system or environment
noise.
Where:
C1 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
C2 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
F1 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
F2 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
Bulk and decoupling capacitors are added, as needed, per power supply design.
Figure 53. XVDD power supply filter circuit
3.3.3 USB_VDD_1P0 power supply filtering
USB_VDD_1P0 should be sourced by a filtered VDD_PL using a star connection. An example solution for USB_VDD_1P0
filtering, where USB_VDD_1P0 is sourced from VDD_PL, is illustrated in Figure 54. The component values in this example filter
is system dependent and are still under characterization, component values may need adjustment based on the system or
environment noise.
Where:
C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
Bulk and decoupling capacitors are added, as needed, per power supply design.
Figure 54. USB_VDD_1P0 power supply filter circuit
3.4 Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the chip’s system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, OVDD, CVDD, GVDD, and
LVDD pin of the chip. These decoupling capacitors should receive their power from separate VDD, BVDD, OVDD, CVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed
directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD,
OVDD, CVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
XVDD 1.5 V or 1.8V source
C1 C2
GND
F1
F2
Bulk and
Decoupling
Capacitors
USB_VDD_1P0 VDD_PL
C1 C1
GND
F1
Bulk and
Decoupling
Capacitors
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor140
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
3.5 SerDes block power supply decoupling recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
• First, the board should have at least 10 ×10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
chip as close to the supply and ground connections as possible.
• Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes
supplies.
• Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip
capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
3.6 Connection recommendations
To ensure reliable operation, it is recommended the user consider the following:
• Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD, BVDD,
CVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no
connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, BVDD,
CVDD, OVDD, GVDD, LVDD, and GND pins of the chip.
• The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field
EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do
not need to be externally pulled to an appropriate signal level.
•ECn_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the
ECn_GTX_CLK125 input can be tied off to GND.
• If RCW field DMA1=0b1 (RCW bit 384), the DMA1 external interface is not enabled and this pin should be left as a
no connect.
• If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled
for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that
SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby
selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP =
write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used.
• .For P5021 (SVR = 0x8205_00XX) or P5021E (SVR = 0x820D_00XX), TEST_SEL must be connected to GND.
• The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust
Architecture” in the applicable chip reference manual). When using Trust Architecture functionality, external logic
must ramp TMP_DETECT with OVDD. If not using Trust Architecture functionality, TMP_DETECT must be tied to
OVDD to prevent the input from going low.
3.6.1 Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56.
Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most
have asynchronous behavior and spurious assertion gives unpredictable results.
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 141
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be
asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal device operation.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST
during the power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also used for
accessing the common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
PORESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in Figure 56 allows the COP port to independently assert PORESET or TRST, while ensuring that the
target can drive PORESET as well.
The COP interface has a standard header, shown in Figure 55, for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering
schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom.
Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal
placement recommended in Figure 55 is common to all known emulators.
3.6.1.1 Termination of unused signals
If the JTAG interface and COP header is not used, Freescale recommends the following connections:
•TRST
should be tied to PORESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal
(PORESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in Figure 56. If this is not possible, the
isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future
debug situations.
• No pull-up/pull-down is required for TDI, TMS, or TDO.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor142
Figure 55. Legacy COP connector physical pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
12
COP_TDO
COP_TDI
NC
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
NC
GND
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CHKSTP_OUT
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 143
Figure 56. Legacy JTAG interface connection
PORESET
From Target
Board Sources
COP_HRESET
13
COP_SRESET
HRESET
NC
11
COP_VDD_SENSE2
6
15
10 Ω
10 kΩ
10 kΩ
COP_CHKSTP_IN
8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4COP_TRST
7
16
2
10
12
(if any)
COP Header
14 3
Notes:
10 kΩ
TRST1
10 kΩ
10 kΩ
10 kΩ
CKSTP_OUT
COP_CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pinout
1
2
NC
HRESET
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
NC
OVDD
10 kΩPORESET1
in order to fully control the processor as shown here.
1. The COP port and target board should be able to independently assert PORESET and TRST to the processor
signal integrity.
TCK
4
5
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to position B.
10 kΩ
6
6.
Asserting HRESET causes a hard reset on the device.
3. T
he KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
A
B
5
System logic
Chip
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor144
3.6.2 Aurora configuration signals
Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 57
and Figure 58. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating
conditions as most have asynchronous behavior and spurious assertion gives unpredictable results.
Freescale recommends that the Aurora 22 pin duplex connector be designed into the system as shown in Figure 59 or the 70 pin
duplex connector be designed into the system as shown in Figure 60.
If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in
Section 3.6.1.1, “Termination of unused signals.”
Figure 57. Aurora 22 pin connector duplex pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
TX0+
TX0-
GND
VIO (VSense)
TCK
TMS
TDI
TDO
TRST
Vendor I/O 1
TX1+
TX1-
GND
RX0+
RX0-
17 18
20
19
21 22
GND
RX1+
RX1-
Vendor I/O 0
14
Vendor I/O 3
Vendor I/O 2
RESET
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 145
Figure 58. Aurora 70 pin connector duplex pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
TX0+
TX0-
GND
VIO (VSense)
TCK
TMS
TDI
TDO
TRST
Vendor I/O 1
TX1+
TX1-
GND
RX0+
RX0-
17 18
20
19
21 22
GND
RX1+
RX1-
Vendor I/O 0
14
Vendor I/O 3
Vendor I/O 2
RESET
25
35
31
27
23
28
32
37
33
29
38
34
30
26
24
GND
TX2+
TX2-
GND
CLK+
CLK-
GND
Vendor I/O 4
Vendor I/O 5
N/C
GND
TX3+
TX3-
GND
RX2+
39 40
42
41
43 44
RX2-
GND
RX3+
GND
36
GND
N/C
N/C
47
57
53
49 50
54
59
55
51
60
56
52
48
45 46
RX3-
GND
TX4+
N/C
GND
N/C
N/C
GND
N/C
GND
TX4-
GND
TX5+
TX5-
GND
61 62
64
63
65 66
TX6+
TX6-
GND
N/C
58
N/C
N/C
GND
68
67
69 70
TX7+
TX7-
N/C
N/C
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor146
Figure 59. Aurora 22 pin connector duplex interface connection
PORESET
From Target
Board Sources
RESET
22
HRESET
VIO VSense2
21 kΩ
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
6
10
8
12 TRST
4
17
11
(if any)
COP Header
Notes:
10 kΩ
TRST1
10 kΩ
10 kΩ
10 kΩ
Duplex 22 Connector
Physical Pinout
HRESET
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
OVDD
10 kΩPORESET1
in order to fully control the processor as shown here.
1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
TCK
3
3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to position B.
10 kΩ
4
4.
Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
A
B
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
17 18
20
19
21 22
14
20 Vendor I/O 3 N/C
18 Vendor I/O 2 (Aurora Event Out)
16 Vendor I/O 1 (Aurora Event In)
14 Vendor I/O 0 (Aurora HALT)
5
EVT[4]
EVT[1]
EVT[0]
1TX0_P
3TX0_N
SD_TX09_P
SD_TX09_N
7TX1_P
9TX1_N
SD_TX08_P
SD_TX08_N
13 RX0_P
15 RX0_N
SD_RX09_P
SD_RX09_N
19 RX1_P
21 RX1_N
SD_RX08_P
SD_RX08_N
Chip
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 147
Figure 60. Aurora 70 pin connector duplex interface connection
PORESET
From Target
Board Sources
RESET
22
HRESET
VIO VSense2
21 kΩ
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
6
10
8
12
TRST
4
42,47,48,53,54,
29,30,35,36,41,
(if any)
COP Header
Notes:
TRST1
10 kΩ
10 kΩ
10 kΩ
Duplex 70
HRESET
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
OVDD
10 kΩPORESET1
in order to fully control the processor as shown here.
1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
TCK
3
3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to position B.
10 kΩ
4
4.
Asserting HRESET causes a hard reset on the device.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
A
B
20 Vendor I/O 3 N/C
18 Vendor I/O 2 (Aurora Event Out)
16 Vendor I/O 1 (Aurora Event In)
14 Vendor I/O 0 (Aurora HALT)
5,11,17,23,24,
EVT[4]
EVT[1]
EVT[0]
1TX0_P
3TX0_N
SD_TX09_P
SD_TX09_N
7TX1_P
9TX1_N
SD_TX08_P
SD_TX08_N
13 RX0_P
15 RX0_N
SD_RX09_P
SD_RX09_N
19 RX1_P
21 RX1_N
SD_RX08_P
SD_RX08_N
3
13
9
5
1
6
10
15
11
7
16
12
8
4
12
17 18
20
19
21 22
14
25
35
31
27
23
28
32
37
33
29
38
34
30
26
24
39 40
42
41
43 44
36
47
57
53
49 50
54
59
55
51
60
56
52
48
45 46
61 62
64
63
65 66
58
68
67
69 70
34 Vendor I/O 5 (Aurora HRESET)
32 Vendor I/O 4 N/C EVT[4]
31,33,37,38,
N/C
39,40,43,44,
45,46,49,50,
51,52,55,56,
57,58,61,62,
63,64,67,68,
25,26,27,28,
69,70
59,60,65,66
Connector
Physical Pinout
10 kΩ
10 k
Ω
Chip
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor148
3.6.3 Guidelines for high-speed interface termination
This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when
it is partly unused.
3.6.3.1 SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.
The following pins must be left unconnected:
• SD_TX[19:0]
•SD_TX
[19:0]
•SD_IMP_CAL_RX
• SD_IMP_CAL_TX
• SD1_IMP_CAL_RX
• SD1_IMP_CAL_TX
The following pins must be connected to SGND:
• SD_RX[19:0]
•SD_RX
[19:0]
• SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4
• SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4
The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2, SRDS_LPD_B3, and SRDS_LPD_B4, all bits must be set to
power down all the lanes in each bank.
The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting
RCW[SRDS_EN_S1] = 0 powers down the PLLs of banks 1 to 3; RCW[SRDS_EN_S2]=0 powers down the PLL of bank 4.
Additionally, software may configure SRDSBnRSTCTL[SDRD] =1 for the unused banks to power down the SerDes bank
PLLs to save power.
Note that both SVDD and XVDD must remain powered.
3.6.3.2 SerDes interface partly unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following pins must be left unconnected:
•SD_TX[n]
•SD_TX
[n]
The following unused pins must be connected to SGND:
•SD_RX[n]
•SD_RX
[n]
• SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)
• SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)
• SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused)
• SD_REF_CLK4, SD_REF_CLK4 (If entire SerDes bank 4 unused)
Hardware design considerations
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 149
In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must
be set to power down the lane.
3.6.4 USB controller connections
This section details the hardware connections required for the USB controllers.
3.6.4.1 USB divider network
This figure shows the required divider network for the VBUS interface for the chip. Additional requirements for the external
components are as follows:
• Both resistors require 0.1% accuracy and a current capability of up to 1 mA. They must both have the same temperature
coefficient and accuracy.
• The zener diode must have a value of 5 V−5.25 V.
• The 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V.
Figure 61. Divider network at VBUS
USB1_DRVVBUS and USB1_PWRFAULT are muxed on GPIO[4:5] pins, respectively. USB2_DRVVBUS and
USB2_PWRFAULT are muxed on GPIO[6:7] pins, respectively. Setting the RCW[GPIO] bit selects USB functionality on the
GPIO pins.
3.6.4.2 USBn_VDD_1P8_DECAP capacitor options
The USBn_VDD_1P8_DECAP pins require a capacitor connected to GND. This table list the recommended capacitors for the
USBn_VDD_1P8_DECAP signal.
Table 107. Recommended capacitor parts for USBn_VDD_1P8_DECAP
Manufacturer Part Number Value ESR Package
Kemet T494B105(1)025A(2) 1 μF, 2 5 V 2 ΩB(3528)
T494B155(1)025A(2) 1.5 μF, 25 V 1.5 Ω—
NIC NMC0603X7R106KTRPF 1 μF, 10 V Low ESR 0603
TDK Corporation CERB2CX5R0G105M 1 μF, 4 V 200 m-Ω0603
Vishay TR3B105(1)035(2)1500 1 μF, 35 V 1.5 ΩB(3528)
USBn_DRVVBUS
18.1 kΩ
USBn_VBUS_CLMP
51.2 kΩ
Chip
5 VZ
0.6 VF
USBn_PWRFAULT
VBUS Charge
Pump
VBUS
(USB Connector)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Hardware design considerations
Freescale Semiconductor150
3.7 Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this document can be obtained from your
local Freescale sales office.
3.8 Thermal management information
This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material.
The recommended attachment method to the heat sink is illustrated in this figure. The heat sink should be attached to the
printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45
Newton).
Figure 62. Exploded cross-sectional view—FC-PBGA (with lid) package
The system board designer can choose between several types of heat sinks to place on the device. There are several
commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat
sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.
3.8.1 Internal package conduction resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance
Adhesive or
Heat sink FC-PBGA package (small lid)
Heat sink
clip
Printed-circuit board
thermal interface material
Die
Die lid
Package information
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 151
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
Figure 63. Package with heat sink mounted to a printed-circuit board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the
silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case
thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.
3.8.2 Thermal interface materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is
generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by
means of a spring clip attachment to the printed-circuit board (see Figure 62).
The system board designer can choose among several types of commercially-available thermal interface materials.
4 Package information
The following section describes the detailed content and mechanical description of the package.
4.1 Package parameters for the FC-PBGA
The package parameters are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 1295 flip-chip,
plastic-ball, grid array (FC-PBGA).
Package outline 37.5 mm × 37.5 mm
Interconnects 1295
Ball Pitch 1.0 mm
Ball Diameter (typical) 0.60 mm
Solder Balls 96.5% Sn, 3% Ag, 0.5% Cu
Module height (typical) 2.88 mm to 3.53 mm (Maximum)
External resistance
External resistance
Internal resistance
Radiation Convection
Radiation Convection
Heat sink
Printed-circuit board
Thermal interface material
Package/solder balls
Die junction
Die/Package
(Note the internal versus external package resistance)
Junction to lid top
Junction to case top
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Package information
Freescale Semiconductor152
4.2 Mechanical dimensions of the FC-PBGA
This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.
Figure 64. Mechanical dimensions of the FC-PBGA with full lid
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.
5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement shall exclude any effect of mark on top surface of package.
Security fuse processor
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor 153
5 Security fuse processor
This chip implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust
Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust
Architecture and SFP can be found in the applicable chip reference manual.
To program SFP fuses, the user is required to supply 1.5 V to the POVDD pin per Section 2.2, “Power-up sequencing.” POVDD
should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles.
All other times, connect POVDD to GND. The sequencing requirements for raising and lowering POVDD are shown in Figure 8.
To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature
range per Table 3.
Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect
POVDD to GND.
6 Ordering information
Please contact your local Freescale sales office or regional marketing team for ordering information.
6.1 Part numbering nomenclature
This table provides the Freescale QorIQ platform part numbering nomenclature.
Table 108. Part Numbering Nomenclature
pnnnn x t e n c d r
Generation Platform Number
of Cores Derivative Qual
Status
Temperature
Range Encryption Package
Type
CPU
Speed
DDR
Speed
Die
Revision
P=45nm 5 • 01=
1 core
•02=
2 cores
•04=
4 cores
0–9 P =
Prototype
N=
Qualified
•S = Std
temp
(0 °C to
105 °C
•X = Ext
temp
(–40 °C to
105 °C)
•E =
SEC
present
•N =
SEC
not
present
1 =
FC-PBGA
lead-free
7=
FC-PBGA
C4/C5
lead-free
•T=
1800 MHz
•V=
2000 MHz
•2=
2200 MHz
•M=
1200 MHz
•N=
1333 MHz
•Q=
1600 MHz
A = Rev
1.0
B = Rev
2.0
C = Rev
2.1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Revision history
Freescale Semiconductor154
6.2 Orderable part numbers addressed by this document
This table provides the Freescale orderable part numbers addressed by this document for the chip. Contact your Freescale Sales
Representative for more information on orderable parts as not all combinations of orderable part numbers are available.
7 Revision history
This table provides a revision history for this document.
Table 109. Orderable part numbers addressed by this document
Part
number pn nn n x t e n cd r
P5021 P 5 02 = 2 cores 1 P =
Prototype
N=
Qualified
•S = Std
temp (0 °C
to 105 °C
• X = Ext
temp
(–40 °C to
105 °C)
• E = SEC
present
• N = SEC
not
present
1 =
FC-PBGA
lead-free
7=
FC-PBGA
C4/C5
lead-free
•TM=
1800 MHz/
1200 MHz
•VN=
2000 MHz/
1333 MHz
•2Q=
2200 MHz/
1600 MHz
B = Rev
2.0
C = Rev
2.1
Table 110. Revision history
Rev.
Number Date Description
1 05/2014 • Includes two SATA controllers
• Updated block diagram
•In Ta bl e 1 “Pins listed by bus,” updated footnote 42.
•In Ta bl e 9 “VDD_LP power dissipation,” updated footnote 2.
0 12/2013 • Initial public release.
Document Number: P5021
Rev. 1
05/2014
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