OPA211
OPA2211
OPA211
OPA2211
OPA211
1
FEATURES DESCRIPTION
APPLICATIONS
INPUTVOLTAGENOISEDENSITYvsFREQUENCY
VoltageNoiseDensity(nV/ )
ÖHz
0.1
100
1
Frequency(Hz)
100k101
10
100 1k 10k
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
1.1nV/ √Hz Noise, Low Power, PrecisionOperational Amplifier in Small DFN-8 Package
23
•LOW VOLTAGE NOISE: 1.1nV/ √Hz at 1kHz
The OPA211 series of precision operationalamplifiers achieves very low 1.1nV/ √Hz noise density•INPUT VOLTAGE NOISE:
with a supply current of only 3.6mA. This series also80nV
PP
(0.1Hz to 10Hz)
offers rail-to-rail output swing, which maximizes•THD+N: – 136dB (G = 1, f = 1kHz)
dynamic range.•OFFSET VOLTAGE: 125 µV (max)
The extremely low voltage and low current noise,•OFFSET VOLTAGE DRIFT: 0.35 µV/ ° C (typ)
high speed, and wide output swing of the OPA211•LOW SUPPLY CURRENT: 3.6mA/Ch (typ)
series make these devices an excellent choice as aloop filter amplifier in PLL applications.•UNITY-GAIN STABLE•GAIN BANDWIDTH PRODUCT:
In precision data acquisition applications, theOPA211 series of op amps provides 700ns settling80MHz (G = 100)
time to 16-bit accuracy throughout 10V output swings.45MHz (G = 1)
This ac performance, combined with only 125 µV of•SLEW RATE: 27V/ µs
offset and 0.35 µV/ ° C of drift over temperature, makes•16-BIT SETTLING: 700ns
the OPA211 ideal for driving high-precision 16-bitanalog-to-digital converters (ADCs) or buffering the•WIDE SUPPLY RANGE:
output of high-resolution digital-to-analog converters± 2.25V to ± 18V, +4.5V to +36V
(DACs).•RAIL-TO-RAIL OUTPUT
The OPA211 series is specified over a wide•OUTPUT CURRENT: 30mA
dual-power supply range of ± 2.25V to ± 18V, or for•DFN-8 (3mm × 3mm), MSOP-8, AND SO-8
single-supply operation from +4.5V to +36V.
The OPA211 is available in the small DFN-8 (3mm ×3mm), MSOP-8, and SO-8 packages. A dual version,•PLL LOOP FILTER
the OPA2211, is available in the DFN-8 (3mm וLOW-NOISE, LOW-POWER SIGNAL
3mm) or an SO-8 PowerPAD™ package. This seriesPROCESSING
of op amps is specified from T
A
= – 40 ° C to +125 ° C.•16-BIT ADC DRIVERS•DAC OUTPUT AMPLIFIERS•ACTIVE FILTERS•LOW-NOISE INSTRUMENTATION AMPS•ULTRASOUND AMPLIFIERS•PROFESSIONAL AUDIO PREAMPLIFIERS•LOW-NOISE FREQUENCY SYNTHESIZERS•INFRARED DETECTOR AMPLIFIERS•HYDROPHONE AMPLIFIERS•GEOPHONE AMPLIFIERS•MEDICAL
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Over operating free-air temperature range (unless otherwise noted).
VALUE UNIT
Supply Voltage V
S
= (V+) – (V – ) 40 VInput Voltage (V – ) – 0.5 to (V+) + 0.5 VInput Current (Any pin except power-supply pins) ± 10 mAOutput Short-Circuit
(2)
ContinuousOperating Temperature (T
A
) – 55 to +150 ° CStorage Temperature (T
A
) – 65 to +150 ° CJunction Temperature (T
J
) 200 ° CHuman Body Model (HBM) 3000 VESD Ratings
Charged Device Model (CDM) 1000 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.(2) Short-circuit to V
S
/2 (ground in symmetrical dual supply setups), one amplifier per package.
PACKAGE/ORDERING INFORMATION
(1)
PACKAGE PACKAGEPRODUCT PACKAGE-LEAD SINGLE SHUTDOWN DUAL DESIGNATOR MARKING
Standard Grade
DFN-8 (3mm × 3mm) ü ü DRG OBDQMSOP-8 ü ü DGK OBCQOPA211AI
A TI OPASO-8 üD
211DFN-8 (3mm × 3mm) üDRG OBHQOPA2211AI
A TI OPASO-8 PowerPAD üDDA
2211
High Grade
DFN-8 (3mm × 3mm) ü ü DRG OBDQMSOP-8 ü ü DGK OBCQOPA211I
TI OPASO-8 üD
211
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
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PIN CONFIGURATIONS
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
Shutdown(3)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
Shutdown(3)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
Pad(2)
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
Pad(2)
A
B
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
A
B
Pad(2)
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
OPA211
OPA211SO-8
MSOP-8
OPA211
OPA2211DFN-8 (3mm × 3mm)
DFN-8 (3mm × 3mm)
OPA2211
SO-8 PowerPAD
(1) NC denotes no internal connection.(2) Exposed thermal die pad on underside; connect thermal die pad to V – . Soldering the thermal pad improves heatdissipation and provides specified performance.(3) Shutdown function:•Device enabled: (V – ) ≤V
SHUTDOWN
≤(V+) – 3V•Device disabled: V
SHUTDOWN
≥(V+) – 0.35V
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Product Folder Link(s): OPA211 OPA2211
ELECTRICAL CHARACTERISTICS: V
S
= ± 2.25V to ± 18V
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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BOLDFACE limits apply over the specified temperature range, T
A
= – 40 ° C to +125 ° C.At T
A
= +25 ° C, R
L
= 10k Ωconnected to midsupply, V
CM
= V
OUT
= midsupply, unless otherwise noted.
Standard Grade High GradeOPA211AI, OPA2211AI OPA211I
(1)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage V
OS
OPA211 V
S
= ± 15V ± 30 ± 125 ± 20 ± 50 µV
OPA2211 V
S
= ± 15V ± 50 ± 150 µV
Drift dV
OS
/dT 0.35 1.5 0.15 0.85 µV/ ° C
vs Power Supply PSRR V
S
= ± 2.25V to ± 18V 0.1 1 0.1 0.5 µV/V
Over Temperature 3 3 µV/V
INPUT BIAS CURRENT
Input Bias Current I
B
V
CM
= 0V ± 60 ± 175 ± 50 ± 125 nA
Over Temperature
OPA211 ± 200 ± 200 nA
OPA2211 ± 250 nA
Offset Current I
OS
V
CM
= 0V ± 25 ± 100 ± 20 ± 75 nA
Over Temperature ± 150 ± 150 nA
NOISE
Input Voltage Noise e
n
f = 0.1Hz to 10Hz 80 80 nV
PP
Input Voltage Noise Density f = 10Hz 2 2 nV/ √Hz
f = 100Hz 1.4 1.4 nV/ √Hz
f = 1kHz 1.1 1.1 nV/ √Hz
Input Current Noise Density I
n
f = 10Hz 3.2 3.2 pA/ √Hz
f = 1kHz 1.7 1.7 pA/ √Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range V
CM
V
S
≥± 5V (V – ) + 1.8 (V+) – 1.4 (V – ) + 1.8 (V+) – 1.4 V
V
S
< ± 5V (V – ) + 2 (V+) – 1.4 (V – ) + 2 (V+) – 1.4 V
Common-Mode Rejection Ratio CMRR V
S
≥± 5V, (V – ) + 2V ≤V
CM
≤(V+) – 2V 114 120 114 120 dB
V
S
< ± 5V, (V – ) + 2V ≤V
CM
≤(V+) – 2V 110 120 110 120 dB
INPUT IMPEDANCE
Differential 20k || 8 20k || 8 Ω|| pF
Common-Mode Ω|| pF10
9
|| 2 10
9
|| 2
OPEN-LOOP GAIN
Open-Loop Voltage Gain A
OL
(V – ) + 0.2V ≤V
O
≤(V+) – 0.2V,
114 130 114 130 dBR
L
= 10k Ω
A
OL
(V – ) + 0.6V ≤V
O
≤(V+) – 0.6V,
110 114 110 114 dBR
L
= 600 Ω
Over Temperature
OPA211 A
OL
(V – ) + 0.6V ≤V
O
≤(V+) – 0.6V,
110 110 dBI
O
≤15mA
OPA211 A
OL
(V – ) + 0.6V ≤V
O
≤(V+) – 0.6V,
103 103 dB15mA ≤I
O
≤30mA
OPA2211 (per channel) A
OL
(V – ) + 0.6V ≤V
O
≤(V+) – 0.6V,
100 dBI
O
≤15mA
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW G = 100 80 80 MHz
G = 1 45 45 MHz
Slew Rate SR 27 27 V/ µs
Settling Time, 0.01% t
S
V
S
= ± 15V, G = – 1, 10V Step, C
L
= 100pF 400 400 ns
0.0015% (16-bit) V
S
= ± 15V, G = – 1, 10V Step, C
L
= 100pF 700 700 ns
Overload Recovery Time G = – 10 500 500 ns
Total Harmonic Distortion + Noise THD+N G = +1, f = 1kHz,
0.000015 0.000015 %V
O
= 3V
RMS
, R
L
= 600 Ω
– 136 – 136 dB
(1) Shaded cells indicate different specifications from standard-grade version of device.
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OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
ELECTRICAL CHARACTERISTICS: V
S
= ± 2.25V to ± 18V (continued)BOLDFACE limits apply over the specified temperature range, T
A
= – 40 ° C to +125 ° C.At T
A
= +25 ° C, R
L
= 10k Ωconnected to midsupply, V
CM
= V
OUT
= midsupply, unless otherwise noted.
Standard Grade High GradeOPA211AI, OPA2211AI OPA211I
(1)
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
OUTPUT
Voltage Output V
OUT
R
L
= 10k Ω, A
OL
≥114dB (V – ) + 0.2 (V+) – 0.2 (V – ) + 0.2 (V+) – 0.2 V
R
L
= 600 Ω, A
OL
≥110dB (V – ) + 0.6 (V+) – 0.6 (V – ) + 0.6 (V+) – 0.6 V
I
O
< 15mA, A
OL
≥110dB (V – ) + 0.6 (V+) – 0.6 (V – ) + 0.6 (V+) – 0.6 V
Short-Circuit Current I
SC
+30/ – 45 +30/ – 45 mA
Capacitive Load Drive C
LOAD
See Typical Characteristics See Typical Characteristics pF
Open-Loop Output Impedance Z
O
f = 1MHz 5 5 Ω
SHUTDOWN
Shutdown Pin Input Voltage
(2)
Device disabled (shutdown) (V+) – 0.35 (V+) – 0.35 V
Device enabled (V+) – 3 (V+) – 3 V
Shutdown Pin Leakage Current 1 1 µA
Turn-On Time
(3)
2 2 µs
Turn-Off Time
(3)
3 3 µs
Shutdown Current Shutdown (disabled) 1 20 1 20 µA
POWER SUPPLY
Specified Voltage V
S
± 2.25 ± 18 ± 2.25 ± 18 V
Quiescent Current
I
Q
I
OUT
= 0A 3.6 4.5 3.6 4.5 mA(per channel)
Over Temperature (per channel) 6 6 mA
TEMPERATURE RANGE
Specified Range T
A
– 40 +125 – 40 +125 ° C
Operating Range T
A
– 55 +150 – 55 +150 ° C
Thermal Resistance
OPA211
SO-8 θ
JA
150 150 ° C/W
MSOP-8 θ
JA
200 200 ° C/W
DFN-8 (3mm × 3mm) θ
JA
(4)
65 65 ° C/W
θ
JP
20 20 ° C/W
OPA2211
SO-8 PowerPAD θ
JA
(4)
52 52 ° C/W
θ
JP
2 2 ° C/W
DFN-8 (3mm × 3mm) θ
JA
(4)
65 65 ° C/W
θ
JP
10 10 ° C/W
(2) When disabled, the output assumes a high-impedance state.(3) See Typical Characteristic graphs, Figure 41 through Figure 43 .(4) Typical θ
JA
specification is based on the use of a high-k board.
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TYPICAL CHARACTERISTICS
CurrentNoiseDensity(pA/ )ÖHz
0.1
100
10
1
Frequency(Hz)
100k101 100 1k 10k
TotalHarmonicDistortion+Noise(%)
0.01
0.1
0.000001
OutputVoltageAmplitude(V )
RMS
100
0.00001
0.1 1 10
0.0001
0.001
0.01
-60
-160
-140
-120
-100
-80
TotalHarmonicDistortion+Noise(dB)
G=1
G=11
G= 1-
V = 15V
R =600
1kHzSignal
MeasurementBW=80kHz
S
L
±
W
TotalHarmonicDistortion+Noise(%)
10
Frequency(Hz)
20k100 1k 10k
TotalHarmonicDistortion+Noise(dB)
0.001
0.0001
0.00001
-
-
-
100
120
140
V = 15V±
S
V =3V
OUT RMS
MeasurementBW=80kHz
G=1
R =600W
L
G=11
R =600W
L
G= 1-
R =5kW
L
TotalHarmonicDistortion+Noise(%)
10
Frequency(Hz)
100k
100 1k 10k
TotalHarmonicDistortion+Noise(dB)
0.001
0.0001
0.00001
-
-
-
100
120
140
V = 15V±
S
V =3V
OUT RMS
MeasurementBW>500kHz
G=1
R =600W
L
G=11
R =600W
L
G= 1-
R =5kW
L
-
-
-
-
-
-
-
-
-
-
80
90
100
110
120
130
140
150
160
170
180-
ChannelSeparation(dB)
10
Frequency(Hz)
100k
100 1k 10k
V = 15V±
S
V =3.5V
IN RMS
G=1
R =2kW
L
R =600W
L
L
R =5kW
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY INPUT CURRENT NOISE DENSITYvs FREQUENCY vs FREQUENCY
Figure 1. Figure 2.
THD+N RATIO vs FREQUENCY THD+N RATIO vs OUTPUT VOLTAGE AMPLITUDE
Figure 3. Figure 4.
THD+N RATIO vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY
Figure 5. Figure 6.
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20nV/div
Time(1s/div)
PSRR(dB)
1 10
160
140
100
80
60
40
0
Frequency(Hz)
100M10k100 1k 100k
20
120
1M 10M
-PSRR
+PSRR
CMRR(dB)
10k
140
100
80
60
40
0
Frequency(Hz)
100M1M100k
20
120
10M
Z( )W
O
10
10k
0.1
Frequency(Hz)
100M
1
100 1k 10k
10
100
1k
100k 10M
1M
Gain(dB)
100 1k
140
120
100
80
60
40
-20
Frequency(Hz)
100M1M10k 100k 10M
20
0
Phase( )°
180
135
90
45
0
Gain
Phase
Open-LoopGain( V/V)m
-75
5
-5
Temperature( C)°
200
2
-50 -25 0
3
4
25 7550
1
100 125 150 175
0
-1
-2
-3
-4
300mVSwingFromRails
200mVSwingFromRails
R =10kW
L
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO0.1Hz TO 10Hz NOISE vs FREQUENCY (Referred to Input)
Figure 7. Figure 8.
COMMON-MODE REJECTION RATIO OPEN-LOOP OUTPUT IMPEDANCEvs FREQUENCY vs FREQUENCY
Figure 9. Figure 10.
GAIN AND PHASE vs FREQUENCY NORMALIZED OPEN-LOOP GAIN vs TEMPERATURE
Figure 11. Figure 12.
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
OffsetVoltageDrift(mV/°C)
Population
-125.0
-112.5
-100.0
-75.0
-62.5
-50.0
-37.5
-25.0
-12.5
0
12.5
25.0
37.5
50.0
62.5
75.0
87.5
100.0
112.5
125.0
OffsetVoltage( V)m
Population
-87.5
2000
1500
1000
500
0
-500
-1000
-1500
-2000
(V )+1.0-(V )+1.5-(V )+2.0-(V+) 1.5-(V+) 1.0-(V+) 0.5-
V (V)
CM
V ( V)m
OS
I (nA)
OS
2.25
100
-100
V ( V)±
S
18
20
4 6
40
60
80
8 10 12 14 16
0
-20
-40
-60
-80
5TypicalUnitsShown
V Shift( V)m
OS
0
12
-12
Time(s)
60
4
10 20 30
6
8
10 20TypicalUnitsShown
2
0
-2
-4
-6
-8
-10
40 50
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
Figure 13. Figure 14.
I
B
AND I
OS
CURRENT vs TEMPERATURE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
Figure 15. Figure 16.
V
OS
WARMUP INPUT OFFSET CURRENT vs SUPPLY VOLTAGE
Figure 17. Figure 18.
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I (nA)
OS
1
100
-100
V (V)
CM
35
75
5 10 15 20 25 30
0
-75
50
25
-25
-50
Common-ModeRange
V =36V
3TypicalUnitsShown
S
I(nA)
B
2.25
150
-150
V ( V)±
S
184 6
100
8 10
50
12 14 16
-IB
+IB
Unit1 Unit2
Unit3
3TypicalUnitsShown
0
-50
-100
I (nA)
B
1
150
-150
V (V)
CM
355 10
100
15 20 25 30
0
-100
50
-50
Common-ModeRange
-IB
+IB
Unit1 Unit2
Unit3
V =36V
3TypicalUnitsShown
S
I(mA)
Q
0
4.0
0
V (V)
S
36
2.0
4 8 12
2.5
3.0
3.5
16 2420
1.5
1.0
0.5
28 32
I Shift(mA)
Q
0
0.05
-0.30
Time(s)
600
-0.15
60 120 180
-0.10
-0.05
0
240 360300
-0.20
-0.25
420 480 540
Averageof10TypicalUnits
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs SUPPLY VOLTAGE
Figure 19. Figure 20.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE QUIESCENT CURRENT vs TEMPERATURE
Figure 21. Figure 22.
QUIESCENT CURRENT vs NORMALIZED QUIESCENT CURRENTSUPPLY VOLTAGE vs TIME
Figure 23. Figure 24.
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20mV/div
Time(0.1 s/div)m
G= 1
C =10pF
-
L
+18V
-18V
RF
604W
RI
604W
CF
5.6pF
CL
OPA211
I(mA)
SC
-75
60
-60
Temperature( C)°
200
20
-50 -25 0
30
40
50
25 7550
10
0
-10
100 125
-20
-30
-40
-50
150 175
Sourcing
Sinking
20mV/div
Time(0.1 s/div)m
G=+1
R =600
C =10pF
LW
L
+18V
-18V CL
RL
OPA211
20mV/div
Time(0.1 s/div)m
G= 1
C =100pF
-
L
+18V
-18V
RF
604W
RI
604W
CF
5.6pF
CL
OPA211
20mV/div
Time(0.1 s/div)m
G=+1
R =600
C =100pF
LW
L
+18V
-18V CL
RL
OPA211
Overshoot(%)
0 200
60
50
40
30
20
10
0
CapacitiveLoad(pF)
1400800400 600 1000 1200
G=+1
G= 1-
G=10
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
SHORT-CIRCUIT CURRENT SMALL-SIGNAL STEP RESPONSEvs TEMPERATURE (100mV)
Figure 25. Figure 26.
SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE(100mV) (100mV)
Figure 27. Figure 28.
SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL OVERSHOOT(100mV) vs CAPACITIVE LOAD (100mV Output Step)
Figure 29. Figure 30.
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Product Folder Link(s): OPA211 OPA2211
2V/div
Time(0.5 s/div)m
G= 1
C =100pF
R =600
-
W
L
L
2V/div
Time(0.5 s/div)m
G=+1
C =100pF
R =600
L
LW
R =100W
F
R =0W
F
Note:Seethe
section, .
ApplicationsInformation
InputProtection
0 100 200 300 400 500 1000600 700 800 900
Time(ns)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DFromFinalValue(mV)
0.010
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.010
DFromFinalValue(%)
16-Bit Settling
( 1/2LSB= 0.00075%)± ±
0 100 200 300 400 500 1000600 700 800 900
Time(ns)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DFromFinalValue(mV)
0.010
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.010
DFromFinalValue(%)
16-Bit Settling
( 1/2LSB= 0.00075%)± ±
0 100 200 300 400 500 1000600 700 800 900
Time(ns)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DromFinalVF alue(mV)
0.010
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.010
DFromFinalValue(%)
16-Bit Settling
( 1/2LSB= 0.00075%)± ±
0 100 200 300 400 500 1000600 700 800 900
Time(ns)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DFromFinalValue(mV)
0.010
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.010
DFromFinalValue(%)
16-Bit Settling
( 1/2LSB= 0.00075%)± ±
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE
Figure 31. Figure 32.
LARGE-SIGNAL POSITIVE SETTLING TIME LARGE-SIGNAL POSITIVE SETTLING TIME(10V
PP
, C
L
= 100pF) (10V
PP
, C
L
= 10pF)
Figure 33. Figure 34.
LARGE-SIGNAL NEGATIVE SETTLING TIME LARGE-SIGNAL NEGATIVE SETTLING TIME(10V
PP
, C
L
= 100pF) (10V
PP
, C
L
= 10pF)
Figure 35. Figure 36.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): OPA211 OPA2211
5V/div
Time(0.5 s/div)m
0V
VIN
VOUT
G= 10-
1kW
10kW
VIN
VOUT
OPA211
5V/div
Time(0.5 s/div)m
0V
VIN
VOUT
G= 10-
1kW
10kW
VIN
VOUT
OPA211
5V/div
0.5ms/div
Output
+18V
-18V
37VPP
( 18.5V)±
Output OPA211
0 10 20 30 40 50 7060
I (mA)
OUT
20
15
10
5
0
-5
-10
-15
-20
V (V)
OUT
+125 C°
0 C°
+85 C°
+125 C°
+85 C°
+150 C°
- °55 C 0 C°
5V/div
20
15
10
5
0
5
10
15
20
-
-
-
-
Time(2 s/div)m
ShutdownSignal
OutputSignal
V = 15V±
S
5V/div
20
15
10
5
0
5
10
15
20
-
-
-
-
Time(2 s/div)m
ShutdownSignal
OutputSignal
V = 15V±
S
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
NEGATIVE OVERLOAD RECOVERY POSITIVE OVERLOAD RECOVERY
Figure 37. Figure 38.
OUTPUT VOLTAGE vs OUTPUT CURRENT NO PHASE REVERSAL
Figure 39. Figure 40.
TURN-OFF TRANSIENT TURN-ON TRANSIENT
Figure 41. Figure 42.
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Product Folder Link(s): OPA211 OPA2211
ShutdownPinVoltage(V)
20
15
10
5
0
5
10
15
20
-
-
-
-
Time(100 s/div)m
ShutdownSignal
OutputVoltage(V)
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
-
-
-
-
Output
V = 15V±
S
OPA211
OPA2211
www.ti.com
...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 ° C, V
S
= ± 18V, and R
L
= 10k Ω, unless otherwise noted.
TURN-ON/TURN-OFF TRANSIENT
Figure 43.
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Product Folder Link(s): OPA211 OPA2211
APPLICATION INFORMATION
OPERATING VOLTAGE
IN-
Pre-OutputDriver OUT
IN+
V-
V+
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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negative output voltage swing. With the OPA211The OPA211 and OPA2211 are unity-gain stable,
series, power-supply voltages do not need to beprecision op amps with very low noise. Applications
equal. For example, the positive supply could be setwith noisy or high-impedance power supplies require
to +25V with the negative supply at – 5V ordecoupling capacitors close to the device pins. In
vice-versa.most cases, 0.1 µF capacitors are adequate.Figure 44 shows a simplified schematic of the The common-mode voltage must be maintainedOPA211. This die uses a SiGe bipolar process and within the specified range. In addition, keycontains 180 transistors. parameters are assured over the specifiedtemperature range, T
A
= – 40 ° C to +125 ° C.Parameters that vary significantly with operatingvoltage or temperature are shown in the TypicalOPA211 series op amps operate from ± 2.25V to
Characteristics .± 18V supplies while maintaining excellentperformance. The OPA211 series can operate with aslittle as +4.5V between the supplies and with up to+36V between the supplies. However, someapplications do not require equal positive and
Figure 44. OPA211 Simplified Schematic
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INPUT PROTECTION NOISE PERFORMANCE
OPA211 Output
RF
Input
-
+
RI
VOLTAGENOISESPECTRALDENSITY
vsSOURCERESISTANCE
100k 1M
SourceResistance,R ( )W
S
100 1k 10k
10k
1k
100
10
1
VotlageNoiseSpectralDensity,EO
RS
EO
E =e
O n S
+(i R ) +4kTR
n S
2 2 2
ResistorNoise
OPA227
OPA211
SHUTDOWN
BASIC NOISE CALCULATIONS
OPA211
OPA2211
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...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
The input terminals of the OPA211 are protected from Figure 46 shows total circuit noise for varying sourceexcessive differential voltage with back-to-back impedances with the op amp in a unity-gaindiodes, as shown in Figure 45 . In most circuit configuration (no feedback resistor network, andapplications, the input protection circuitry has no therefore no additional noise contributions). Twoconsequence. However, in low-gain or G = 1 circuits, different op amps are shown with total circuit noisefast ramping input signals can forward bias these calculated. The OPA211 has very low voltage noise,diodes because the output of the amplifier cannot making it ideal for low source impedances (less thanrespond rapidly enough to the input ramp. This effect 2k Ω). A similar precision op amp, the OPA227 , hasis illustrated in Figure 32 of the Typical somewhat higher voltage noise but lower currentCharacteristics. If the input signal is fast enough to noise. It provides excellent noise performance atcreate this forward bias condition, the input signal moderate source impedance (10k Ωto 100k Ω). Abovecurrent must be limited to 10mA or less. If the input 100k Ω, a FET-input op amp such as the OPA132signal current is not inherently limited, an input series (very low current noise) may provide improvedresistor can be used to limit the signal input current. performance. The equation in Figure 46 is shown forThis input series resistor degrades the low-noise the calculation of the total circuit noise. Note that e
n
=performance of the OPA211, and is discussed in the voltage noise, I
n
= current noise, R
S
= sourceNoise Performance section of this data sheet. impedance, k = Boltzmann ’ s constant = 1.38 × 10
– 23
Figure 45 shows an example implementing a J/K, and T is temperature in degrees Kelvin.current-limiting feedback resistor.
Figure 45. Pulsed Operation
The shutdown (enable) function of the OPA211 is
Figure 46. Noise Performance of the OPA211 andreferenced to the positive supply voltage of the OPA227 in Unity-Gain Buffer Configurationoperational amplifier. A valid high disables the opamp. A valid high is defined as (V+) – 0.35V of thepositive supply applied to the shutdown pin. A validlow is defined as (V+) – 3V below the positive supply
Design of low-noise op amp circuits requires carefulpin. For example, with V
CC
at ± 15V, the device is
consideration of a variety of possible noiseenabled at or below 12V. The device is disabled at or
contributors: noise from the signal source, noiseabove 14.65V. If dual or split power supplies are
generated in the op amp, and noise from theused, care should be taken to ensure the valid high
feedback network resistors. The total noise of theor valid low input signals are properly referred to the
circuit is the root-sum-square combination of all noisepositive supply voltage. This pin must be connected
components.to a valid high or low voltage or driven, and not leftopen-circuit. The enable and disable times are The resistive portion of the source impedanceprovided in the Typical Characteristics section (see produces thermal noise proportional to the squareFigure 41 through Figure 43 ). When disabled, the root of the resistance. This function is plotted inoutput assumes a high-impedance state. Figure 46 . The source impedance is usually fixed;consequently, select the op amp and the feedbackresistors to minimize the respective contributions tothe total noise.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): OPA211 OPA2211
R1
R2
EO
R1
R2
EO
RS
VS
RS
VS
NoiseinNoninvertingGainConfiguration
NoiseinInvertingGainConfiguration
Noiseattheoutput:
E =
O
2
Wheree = Ö
S S
4kTR ´=thermalnoiseofRS
2
1+ R2
R1
e +e
n1 2 n2 S S
+e +(i R ) +e +(inR )
2 2 2 2 2 2
1+ R2
R1
R2
R1
e = Ö
1 1
4kTR ´=thermalnoiseofR1
2
1+ R2
R1
e = Ö
2 2 2
4kTR =thermalnoiseofR
Noiseattheoutput:
E =
O
2
Wheree = 4kTRÖ
S S ´=thermalnoiseofRS
2
1+ R2
R +R
1 S
e +e
n 1 2 n 2 S
+e +(i R ) +e
2 2 2 2 2
R2
R +R
1 S
R2
R +R
1 S
e = 4kTRÖ
1 1 ´=thermalnoiseofR1
e = 4kTRÖ
2 2 2
=thermalnoiseofR
FortheOPA211seriesopampsat1kHz,e =1.1nV/ Hzandi =1.7pA/ Hz.Ö Ö
n n
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
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Figure 46 depicts total noise for varying source Therefore, the lowest noise op amp for a givenimpedances with the op amp in a unity-gain application depends on the source impedance. Forconfiguration (no feedback resistor network, and low source impedance, current noise is negligible andtherefore no additional noise contributions). The voltage noise generally dominates. For high sourceoperational amplifier itself contributes both a voltage impedance, current noise may dominate.noise component and a current noise component.
Figure 47 illustrates both inverting and noninvertingThe voltage noise is commonly modeled as a
op amp circuit configurations with gain. In circuittime-varying component of the offset voltage. The
configurations with gain, the feedback networkcurrent noise is modeled as the time-varying
resistors also contribute noise. The current noise ofcomponent of the input bias current and reacts with
the op amp reacts with the feedback resistors tothe source resistance to create a voltage component
create additional noise components. The feedbackof noise.
resistor values can generally be chosen to makethese noise sources negligible. The equations fortotal noise are shown for both configurations.
Figure 47. Noise Calculation in Gain Configurations
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TOTAL HARMONIC DISTORTION
ELECTRICAL OVERSTRESS
R2
OPA211
R1
SignalGain=1+
DistortionGain=1+
R3VOUT
Generator
Output
Analyzer
Input
AudioPrecision
SystemTwo(1)
withPCController
Load
SIG.
GAIN
DIST.
GAIN R1R2R3
¥
100W
1kW
1kW
10W
11W
1
11
101
101
R2
R1
R2
R IIR
1 3
OPA211
OPA2211
www.ti.com
...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
Audio Precision System Two distortion/noiseMEASUREMENTS analyzer, which greatly simplifies such repetitivemeasurements. The measurement technique can,OPA211 series op amps have excellent distortion
however, be performed with manual distortioncharacteristics. THD + Noise is below 0.0002% (G =
measurement instruments.+1, V
OUT
= 3V
RMS
) throughout the audio frequencyrange, 20Hz to 20kHz, with a 600 Ωload.
The distortion produced by OPA211 series op amps
Designers often ask questions about the capability ofis below the measurement limit of many commercially
an operational amplifier to withstand electricalavailable distortion analyzers. However, a special test
overstress. These questions tend to focus on thecircuit illustrated in Figure 48 can be used to extend
device inputs, but may involve the supply voltage pinsthe measurement capabilities.
or even the output pin. Each of these different pinOp amp distortion can be considered an internal error functions have electrical stress limits determined bysource that can be referred to the input. Figure 48 the voltage breakdown characteristics of theshows a circuit that causes the op amp distortion to particular semiconductor fabrication process andbe 101 times greater than that normally produced by specific circuits connected to the pin. Additionally,the op amp. The addition of R
3
to the otherwise internal electrostatic discharge (ESD) protection isstandard noninverting amplifier configuration alters built into these circuits to protect them fromthe feedback factor or noise gain of the circuit. The accidental ESD events both before and duringclosed-loop gain is unchanged, but the feedback product assembly.available for error correction is reduced by a factor of
It is helpful to have a good understanding of this101, thus extending the resolution by 101. Note that
basic ESD circuitry and its relevance to an electricalthe input signal and load applied to the op amp are
overstress event. See Figure 49 for an illustration ofthe same as with conventional feedback without R
3
.
the ESD circuits contained in the OPA211 (indicatedThe value of R
3
should be kept small to minimize its
by the dashed line area). The ESD protection circuitryeffect on the distortion measurements.
involves several current-steering diodes connectedValidity of this technique can be verified by from the input and output pins and routed back to theduplicating measurements at high gain and/or high internal power-supply lines, where they meet at anfrequency where the distortion is within the absorption device internal to the operational amplifier.measurement capability of the test equipment. This protection circuitry is intended to remain inactiveMeasurements for this data sheet were made with an during normal circuit operation.
(1) For measurement bandwidth, see Figure 3 ,Figure 4 , and Figure 5 .
Figure 48. Distortion Test Circuit
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): OPA211 OPA2211
RF
Op-Amp
Core
RI
RL
V(1)
IN
ID
-In
Out
+In
ESDCurrent-
SteeringDiodes
Edge-TriggeredESD
AbsorptionCircuit
+VS
+V
-V
-VS
OPA211
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
www.ti.com
(1) V
IN
= +V
S
+ 500mV.
Figure 49. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
An ESD event produces a short duration,
Figure 49 depicts a specific example where the inputhigh-voltage pulse that is transformed into a short
voltage, V
IN
, exceeds the positive supply voltageduration, high-current pulse as it discharges through
(+V
S
) by 500mV or more. Much of what happens ina semiconductor device. The ESD protection circuits
the circuit depends on the supply characteristics. Ifare designed to provide a current path around the
+V
S
can sink the current, one of the upper inputoperational amplifier core to prevent it from being
steering diodes conducts and directs current to +V
S
.damaged. The energy absorbed by the protection
Excessively high current levels can flow withcircuitry is then dissipated as heat.
increasingly higher V
IN
. As a result, the datasheetWhen an ESD voltage develops across two or more specifications recommend that applications limit theof the amplifier device pins, current flows through one input current to 10mA.or more of the steering diodes. Depending on the
If the supply is not capable of sinking the current, V
INpath that the current takes, the absorption device
may begin sourcing current to the operationalmay activate. The absorption device has a trigger, or
amplifier, and then take over as the source of positivethreshold voltage, that is above the normal operating
supply voltage. The danger in this case is that thevoltage of the OPA211 but below the device
voltage can rise to levels that exceed the operationalbreakdown voltage level. Once this threshold is
amplifier absolute maximum ratings. In extreme butexceeded, the absorption device quickly activates
rare cases, the absorption device triggers on whileand clamps the voltage across the supply rails to a
+V
S
and – V
S
are applied. If this event happens, asafe level.
direct current path is established between the +V
SWhen the operational amplifier connects into a circuit and – V
S
supplies. The power dissipation of thesuch as that illustrated in Figure 49 , the ESD absorption device is quickly exceeded, and theprotection components are intended to remain extreme internal heating destroys the operationalinactive and not become involved in the application amplifier.circuit operation. However, circumstances may arise
Another common question involves what happens towhere an applied voltage exceeds the operating
the amplifier if an input signal is applied to the inputvoltage range of a given pin. Should this condition
while the power supplies +V
S
and/or – V
S
are at 0V.occur, there is a risk that some of the internal ESD
Again, it depends on the supply characteristic while atprotection circuits may be biased on, and conduct
0V, or at a level below the input signal amplitude. Ifcurrent. Any such current flow occurs through
the supplies appear as high impedance, then thesteering diode paths and rarely involves the
operational amplifier supply current may be suppliedabsorption device.
by the input source via the current steering diodes.This state is not a normal bias condition; the amplifier
18 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
THERMAL CONSIDERATIONS
DFN LAYOUT GUIDELINES
DFN PACKAGE
OPA211
OPA2211
www.ti.com
...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
most likely will not operate normally. If the supplies DFN packages are physically small, and have aare low impedance, then the current through the smaller routing area, improved thermal performance,steering diodes can become quite high. The current and improved electrical parasitics. Additionally, thelevel depends on the ability of the input source to absence of external leads eliminates bent-leaddeliver current, and any resistance in the input path. issues.
The DFN package can be easily mounted usingstandard printed circuit board (PCB) assemblytechniques. See Application Note QFN/SON PCBA primary issue with all semiconductor devices is
Attachment (SLUA271 ) and Application Report Quadjunction temperature (T
J
). The most obvious
Flatpack No-Lead Logic Packages (SCBA017 ), bothconsideration is assuring that T
J
never exceeds the
available for download at www.ti.com .absolute maximum rating specified for the device.However, addressing device thermal dissipation has
The exposed leadframe die pad on the bottom ofbenefits beyond protecting the device from damage.
the package must be connected to V – . SolderingEven modest increases in junction temperature can
the thermal pad improves heat dissipation anddecrease op amp performance, and
enables specified device performance.temperature-related errors can accumulate.Understanding the power generated by the devicewithin the specific application and assessing thethermal effects on the error tolerance lead to a better
The exposed leadframe die pad on the DFN packageunderstanding of system performance and
should be soldered to a thermal pad on the PCB. Athermal-dissipation needs. For dual-channel products,
mechanical drawing showing an example layout isthe worst-case power resulting from both channels
attached at the end of this data sheet. Refinements tomust be determined. Products with a thermal pad
this layout may be necessary based on assembly(DFN and PowerPAD devices) provide the best
process requirements. Mechanical drawings locatedthermal conduction away from the junction; see the
at the end of this data sheet list the physicalThermal Resistance from Junction to Pad parameter
dimensions for the package and pad. The five holes(θ
JP
) in the Electrical Characteristics section. The use
in the landing pattern are optional, and are intendedof packages with a thermal pad improves thermal
for use with thermal vias that connect the leadframedissipation. The device achieves its optimal
die pad to the heatsink area on the PCB.performance through careful board and system
Soldering the exposed pad significantly improvesdesign that considers characteristics such as board
board-level reliability during temperature cycling, keythickness, metal layers, component spacing, airflow,
push, package shear, and similar board-level tests.and board orientation. Refer to these application
Even with applications that have low-powernotes (available for download at www.ti.com ) for
dissipation, the exposed pad must be soldered to theadditional details: SZZA017A ,SCBA017 , and
PCB to provide structural integrity and long-termSPRA953A . For unusual loads and signals, see
reliability.SBOA022 .
The OPA211 is offered in an DFN-8 package (alsoknown as SON). The DFN package is a QFNpackage with lead contacts on only two sides of thebottom of the package. This leadless packagemaximizes board space and enhances thermal andelectrical characteristics through an exposed pad.
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
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GENERAL POWERPAD DESIGN
OPA211
OPA2211
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example thermal land pattern mechanical drawingCONSIDERATIONS is attached to the end of this data sheet.3. Additional vias may be placed anywhere alongThe OPA2211 is available in a thermally-enhanced
the thermal plane outside of the thermal pad areaSO-8 PowerPAD package. This package is
to help dissipate the heat generated by theconstructed using a downset leadframe upon which
OPA2211 SO-8. These additional vias may bethe die is mounted, as Figure 50 (a) and Figure 50 (b)
larger than the 13-mil diameter vias directly underillustrate. This arrangement results in the lead frame
the thermal pad. They can be larger becausebeing exposed as a thermal pad on the underside of
they are not in the thermal pad area to bethe package, as shown in Figure 50 (c). This thermal
soldered; thus, wicking is not a problem.pad has direct thermal contact with the die; thus,excellent thermal performance is achieved by 4. Connect all holes to the internal plane that is atproviding a good thermal path away from the thermal the same voltage potential as the V – pin.pad.
5. When connecting these holes to the internalplane, do not use the typical web or spoke viaThe PowerPAD package allows for both assembly
connection methodology. Web connections haveand thermal management in one manufacturing
a high thermal resistance connection that isoperation. During the surface-mount solder operation
useful for slowing the heat transfer during(when the leads are being soldered), the thermal pad
soldering operations. This configuration makesmust be soldered to a copper area underneath the
the soldering of vias that have plane connectionspackage. Through the use of thermal paths within this
easier. In this application, however, low thermalcopper area, heat can be conducted away from the
resistance is desired for the most efficient heatpackage into either a ground plane or other
transfer. Therefore, the holes under the OPA2211heat-dissipating device. Soldering the PowerPAD to
PowerPAD package should make theirthe printed circuit board (PCB) is always required,
connection to the internal plane with a completeeven with applications that have low power
connection around the entire circumference of thedissipation. This technique provides the necessary
plated-through hole.thermal and mechanical connection between the leadframe die pad and the PCB. 6. The top-side solder mask should leave theterminals of the package and the thermal padThe PowerPAD must be connected to the most
area with its six holes exposed. The bottom-sidenegative supply voltage on the device (V – ).
solder mask should cover the holes of the1. Prepare the PCB with a top-side etch pattern.
thermal pad area. This masking prevents solderThere should be etching for the leads as well as
from being pulled away from the thermal padetch for the thermal pad.
area during the reflow process.2. Place recommended holes in the area of the
7. Apply solder paste to the exposed thermal padthermal pad. Ideal thermal land size and thermal
area and all of the IC terminals.via patterns for the SO-8 DDA package can be
8. With these preparatory steps in place, simplyseen in the technical brief, PowerPAD
place the OPA2211 SO-8 IC in position and runThermally-Enhanced Package (SLMA002 ),
the chip through the solder reflow operation asavailable for download at www.ti.com. These
any standard surface-mount component. Thisholes should be 13 mils (0,33mm) in diameter.
preparation results in a properly installed part.Keep them small, so that solder wicking throughthe holes is not a problem during reflow. An
20 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
Die
DieAttach(Epoxy)
Leadframe
(CopperAlloy)
ExposedatBaseofPackage
MoldCompound
(Plastic)
Terminal
(b)CutawayView:DRGPackage(DFN-8)
MoldCompound(Plastic)
LeadframeDiePad
ExposedatBaseofthePackage
(CopperAlloy)
Leadframe(CopperAlloy)
IC(Silicon) DieAttach(Epoxy)
(a)CutawayView:DDAPackage(SO-8)
(c)BottomView
DRGPackage
(DFN-8)
Thermal
Pad
DDAPackage
(SO-8)
Thermal
Pad
OPA211
OPA2211
www.ti.com
...................................................................................................................................................... SBOS377G – OCTOBER 2006 – REVISED MAY 2009
Figure 50. Views of Thermally-Enhanced SO-8 and DFN-8 Packages
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): OPA211 OPA2211
OPA211
OPA2211
SBOS377G – OCTOBER 2006 – REVISED MAY 2009 ......................................................................................................................................................
www.ti.com
REVISION HISTORYNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November, 2008) to Revision G .......................................................................................... Page
•Changed orderable status of OPA2211 device packages to released from product preview throughout document ............ 2•Revised description of NC pin ............................................................................................................................................... 3•Added Input Offset Voltage,Input Bias Current,Open-Loop Gain, and Thermal Resistance specifications to indicateperformance for OPA2211 device ......................................................................................................................................... 4•Corrected Temperature Range parametric symbol location for specified and operating range specifications ..................... 5•Added footnote (4) to Electrical Characteristics table ............................................................................................................ 5•Updated Figure 3 ................................................................................................................................................................... 6•Added information to legend in Figure 4 ................................................................................................................................ 6•Added Figure 5 ..................................................................................................................................................................... 6•Added Figure 6 ...................................................................................................................................................................... 6•Changed title of Figure 12 for clarification ............................................................................................................................. 7•Corrected circuit drawing in Figure 26 ................................................................................................................................. 10•Corrected circuit drawing in Figure 27 ................................................................................................................................. 10•Changed first paragraph of Total Harmonic Distortion Measurements section ................................................................... 17•Updated Figure 48 ............................................................................................................................................................... 17•Added Thermal Considerations section ............................................................................................................................... 19•Added General PowerPAD Design Considerations section ................................................................................................ 20
22 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): OPA211 OPA2211
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA211AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDRGR ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDRGRG4 ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDRGT ACTIVE SON DRG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211AIDRGTG4 ACTIVE SON DRG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA211IDRGR ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA211IDRGT ACTIVE SON DRG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2211AIDDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2211AIDDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
OPA2211AIDRGR ACTIVE SON DRG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2211AIDRGT ACTIVE SON DRG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA211 :
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
•Enhanced Product: OPA211-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA211AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA211AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA211AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA211AIDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA211AIDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA211IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA211IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA211IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA211IDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA211IDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA2211AIDDAR SO
Power
PAD
DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2211AIDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA2211AIDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA211AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
OPA211AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA211AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA211AIDRGR SON DRG 8 3000 367.0 367.0 35.0
OPA211AIDRGT SON DRG 8 250 210.0 185.0 35.0
OPA211IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
OPA211IDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA211IDR SOIC D 8 2500 367.0 367.0 35.0
OPA211IDRGR SON DRG 8 3000 367.0 367.0 35.0
OPA211IDRGT SON DRG 8 250 210.0 185.0 35.0
OPA2211AIDDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
OPA2211AIDRGR SON DRG 8 3000 367.0 367.0 35.0
OPA2211AIDRGT SON DRG 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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