1
FEATURES APPLICATIONS
DESCRIPTION
VIN
NC
NC
ENA
GND
VSENSE
BOOT
PH
VIN VOUT
SimplifiedSchematic EfficiencyvsOutputCurrent
50
55
60
65
70
75
80
85
90
95
100
I - Output Current - A
O
Efficiency-%
0 1 2 3 4 5 6
V =12V,
V =5V,
f =500kHz,
T =25°C
I
O
s
A
TPS5450
SLVS757 – MARCH 2007www.ti.com
5-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER
•High Density Point-of-Load Regulators2
•Wide Input Voltage Range: 5.5 V to 36 V
•LCD Displays, Plasma Displays•Up to 5-A Continuous (6-A Peak) Output
•Battery ChargersCurrent
•12-V/24-V Distributed Power Systems•High Efficiency Greater than 90% Enabled by110-m ΩIntegrated MOSFET Switch•Wide Output Voltage Range: Adjustable Downto 1.22 V with 1.5% Initial Accuracy
As a member of the SWIFT™ family of DC/DCregulators, the TPS5450 is a high-output-current•Internal Compensation Minimizes External
PWM converter that integrates a low resistance highParts Count
side N-channel MOSFET. Included on the substrate•Fixed 500 kHz Switching Frequency for Small
with the listed features are a high performanceFilter Size
voltage error amplifier that provides tight voltageregulation accuracy under transient conditions; an•18 μA Shut Down Supply Current
undervoltage-lockout circuit to prevent start-up until•Improved Line Regulation and Transient
the input voltage reaches 5.5 V; an internally setResponse by Input Voltage Feed Forward
slow-start circuit to limit inrush currents; and a voltage•System Protected by Overcurrent Limiting,
feed-forward circuit to improve the transientOvervoltage Protection and Thermal Shutdown
response. Using the ENA pin, shutdown supplycurrent is reduced to 18 μA typically. Other features•– 40 °C to 125 °C Operating Junction
include an active-high enable, overcurrent limiting,Temperature Range
overvoltage protection and thermal shutdown. To•Available in Small Thermally Enhanced 8-Pin
reduce design complexity and external componentSOIC PowerPAD™ Package
count, the TPS5450 feedback loop is internally•For SWIFT™ Documentation, Application
compensated.Notes and Design Software, See the TI Website
The TPS5450 device is available in a thermallyat www.ti.com/swift
enhanced, 8-pin SOIC PowerPAD™ package. TIprovides evaluation modules and software tool to aidin achieving high-performance power supply designsto meet aggressive equipment development cycles.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – , Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1) (2)
RECOMMENDED OPERATING CONDITIONS
TPS5450
SLVS757 – MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE
(1)
PART NUMBER
– 40 °C to 125 °C 5.5 V to 36 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA)
(2)
TPS5450DDA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5450DDAR). See applications sectionof data sheet for PowerPAD™ drawing and layout information.
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
VIN – 0.3 to 40
(3)
V
I
Input voltage range BOOT – 0.3 to 50PH (steady-state) – 0.6 to 40
(3)
ENA – 0.3 to 7 VBOOT-PH 10VSENSE – 0.3 to 3PH (transient < 10 ns) – 1.2I
O
Source current PH Internally LimitedI
lkg
Leakage current PH 10 μAT
J
Operating virtual junction temperature range – 40 to 150 °CT
stg
Storage temperature – 65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
THERMAL IMPEDANCEPACKAGE
JUNCTION-TO-AMBIENT
8 Pin DDA (4-layer board with solder)
(3)
30 °C/W
(1) Maximum power dissipation may be limited by overcurrent protection.(2) Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 125 °C. This is the point wheredistortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at orbelow 125 °C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for moreinformation.
(3) Test board conditions:a. 2 in x 1.85 in, 4 layers, thickness: 0.062 inch (1,57 mm).b. 2 oz. copper traces located on the top and bottom of the PCB.c. 2 oz. copper ground planes on the 2 internal layers.d. 4 thermal vias in the PowerPAD area under the device package.
MIN NOM MAX UNIT
V
I
Input voltage range 5.5 36 VT
J
Operating junction temperature – 40 125 °C
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ELECTRICAL CHARACTERISTICS
TPS5450
SLVS757 – MARCH 2007
T
J
= – 40 °C to 125 °C, VIN = 5.5 V - 36 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VSENSE = 2 V, Not switching,
3 4.4 mAPH pin openI
Q
Quiescent current
Shutdown, ENA = 0 V 18 50 μA
UNDERVOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO 5.3 5.5 VHysteresis voltage, UVLO 330 mV
VOLTAGE REFERENCE
T
J
= 25 °C 1.202 1.221 1.239Voltage reference accuracy VI
O
= 0 A – 5 A 1.196 1.221 1.245
OSCILLATOR
Internally set free-running frequency 400 500 600 kHzMinimum controllable on time 150 200 nsMaximum duty cycle 87 89 %
ENABLE (ENA PIN)
Start threshold voltage, ENA 1.3 VStop threshold voltage, ENA 0.5 VHysteresis voltage, ENA 450 mVInternal slow-start time (0~100%) 6.6 8 10 ms
CURRENT LIMIT
Current limit 6.0 7.5 9.0 ACurrent limit hiccup time 13 16 20 ms
THERMAL SHUTDOWN
Thermal shutdown trip point 135 162 °CThermal shutdown hysteresis 14 °C
OUTPUT MOSFET
VIN = 5.5 V 150r
DS(on)
High-side power MOSFET switch m Ω110 230
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PIN ASSIGNMENTS
1
2
3
4
8
7
6
5
PowerPAD
(Pin9)
BOOT
NC
NC
VSENSE
PH
VIN
GND
ENA
DDAPACKAGE
(TOPVIEW)
TPS5450
SLVS757 – MARCH 2007
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTIONNAME NO.
BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin.NC 2, 3 Not connected internally.VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider.ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.GND 6 Ground. Connect to PowerPAD.Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramicVIN 7
capacitor.PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.PowerPAD 9 GND pin must be connected to the exposed pad for proper operation.
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TYPICAL CHARACTERISTICS
2.5
2.75
3
3.25
3.5
−50 −25 0 25 50 75 100 125
TJ−JunctionT emperature − °C
IQ−QuiescentCurrent −mA
V =12V
I
460
470
480
490
500
510
520
530
−50 −25 0 25 50 75 100 125
f − OscillatorFrequency − kHz
T − JunctionTemperature − °C
1.210
1.215
1.220
1.225
1.230
-50 -25 0 25 50 75 100 125
T -JunctionTemperature-°C
J
V -VoltageReference-V
REF
5
10
15
20
25
0 5 10 15 20 25 30 35 40
TJ=125°C
TJ=27°C
TJ=– °40 C
ENA=0V
VI−InputV oltage −V
ISD −ShutdownCurrent −Aµ
7
7.5
8
8.5
9
−50 −25 0 25 50 75 100 125
TJ− JunctionTemperature − °C
TSS− InternalSlowStartT
ime − ms
TPS5450
SLVS757 – MARCH 2007
OSCILLATOR FREQUENCY NON-SWITCHING QUIESCENT CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2.
SHUTDOWN QUIESCENT CURRENT VOLTAGE REFERENCEvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 3. Figure 4.
ON RESISTANCE INTERNAL SLOW START TIMEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
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120
130
140
150
160
170
180
−50 −25 0 25 50 75 100 125
TJ− JunctionTemperature − °C
MinimumControllableOnT
ime − ns
TPS5450
SLVS757 – MARCH 2007
TYPICAL CHARACTERISTICS (continued)
MINIMUM CONTROLLABLE ON TIME MINIMUM CONTROLLABLE DUTY RATIOvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 7. Figure 8.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
UVLO
ENABLE
Thermal
Protection
Reference
Overcurrent
GateDrive
Oscillator
Ramp
Generator
VREF
PH
ENA
GND
BOOT
Z1
Z2
SHDN
SHDN
SHDN
SHDN
SHDN
SHDN
SHDN
SHDN
VIN
112.5%VREF
VSENSE OVP
HICCUP
HICCUP
SHDN
NC
FeedForward
BOOT
NC
POWERPAD
VIN
VOUT
5 µA
1.221VBandgap SlowStart Boot
Regulator
Error
Amplifier
Gain=25
PWM
Comparator
Protection
Gate
Driver
Control
VSENSE
DETAILED DESCRIPTION
Oscillator Frequency
Voltage Reference
Enable (ENA) and Internal Slow Start
TPS5450
SLVS757 – MARCH 2007
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switchingfrequency allows less output inductance for the same output ripple requirement resulting in a smaller outputinductor.
The voltage reference system produces a precision reference signal by scaling the output of a temperaturestable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of1.221 V at room temperature.
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the thresholdvoltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulledbelow the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pinto ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. Thequiescent current of the TPS5450 in shutdown mode is typically 18 μA.
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Undervoltage Lockout (UVLO)
Boost Capacitor (BOOT)
Output Feedback (VSENSE) and Internal Compensation
Voltage Feed Forward
Feed Forward Gain +VIN
Ramppk*pk
(1)
Pulse-Width-Modulation (PWM) Control
Overcurrent Limiting
TPS5450
SLVS757 – MARCH 2007
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an applicationrequires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limitthe start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to itsfinal value, linearly. The internal slow start time is 8 ms typically.
The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the inputvoltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and theinternal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO startthreshold voltage is reached, the internal slow start is released and device start-up begins. The device operatesuntil VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides thegate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stablevalues over temperature.
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor dividernetwork to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltagereference 1.221 V.
The TPS5450 implements internal compensation to simplify the regulator design. Since the TPS5450 usesvoltage mode control, a type 3 compensation network has been designed on chip to provide a high crossoverfrequency and a high phase margin for good stability. See the Internal Compensation Network in the applicationssection for more details.
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the inputvoltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forwardvaries the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain areconstant at the feed forward gain, i.e.
The typical feed forward gain of TPS5450 is 25.
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedbackvoltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier andcompensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by thePWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. Thedrain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If thedrain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The systemwill ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid anyturn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off forthe rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle currentlimiting.
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Overvoltage Protection
Thermal Shutdown
PCB Layout
TPS5450
SLVS757 – MARCH 2007
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happenwhen using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup modeovercurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-sideMOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts undercontrol of the slow start circuit.
The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering fromoutput fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltageand a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-sideMOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-sideMOSFET will be enabled again.
The TPS5450 protects itself from overheating with an internal thermal shutdown circuit. If the junctiontemperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-sideMOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junctiontemperature drops 14 °C below the thermal shutdown trip point.
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop areaformed by the bypass capacitor connections, the VIN pin, and the TPS5450 ground pin. The best way to do thisis to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypasscapacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramicwith a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connectionto the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at theground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground byconnecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection isthe switching node, the inductor should be located very close to the PH pin and the area of the PCB conductorminimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device tominimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin asshown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The componentplacements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep theloop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do notroute this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the tracemay need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if atrace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 9 , use a via connection to a different layer to route to the ENApin.
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BOOT
NC
NC
VSENSE
PH
VIN
GND
ENA
Vout
PH Vin
TOPSIDEGROUND AREA
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
CATCH
DIODE
RouteINPUT VOLTAGE
traceunderthecatchdiode
andoutputcapacitor
oronanotherlayer
SignalVIA
RESISTOR
DIVIDER
Feedback Trace
EXPOSED
POWERPAD
AREA
TPS5450
SLVS757 – MARCH 2007
Figure 9. Design Layout
Figure 10. TPS5450 Land Pattern
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Application Circuits
Design Procedure
TPS5450
SLVS757 – MARCH 2007
Figure 11 shows the schematic for a typical TPS5450 application. The TPS5450 can provide up to 5-A outputcurrent at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™underneath the device must be soldered down to the printed-circuit board.
Figure 11. Application Circuit, 12-V to 5.0-V
The following design procedure can be used to select component values for the TPS5450. Alternately, theSWIFT™ Designer Software may be used to generate a complete design. The SWIFT™ Designer Software usesan iterative design procedure and accesses a comprehensive database of components when generating adesign. This section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:•Input voltage range•Output voltage•Input ripple voltage•Output ripple voltage•Output current rating•Operating frequency
Design Parameters
For this design example, use the following as the input parameters:DESIGN PARAMETER
(1)
EXAMPLE VALUE
Input voltage range 10 V to 31 VOutput voltage 5 VInput ripple voltage 400 mVOutput ripple voltage 30 mVOutput current rating 5 AOperating frequency 500 kHz
(1) As an additional constraint, the design is set up to be small size and low component height.
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DVIN +
IOUT(MAX) 0.25
CBULK ƒsw )ǒIOUT(MAX) ESRMAXǓ
(2)
ICIN +
IOUT(MAX)
2
(3)
LMIN +
VOUT(MAX) ǒVIN(MAX) *VOUTǓ
VIN(MAX) KIND IOUT FSW(MIN)
(4)
TPS5450
SLVS757 – MARCH 2007
Switching Frequency
The switching frequency for the TPS5450 is internally set to 500 kHz. It is not possible to adjust the switchingfrequency.
Input Capacitors
The TPS5450 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.The minimum recommended decoupling capacitance is 4.7 μF. A high quality ceramic type X5R or X7R isrequired. For some applications, a smaller value decoupling capacitor may be used, so long as the input voltageand current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,including ripple.
This input ripple voltage can be approximated by Equation 2 :
Where I
OUT(MAX)
is the maximum load current, f
SW
is the switching frequency, C
IN
is the input capacitor value andESR
MAX
is the maximum series resistance of the input capacitor. For this design, the input capacitance consistsof two 4.7 μF capacitors, C1 and C4, in parallel. An additional high frequency bypass capacitor, C5 is also used.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can beapproximated by Equation 3 :
In this case the input ripple voltage would be 281 mV and the RMS ripple current would be 2.5 A. The maximumvoltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor israted for 50 V and the ripple current capacity is greater than 2.5 A each, providing ample margin. It is veryimportant that the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5450 circuit is not located within about2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated tohandle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltageis acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5450 is an internallycompensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4 :
K
IND
is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.Three things need to be considered when determining the amount of ripple current in the inductor: the peak topeak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch currentand the amount of ripple current determines at what point the circuit becomes discontinuous. For designs usingthe TPS5450, K
IND
of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when paired withthe proper output capacitor, the peak switch current will be well below the current limit set point and relatively lowload currents can be sourced before discontinuous operation.
For this design example use K
IND
= 0.2 and the minimum inductor value is calculated to be 10.4 μH. A higherstandard value is 15 μH, which is used in this design.
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IL(RMS) +I2
OUT(MAX))1
12 ǒVOUT ǒVIN(MAX) *VOUTǓ
VIN(MAX) LOUT FSW(MIN)Ǔ2
Ǹ
(5)
IL(PK) +IOUT(MAX))
VOUT ǒVIN(MAX) *VOUTǓ
1.6 VIN(MAX) LOUT FSW(MIN)
(6)
fCO +fLC2
85 VOUT
(7)
COUT +1
3357 LOUT fCO VOUT
(8)
ESRMAX +1
2p COUT fCO
(9)
V (MAX)=
PP
()
ESR xV xV -V
MAX OUT IN(MAX) OUT
N xV xL
C IN(MAX) OUT xFSW
(10)
TPS5450
SLVS757 – MARCH 2007
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.The RMS inductor current can be found from Equation 5 :
and the peak inductor current can be determined with Equation 6 :
For this design, the RMS inductor current is 5.004 A, and the peak inductor current is 5.34 A. The choseninductor is a Sumida CDRH1127/LD-150 15 μH. It has a minimum rated current of 5.65 A for both saturation andRMS current. In general, inductor values for use with the TPS5450 are in the range of 10 μH to 100 μH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalentseries resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is importantbecause along with the inductor ripple current it determines the amount of output ripple voltage. The actual valueof the output capacitor is not critical, but some practical limits do exist. Consider the relationship between thedesired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to thedesign of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this designexample, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHzand also below the ESR zero of the output capacitor. Under these conditions the closed loop crossoverfrequency is related to the LC corner frequency by:
And the desired output capacitor value for the output filter to:
For a desired crossover of 12 kHz and a 15- μH inductor, the calculated value for the output capacitor is 330 μF.The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESRshould be:
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initialdesign parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable outputripple voltage:
Where:
ΔV
PP
is the desired peak-to-peak output ripple.N
C
is the number of parallel output capacitors.F
SW
is the switching frequency.
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ICOUT(RMS) +1
12
Ǹ
ȧ
ȡ
Ȣ
VOUT ǒVIN(MAX) *VOUTǓ
VIN(MAX) LOUT FSW NCȧ
ȣ
Ȥ
(11)
R2 +R1 1.221
VOUT *1.221
(12)
ADVANCED INFORMATION
Output Voltage Limitations
VOUTMAX +0.87 ǒǒVINMIN *IOMAX 0.230Ǔ)VDǓ*ǒIOMAX RLǓ*VD
(13)
TPS5450
SLVS757 – MARCH 2007
For this design example, a single 330- μF output capacitor is chosen for C3. The calculated RMS ripple current is143 mA and the maximum ESR required is 40 m Ω. A capacitor that meets these requirements is a SanyoPoscap 10TPB330M, rated at 10 V with a maximum ESR of 35 m Ωand a ripple current rating of 3 A. Anadditional small 0.1- μF ceramic bypass capacitor, C6 is also used in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zerowhen the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus onehalf the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in theoutput capacitor is given by Equation 11 :
Where:
N
C
is the number of output capacitors in parallel.F
SW
is the switching frequency.
Other capacitor types can be used with the TPS5450, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5450 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.Calculate the R2 resistor value for the output voltage of 5 V using Equation 12 :
For any TPS5450 design, start with an R1 value of 10 k Ω. For an output voltage closest to but at least 5 V, R2 is3.16 k Ω.
Boot Capacitor
The boot capacitor should be 0.01 μF.
Catch Diode
The TPS5450 is designed to operate using an external catch diode between PH and GND. The selected diodemust meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximumvoltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half thepeak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to notethat the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diodeparameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen iscapable of dissipating the power losses. For this design, a Diodes, Inc. B540A is chosen, with a reverse voltageof 40 V, forward current of 5 A, and a forward voltage drop of 0.5 V.
Due to the internal design of the TPS5450, there are both upper and lower output voltage limits for any giveninput voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%and is given by:
14 Submit Documentation Feedback Copyright © 2007 – , Texas Instruments Incorporated
Product Folder Link(s): TPS5450
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VOUTMIN +0.12 ǒǒVINMAX *IOMIN 0.110Ǔ)VDǓ*ǒIOMIN RLǓ*VD
(14)
Internal Compensation Network
H(s) +ǒ1)s
2p Fz1Ǔ ǒ1)s
2p Fz2Ǔ
ǒs
2p Fp0Ǔ ǒ1)s
2p Fp1Ǔ ǒ1)s
2p Fp2Ǔ ǒ1)s
2p Fp3Ǔ
(15)
Thermal Calculations
TPS5450
SLVS757 – MARCH 2007
Where
V
INMIN
= minimum input voltageI
OMAX
= maximum load currentV
D
= catch diode forward voltage.R
L
= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. Theapproximate minimum output voltage for a given input voltage and minimum load current is given by:
Where
V
INMAX
= maximum input voltageI
OMIN
= minimum load currentV
D
= catch diode forward voltage.R
L
= output inductor series resistance.This equation assumes nominal on resistance for the high side FET and accounts for worst case variation ofoperating frequency set point. Any design operating near the operational limits of the device should becarefully checked to assure proper functionality.
The design equations given in the example circuit can be used to generate circuits using the TPS5450. Thesedesigns are based on certain assumptions and will tend to always select output capacitors within a limited rangeof ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation ofthe TPS5450. Equation 15 gives the nominal frequency response of the internal voltage-mode type IIIcompensation network:
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 HzFp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHzFp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,the closed loop transfer function can be derived.
The following formulas show how to estimate the device power dissipation under continuous conduction modeoperations. They should not be used if the device is working at light loads in the discontinuous conduction mode.Conduction Loss: Pcon = I
OUT
2
x R
DS(on)
x V
OUT
/V
INSwitching Loss: Psw = V
IN
x I
OUT
x 0.01Quiescent Current Loss: Pq = V
IN
x 0.01Total Loss: Ptot = Pcon + Psw + PqGiven T
A
=> Estimated Junction Temperature: T
J
= T
A
+ Rth x PtotGiven T
JMAX
= 125 °C => Estimated Maximum Ambient Temperature: T
AMAX
= T
JMAX
– Rth x Ptot
Copyright © 2007 – , Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS5450
www.ti.com
PERFORMANCE GRAPHS
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
I -OutputCurrent- A
O
OutputRegulation-%
75
80
85
90
95
100
0 1 2 3 4 5 6
I -OutputCurrent- A
O
Efficiency-%
V =12V
I
V =15V
I
V =24V
I
V =28V
I
V =200mV/Div(ACCoupled)
I
PH=10V/Div
t-Time-1 s/Divm
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
10 13 16 19 22 25 28 31
V -InputVoltage-V
I
OutputRegulation-%
I =2.5 A
O
I =5 A
O
I =0 A
O
TPS5450
SLVS757 – MARCH 2007
The performance graphs (Figure 12 through Figure 18 ) are applicable to the circuit in Figure 11 . Ta = 25 °C.unless otherwise specified.
Figure 12. Efficiency vs. Output Current Figure 13. Output Regulation % vs. Output Current
Figure 14. Output Regulation % vs. Input Voltage Figure 15. Input Voltage Ripple and PH Node, Io = 5 A.
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V =50mV/div(ACCoupled,20MHzBWL)
OUT
V =10V/div
PH
t-Time=1 s/divm
V =50mV/div(ACCoupled,20MHzBWL)
OUT
I =1 A/div
OUT
t-Time=100 s/divm
25
50
75
100
125
0 0.5 1 1.5 2 2.5 3 3.5
I PowerDissipation-W
C
T-JunctionTemperature-°C
J
TPS5450
SLVS757 – MARCH 2007
Figure 16. Output Voltage Ripple and PH Node, Io = 5 A Figure 17. Transient Response, Io Step 1.25 to 3.75 A.
Figure 18. TPS5450 Power Dissipation vs JunctionTemperature.
Copyright © 2007 – , Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS5450
PACKAGE OPTION ADDENDUM
www.ti.com 22-Feb-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS5450DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5450DDAG4 ACTIVE SO PowerPAD DDA 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5450DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS5450DDARG4 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS5450 :
PACKAGE OPTION ADDENDUM
www.ti.com 22-Feb-2012
Addendum-Page 2
•Automotive: TPS5450-Q1
•Enhanced Product: TPS5450-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS5450DDAR SO
Power
PAD
DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5450DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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