1
FEATURES DESCRIPTION
APPLICATIONS
OUT
EN
IN
GND
VSET
C3
B2
A3
C1
A1
IN
GND
Thermal
Pad(1)
EN
6
5
4
OUT
VSET
NC
1
2
3
TPS728xxSeries
DRVPACKAGE
2mmx2mmSON-6
(TOPVIEW)
TPS728xxSeries
YZUPACKAGE
WCSP-5
(TOPVIEW)
TPS728xx Series
SBVS095 – AUGUST 2007www.ti.com
200mA Low-Dropout Linear Regulatorwith Pin-Selectable Dual-Voltage Level Output
2
•Very Low Dropout: 230mV Typical at 200mA
The TPS728xx series of low-dropout linear regulators(LDOs), with a selectable dual-voltage level output, is•3% Accuracy Over Load/Line/Temperature
designed specially for applications that require two•Low I
Q
: 50 μA in Active Mode
levels of output voltage regulation. Programming•Available in Fixed-Output Voltages From 0.9V
fuses and memory cards, reducing leakage effects,to 3.6V Using Innovative Factory EEPROM
and conserving power in nanometric processes areProgramming
some application examples.•VSET Pin Toggles Output Voltage Between
The VSET pin is used to select one of two outputTwo Preset Levels
voltage levels preset through innovative factoryEEPROM programming. A precision bandgap and– Preset Output Voltage Levels Can Be
error amplifier provides an overall 3% accuracy overEEPROM-Programmed To Any Combination
load, line, and temperature extremes.•High PSRR: 65dB at 1kHz
Ultra-small wafer chip scale (WCSP) and 2mm x•Stable with a 1.0 μF Ceramic Capacitor
2mm SON packages make the TPS728xx series ideal•Thermal Shutdown and Over-Current
for handheld applications.Protection
This family of devices is fully specified over a•Available in Wafer-Level Chip Scale and
temperature range of T
J
= – 40 °C to +125 °C.2mm x 2mm SON Packages
•Power Rails with Programming Mode•Dual Voltage Levels for Power-Saving Mode•Leakage Reduction for 90nm and 65nmProcessors
•Wireless Handsets, Smart Phones, PDAs•MP3 Players and Other Handheld Products
(1) It is recommended that the SON packagethermal pad be connected to ground.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS728xx Series
SBVS095 – AUGUST 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS728 vvvxxxyyyz VVV is the nominal output voltage for V
OUT1
and corresponds to V
SET
= Low.XXX is the nominal output voltage for V
OUT2
and corresponds to V
SET
= High.YYY is package designator.Zis Tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;minimum order quantities may apply. Contact factory for details and availability.
At T
J
= – 40 °C to +125 °C (unless otherwise noted). All voltages are with respect to GND.
PARAMETER TPS728xx Series UNIT
Input voltage range, V
IN
– 0.3 to +7.0 VEnable and VSET voltage range, V
EN
and V
SET
– 0.3 to V
IN
+ 0.3
(2)
VOutput voltage range, V
OUT
– 0.3 to +7.0 VMaximum output current, I
OUT
Internally limitedOutput short-circuit duration IndefiniteTotal continuous power dissipation, P
DISS
See Dissipation Ratings TableHuman body model (HBM) 2 kVESD rating
Charged device model (CDM) 500 VOperating junction temperature range, T
J
– 55 to +150 °CStorage temperature range, T
STG
– 55 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.(2) V
EN
and V
SET
absolute maximum rating is V
IN
+ 0.3V or +7.0V, whichever is less.
DERATING FACTORBOARD PACKAGE R
θJC
R
θJA
ABOVE T
A
= +25 °C T
A
< +25 °C T
A
= +70 °C T
A
= +85 °C
High-K
(1)
DRV 20 °C/W 65 °C/W 15.4mW/ °C 1540mW 845mW 615mWHigh-K
(1)
YZU 85 °C/W 268 °C/W 3.7mW/ °C 370mW 205mW 150mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3- ×3-inch, multilayer board with 1-ounce internal power and groundplanes and 2-ounce copper traces on top and bottom of the board.
2Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
TPS728xx Series
SBVS095 – AUGUST 2007
Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
SET
= V
EN
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range 2.7 6.5 VNominal T
J
= +25 °C, V
SET
= high/low – 2.5 +2.5 mVV
OUT
(1)
DC output accuracy
Over V
IN
, I
OUT
, V
OUT
+ 0.5V ≤V
IN
≤6.5V,
– 3.0 +3.0 %temperature 0mA ≤I
OUT
≤200mA, V
SET
= high/low100 μA to 200mA in 1 μs,ΔV
OUT
Load transient ± 60.0 mV200mA to 100 μA in 1 μs, C
OUT
= 1 μFV
O
Output voltage range 0.9 3.6 VV
OUT(NOM)
+ 0.5V ≤V
IN
≤6.5V,ΔV
O
/ΔV
IN
Line regulation 130 μV/VI
OUT
= 5mA
ΔV
O
/ΔI
OUT
Load regulation 0mA ≤I
OUT
≤200mA 75 μV/mAV
DO
Dropout voltage
(2)
V
IN
= V
OUT(NOM)
– 0.1V, I
OUT
= 200mA 230 400 mVI
CL
Output current limit V
OUT
= 0.9 ×V
OUT(NOM)
240 340 575 mAI
OUT
= 0mA 50 80 μAI
GND
Ground pin current
I
OUT
= 200mA 120 μAV
EN
≤0.4V, 2.7V ≤V
IN
< 4.5V,I
SHDN
Shutdown current (I
GND
) 0.10 1.0 μAT
J
= – 40 °C to +85 °C
f = 100Hz 65 dBV
IN
= 3.8V,
f = 1kHz 65 dBPSRR Power-supply rejection ratio V
OUT
= 2.8V,
f = 10kHz 55 dBI
OUT
= 200mA
f = 100kHz 40 dBBW = 100Hz to 100kHz, V
IN
= 3.3V,V
N
Output noise voltage 75 ×V
OUT
μV
RMSV
OUT
= 2.8V, I
OUT
= 10mATransition time (low-to-high)
V
OUT_LOW
= 1.8V, V
OUT_HIGH
= 3.15V,t
TR
V
OUT
= V
OUT_LOW
to V
OUT_HIGH
60 μsI
OUT
= 10mAV
OUT
= 97% ×V
OUT_HIGH
t
STR
Startup time
(3)
C
OUT
= 1.0 μF 160 μst
SHUT
Shutdown time
(4)
R
L
=∞, C
OUT
= 1.0 μF, V
OUT
= 2.8V 180
(5)
μsVSET high (output V
OUT2
selected),V
HI
1.2 V
IN
Vor enable pin high (enabled)VSET low (output V
OUT1
selected),V
LO
0 0.4 Vor enable pin low (disabled)I
EN
, I
VSET
Enable and select pin currents EN = VSET = 6.5V 0.04 1.0 μAUndervoltage lockout V
IN
rising, V
SET
= high/low 2.38 2.51 2.65 VUVLO
Hysteresis V
IN
falling, V
SET
= high/low 230 mVShutdown, temperature increasing +160 °CT
SD
Thermal shutdown temperature
Reset, temperature decreasing +140 °CT
J
Operating junction temperature – 40 +125 °C
(1) The output voltage for V
SET
= low/high is programmed at the factory.(2) V
DO
is not measured for devices with V
OUT(NOM)
< 2.8V because minimum V
IN
= 2.7V.(3) Time from V
EN
= 1.2V to V
OUT
= 97% (V
OUT(NOM)
).(4) Time from V
EN
= 0.4V to V
OUT
= 5% (V
OUT(NOM)
).(5) See Shutdown in the Application Information section for more details.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
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DEVICE INFORMATION
Thermal
Shutdown
60W
Current
Limit
UVLO
Bandgap
IN
EN
OUT
EEPROM
MUX
VSET
LOGIC
Active
Pull-
Down
TPS728xx Series
SBVS095 – AUGUST 2007
Figure 1. Functional Block Diagram
4Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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OUT
EN
IN
GND
VSET
C3
B2
A3
C1
A1
IN
GND
EN
6
5
4
OUT
VSET
NC
1
2
3
Thermal
Pad(1)
TPS728xx Series
SBVS095 – AUGUST 2007
YZU PACKAGE
WCSP-5
(TOP VIEW)
DRV PACKAGE
SON-8
(TOP VIEW)
(1) It is recommended that the SON package thermal pad be connected to ground.
PIN DESCRIPTIONS
TPS728xx Series
NAME DRV YZU DESCRIPTION
Regulated output voltage pin. A small 1 μF ceramic capacitor is needed from this pin to ground to assureOUT 1 C1 stability. See Input and Output Capacitor Requirements in the Application Information section for moredetails.
Select pin. Driving VSET below 0.4V selects preset output voltage V
OUT1
. Driving VSET over 1.2V selectsVSET 2 A3
preset output voltage V
OUT2
.NC 3 — No connection.
Enable pin. Driving EN over 1.2V turns on the regulator. Driving EN below 0.4V puts the regulator intoEN 4 A1
shutdown mode, thus reducing the operating current to 100nA, nominal.GND 5 B2 Ground pin (connect DRV thermal pad to ground)Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and OutputIN 6 C3
Capacitor Requirements in the Application Information section for more details.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
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TYPICAL CHARACTERISTICS
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DV (mV)
OUT
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25 C°
J
T =+85 C
J°
T =+125 C°
J
10
8
6
4
2
0
-2
-4
-6
-8
-10
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DVOUT (mV)
5.0 5.5 6.0 6.5
T = 40- °
JC
TJ=+25 C°
T =+85 C
J°
TJ=+125 C°
6
3
0
-3
-6
-9
-12
-15
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DVOUT(mV)
5.0 5.5 6.0 6.5
T = 40-
J°C
T =+25 C°
J
T =+85 C°
J
T =+125 C°
J
6
3
0
-3
-6
-9
-2
-15
-18
-21
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DVOUT (mV)
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25 C
J°
T =+85 C
J°
T =+125 C
J°
5
0
-5
-10
-15
-20
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DVOUT (mV)
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25 C
J°
T =+85 C
J°
T =+125 C
J°
10
5
0
-5
-10
-15
-20
-25
-30
2.5 3.0 3.5 4.0 4.5
V (V)
IN
DVOUT (mV)
5.0 5.5 6.0 6.5
T°
J= 40-C
T =+25 C
J°
T =+85 C
J°
T =+125 C
J°
TPS728xx Series
SBVS095 – AUGUST 2007
Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
LINE REGULATION LINE REGULATIONI
OUT
= 5mA, V
OUT
= 0.9V (nom) I
OUT
= 200mA, V
OUT
= 0.9V (nom)
Figure 2. Figure 3.
LINE REGULATION LINE REGULATIONI
OUT
= 5mA, V
OUT
= 1.85V (nom) I
OUT
= 200mA, V
OUT
= 1.85V (nom)
Figure 4. Figure 5.
LINE REGULATION LINE REGULATIONI
OUT
= 5mA, V
OUT
= 3.6V (nom) I
OUT
= 200mA, V
OUT
= 3.6V (nom)
Figure 6. Figure 7.
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15
10
5
0
-5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I (mA)
OUT
DVOUT (mV)
T = - °
J40 C
TJ=+25°C
TJ=+85°C
TJ=+125°C
10
5
0
-5
-10
-15
-20
-25
0 20 40 60 80 100 120 140 160 180 200
I (mA)
OUT
DVOUT (mV)
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TJ=+125°C
8
6
4
2
0
-2
-4
-6
-8
-10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I (mA)
OUT
DVOUT (mV)
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TJ=+125°C
10
5
0
-5
-10
-15
-20
-25
-30
-35
0 20 40 60 80 100 120 140 160 180 200
I (mA)
OUT
DVOUT (mV)
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TJ=+125°C
25
20
15
10
5
0
-5
-10
-15
-20
-25
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I (mA)
OUT
DVOUT (mV)
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TJ=+125°C
25
20
15
10
5
0
-5
-10
-15
-20
-25
0 20 40 60 80 100 120 140 160 180 200
I (mA)
OUT
DVOUT (mV)
T = 40- °
JC
TJ=+25°C
TJ=+85°C
TJ=+125°C
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
LOAD REGULATION UNDER LIGHT LOADS LOAD REGULATIONV
OUT
= 0.9V (nom) V
OUT
= 0.9V (nom)
Figure 8. Figure 9.
LOAD REGULATION UNDER LIGHT LOADS LOAD REGULATIONV
OUT
= 1.85V (nom) V
OUT
= 1.85V (nom)
Figure 10. Figure 11.
LOAD REGULATION UNDER LIGHT LOADS LOAD REGULATIONV
OUT
= 3.6V (nom) V
OUT
= 3.6V (nom)
Figure 12. Figure 13.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
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3
2
1
0
-1
-2
-3
-40 -25 -10 5 20 35 50 65 80 95 110 125
T ( C)°
J
DV (%)
OUT
I =0.1mA
OUT
I =5mA
OUT
I =200mA
OUT
V =0.9V
OUT
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ(°C)
DV(%)
OUT
I =0.1mA
OUT
I =5mA
OUT
I =200mA
OUT
V =3.6V
OUT
50
45
40
35
30
25
I ( A)
GNDm
T = 40- °
JC
T =+25 C
J°
T =+85 C
J°
T =+125 C
J°
2.5 3.0 3.5 4.0 4.5
V (V)
IN
5.0 5.5 6.0 6.5
I =0mA
OUT
150
130
110
90
70
50
30
0 20 40 60 80 100 120 140 160 180 200
I (mA)
OUT
I (m
GND A)
T = 40-
J°C
T =+25°
JC
T =+85°
JC
T =+125°
JC
60
55
50
45
40
35
30
-40 -25 -10 5 20 35 50 65 80 95 110 125
T ( C)
J°
I ( A)
GND m
I =0mA
OUT
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
DROPOUT VOLTAGE OUTPUT VOLTAGEvs OUTPUT CURRENT vs TEMPERATURE
Figure 14. Figure 15.
OUTPUT VOLTAGE GROUND PIN CURRENTvs TEMPERATURE vs INPUT VOLTAGE
Figure 16. Figure 17.
GROUND PIN CURRENT GROUND PIN CURRENTvs OUTPUT CURRENT vs TEMPERATURE
Figure 18. Figure 19.
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1600
1400
1200
1000
800
600
400
200
0
2.5 3.0 3.5 4.0 4.5
V (V)
IN
I (nA)
SHDN
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25 C°
J
T =+85 C°
J
T =+125 C°
J
I =0mA
OUT
350
340
330
320
310
300
290
280
270
2.5 3.0 3.5 4.0 4.5
V (V)
IN
CurrentLimit(mA)
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25°
JC
T =+85°
JC
T =+125°
JC
V =0.9V(nom)
OUT
350
340
330
320
310
300
290
280
270
2.5 3.0 3.5 4.0 4.5
V (V)
IN
CurrentLimit(mA)
5.0 5.5 6.0 6.5
T = 40- °
JC
T =+25°
JC
T =+85°
JC
T =+125°
JC
V =3.6V(nom)
OUT
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Frequency(Hz)
PSRR(dB)
10M
200mA 100mA
5mA V =2.7V
IN
V =1.85V
C =1 F
OUT
OUT m
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Frequency(Hz)
PSRR(dB)
10M
200mA 100mA
5mA V =2.85V
IN
V =1.85V
C =1 F
OUT
OUT m
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Frequency(Hz)
PSRR(dB)
10M
200mA 100mA
5mA
V =3.65V
IN
V =3.15V
C =1 F
OUT
OUT m
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
SHUTDOWN CURRENT CURRENT LIMITvs INPUT VOLTAGE vs INPUT VOLTAGE
Figure 20. Figure 21.
CURRENT LIMIT TPS728185315 POWER-SUPPLY RIPPLE REJECTIONvs INPUT VOLTAGE vs FREQUENCY (V
IN
– V
OUT
= 0.85V)
Figure 22. Figure 23.
TPS728185315 POWER-SUPPLY RIPPLE REJECTION TPS728185315 POWER-SUPPLY RIPPLE REJECTIONvs FREQUENCY (V
IN
– V
OUT
= 1.0V) vs FREQUENCY (V
IN
– V
OUT
= 0.5V)
Figure 24. Figure 25.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
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90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Frequency(Hz)
PSRR(dB)
10M
200mA
5mA
100mA
V =4.15V
IN
V =3.15V
C =1 F
OUT
OUT m
10
1
0.1
0.01
10 100 1k 10k
Frequency(Hz)
OutputspectalNoiseDensity(mV/Ö)
Hz
100k
LoadI =185mA
OUT
C =C =1m
IN OUT F
V =1.85V
OUT
Noise=141.6 VmRMS
Time(100 s )m/div
10mV/div
V =2.7Vto6.5V,SlewRate=1V/ s
V =1.85V,I =200mA
m
IN
OUT OUT VOUT
VIN
10
1
0.1
0.01
10 100 1k 10k
Frequency(Hz)
OutputspectalNoiseDensity(mV/Ö)
Hz
100k
LoadI =200mA
OUT
C =C =1m
IN OUT F
V =3.15V
OUT
Noise=217 VmRMS
Time(100 s )m/div
V =3.8Vto6.5V,SlewRate=1V/ s
V =3.3V,I =200mA
m
IN
OUT OUT
10mV/div
VOUT
VIN
Time(10 s )m/div
V =2.7V
V =1.85V
I =5mAto200mA
t =t =1 s
IN
OUT
OUT
R F m
5mA
200mA
10mV/div
VOUT
IOUT
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS728185315 POWER-SUPPLY RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITYvs FREQUENCY (V
IN
– V
OUT
= 1.0V) vs FREQUENCY
Figure 26. Figure 27.
OUTPUT SPECTRAL NOISE DENSITYvs FREQUENCY LINE TRANSIENT RESPONSE
Figure 28. Figure 29.
LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 30. Figure 31.
10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
www.ti.com
Time(10 s )m/div
V =3.8V
V =3.3V
I =5mAto200mA
t =t =1 s
IN
OUT
OUT
R F m
5mA
200mA
10mV/div
VOUT
IOUT
Time(100 s )m/div
V =3.8V,V =3.3V,I =0mA
Enable=0.4Vto1Vto0.4V
IN OUT OUT
200mV/div
500mV/div
EN
VOUT
Time(2ms )/div
1V/div
VIN
VOUT
Time(10 s )m/div
V TransitionTime<40 s(2%settling)m
OUT
VOUT
VSET
V Transitioningfrom1.85Vto3.15V
I =1mA
OUT
OUT
200mV/div
Time(100 s )m/div
V Transitioningfrom3.15Vto1.85V
I =1mA
OUT
OUT
VOUT
VSET
200mV/div
Time(40 s )m/div
V Transitioningfrom1.85Vto3.15V
I =10mA
OUT
OUT
VOUT
VSET
V TransitionTime<40 s(2%settling)m
OUT
200mV/div
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
LOAD TRANSIENT RESPONSE ENABLE TRANSIENT RESPONSE
Figure 32. Figure 33.
V
IN
RAMP UP AND RAMP DOWN RESPONSE VSET PIN TOGGLE
Figure 34. Figure 35.
VSET PIN TOGGLE VSET PIN TOGGLE
Figure 36. Figure 37.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
www.ti.com
Time(20 s/div)m
V Transitioningfrom3.15Vto1.85V
I =10mA
OUT
OUT
VOUT
VSET
200mV/div
TPS728xx Series
SBVS095 – AUGUST 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater;I
OUT
= 0.5mA, V
EN
= V
SET
= V
IN
, C
OUT
= 1.0 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
VSET PIN TOGGLE
Figure 38.
12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
www.ti.com
APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITOR
TPS728xx
GND
EN
VSET
IN OUT
VIN VOUT
1 Fm
1 Fm
2.7Vto6.5V 0.9Vto3.6V
On
Off
On(V )
OUT2
Off(V )
OUT1
APPLICATION EXAMPLES
BOARD LAYOUT RECOMMENDATIONS TO
TPS728xx Series
SBVS095 – AUGUST 2007
Another area where the TPS728xx can be usedThe TPS728xx series belongs to a family of new
effectively is in dynamic voltage scaling (DVS)generation LDO regulators that use innovative
applications. In DVS applications, it is required tocircuitry to achieve ultra-wide bandwidth and high
dynamically switch between a high operationalloop gain, resulting in extremely high PSRR (up to
voltage to a low standby voltage in order to balance1MHz) at very low headroom (V
IN
– V
OUT
). These
performance of processors and achieve powerfeatures, combined with low noise, low ground pin
savings. Modern multimillion gate microprocessorscurrent, and ultra-small packaging, make this device
fabricated with the latest sub-micron processes saveideal for portable applications. This family of
on power by transitioning to a lower voltage to reduceregulators offers sub-bandgap output voltages,
leakage currents without losing content. Thiscurrent limit and thermal protection, and is fully
architecture enables the microprocessor to transitionspecified from – 40 °C to +125 °C.
quickly into an operational state (wake up) withoutrequiring reloading of the states from externalFigure 39 shows the basic circuit connections.
memory, or a reboot.
REQUIREMENTS
Although an input capacitor is not required forstability, it is good analog design practice to connecta 0.1 μF to 1.0 μF low equivalent series resistance(ESR) capacitor across the input supply near theregulator. This capacitor counteracts reactive inputsources and improves transient response, noiserejection, and ripple rejection. A higher-valuecapacitor may be necessary if large, fast rise-timeload transients are anticipated, or if the device is notlocated near the power source. If source impedanceFigure 39. Typical Application Circuit
is not sufficiently low, a 0.1 μF input capacitor may benecessary to ensure stability.
The TPS728xx is designed to be stable with standardEEPROM-based applications require the
ceramic capacitors with values of 1.0 μF or larger atprogramming voltage to be higher than the operating
the output. X5R- and X7R-type capacitors are bestvoltage. The TPS728xx suits such applications where
because they have minimal variation in value andthe maximum programming voltage of the EEPROM
ESR over temperature. Maximum ESR should be lessis higher than the operating voltage. The VSET logic
than 1.0 Ω.pin allows the application to transition between thehigher EEPROM programming voltage and the loweroperating voltage. For example, the TPS728xx
IMPROVE PSRR AND NOISE PERFORMANCEtypically takes less than 40 μs to transition from alower voltage of 1.85V to a higher voltage of 3.15V
To improve ac performance such as PSRR, outputunder an output load of 1mA to 10mA, as shown in
noise, and transient response, it is recommended thatFigure 35 and Figure 37 , respectively. The special
the board be designed with separate ground planescircuitry in the TPS728xx helps transition from the
for V
IN
and V
OUT
, with each ground plane connectedhigher voltage to the lower voltage under no load.
only at the GND pin of the device. In addition, theThe load on the output at the end of the programming
ground connection for the output capacitor shouldcycle is typically under 10mA. Output voltage
connect directly to the GND pin of the device. Highovershoots and undershoots are minimal under this
ESR capacitors may degrade PSRR.load condition. The TPS728xx typically takes lessthan 1ms of transition time going from 3.15V to1.85V, as shown in Figure 36 and Figure 38 ,respectively. Both output states of the TPS728xx areprogrammable between 0.9V to 3.6V.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
www.ti.com
INTERNAL CURRENT LIMIT
TPS728xx
GND
EN
VSET
IN OUT
VIN VOUT
1 Fm
1 Fm
2.7Vto6.5V 0.9Vto3.6V
VSET2
VSET1
2kW
SHUTDOWN
t=3
60 RL
´
60+RL
COUT
´
TPS728xx
GND
EN
VSET
IN OUT
VIN VOUT
1 Fm
1 Fm
2.7Vto6.5V 0.9Vto3.6V
2kW
DROPOUT VOLTAGE UNDERVOLTAGE LOCK-OUT (UVLO)
MINIMUM LOADTRANSIENT RESPONSE
TPS728xx Series
SBVS095 – AUGUST 2007
The TPS728xx internal current limits help protect theregulator during fault conditions. During current limit,the output sources a fixed amount of current that islargely independent of output voltage. For reliableoperation, the device should not be operated in acurrent limit state for extended periods of time.
The PMOS pass element in the TPS728xx has abuilt-in body diode that conducts current when thevoltage at OUT exceeds the voltage at IN. Thiscurrent is not limited, so if extended reverse voltageoperation is anticipated, external limiting to 5% ofrated output current may be appropriate.
Figure 40. Circuit Showing EN Tied High whenShutdown Capability is Not Required
The enable pin (EN) is active high and is compatiblewith standard and low voltage, TTL-CMOS levels.When shutdown capability is not required, EN can beconnected to the IN pin, as shown in Figure 40 .Figure 41 shows when both EN and VSET are tied toIN. The TPS728xx, with internal active outputpulldown circuitry, discharges the output to within 5%of V
OUT
with a time ( t) of:
Where:
Figure 41. Circuit to Tie Both EN and VSET HighR
L
= output load resistanceC
OUT
= output capacitance
The TPS728xx uses a PMOS pass transistor to The TPS728xx uses an undervoltage lock-out circuitachieve low dropout. When (V
IN
– V
OUT
) is less than to keep the output shut off until the internal circuitry isthe dropout voltage (V
DO
), the PMOS pass device is operating properly. The UVLO circuit has a deglitchin the linear region of operation and the feature so that it typically ignores undershootinput-to-output resistance is the R
DS(ON)
of the PMOS transients on the input if they are less than 5 μspass element. V
DO
approximately scales with output duration. The UVLO circuit triggers at approximatelycurrent because the PMOS device behaves like a 2.3V on an undershooting or a falling input voltage.resistor in dropout. On the TPS728xx, the active pulldown dischargesV
OUT
when the device is in UVLO off condition.As with any linear regulator, PSRR and transient
However, the input voltage must be greater than 0.8Vresponse are degraded as (V
IN
– V
OUT
) approaches
for the active pulldown to work.dropout. This effect is shown in Figure 25 andFigure 26 in the Typical Characteristics section.
The TPS728xx is stable with no output load.Traditional PMOS LDO regulators suffer from lowerAs with any regulator, increasing the size of the
loop gain at very light output loads. The TPS728xxoutput capacitor reduces over/undershoot magnitude
employs an innovative, low-current mode circuitbut increases duration of the transient response.
under very light or no-load conditions, resulting inimproved output voltage regulation performancedown to zero output current.
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
www.ti.com
THERMAL INFORMATION
Thermal Protection
Power Dissipation
P =(V V ) I- ´
D IN OUT OUT
(1)
Package Mounting
N TES:O
1,395
1,345
1.All lineardimen eters.sionsareinmillim
2.This drawingissub outnotice.jecttochangewith
1,025
0,975
TPS728xx Series
SBVS095 – AUGUST 2007
It was not intended to replace proper heatsinking.Continuously running the TPS728xx into thermalshutdown degrades device reliability.
Thermal protection disables the output when thejunction temperature rises to approximately +160 °C,allowing the device to cool. When the junction The ability to remove heat from the die is different fortemperature cools to approximately +140 °C the each package type, presenting differentoutput circuitry is again enabled. Depending on power considerations in the printed circuit board (PCB)dissipation, thermal resistance, and ambient layout. The PCB area around the device that is freetemperature, the thermal protection circuit may cycle of other components moves the heat from the deviceon and off. This cycling limits the dissipation of the to the ambient air. Performance data for JEDEC low-regulator, protecting it from damage as a result of and high-K boards are given in the Dissipationoverheating. Ratings table. Using heavier copper increases theeffectiveness in removing heat from the device. TheAny tendency to activate the thermal protection circuit
addition of plated through-holes to heat-dissipatingindicates excessive power dissipation or an
layers also improves the heatsink effectiveness.inadequate heatsink. For reliable operation, junctiontemperature should be limited to +125 °C maximum. Power dissipation depends on input voltage and loadTo estimate the margin of safety in a complete design conditions. Power dissipation (P
D
) is equal to the(including heatsink), increase the ambient product of the output current times the voltage droptemperature until the thermal protection is triggered; across the output pass element (V
IN
to V
OUT
), asuse worst-case loads and signal conditions. For good shown in Equation 1 :reliability, thermal protection should trigger at least+35 °C above the maximum expected ambientcondition of your particular application. Thisconfiguration produces a worst-case junctiontemperature of +125 °C at the highest expected
Solder pad footprint recommendations for theambient temperature and worst-case load.
TPS728xx are available from the Texas Instrumentsweb site at www.ti.com .The internal protection circuitry of the TPS728xx hasbeen designed to protect against overload conditions.
Figure 42. YZU Wafer Chip-Scale Package Dimensions (in mm)
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
PACKAGE OPTION ADDENDUM
www.ti.com 15-May-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS728120150DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAO
TPS728120150DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAO
TPS728175295YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 AU
TPS728175295YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 AU
TPS728180285YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DT
TPS728180285YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DT
TPS728180300YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VL
TPS728180300YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VL
TPS728185295YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VM
TPS728185295YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 VM
TPS728185315DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 BYW
TPS728185315YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FN
TPS728185315YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FN
TPS728285180YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 TL
TPS728285180YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 TL
TPS728330180YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DJ
TPS728330180YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 DJ
PACKAGE OPTION ADDENDUM
www.ti.com 15-May-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS728330185DRVR ACTIVE WSON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBD
TPS728330185DRVT ACTIVE WSON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS728120150DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS728120150DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS728175295YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728175295YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728180285YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728180285YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728180300YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728180300YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728185295YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728185295YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728185315DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS728185315YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728185315YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728285180YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728285180YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728330180YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728330180YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1
TPS728330185DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 22-May-2018
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS728330185DRVT WSON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS728120150DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS728120150DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS728175295YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
TPS728175295YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728180285YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
TPS728180285YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728180300YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
TPS728180300YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728185295YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
TPS728185295YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728185315DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS728185315YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
TPS728185315YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728285180YZUR DSBGA YZU 5 3000 210.0 185.0 35.0
TPS728285180YZUT DSBGA YZU 5 250 210.0 185.0 35.0
TPS728330180YZUR DSBGA YZU 5 3000 182.0 182.0 20.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-May-2018
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS728330180YZUT DSBGA YZU 5 250 182.0 182.0 20.0
TPS728330185DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS728330185DRVT WSON DRV 6 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-May-2018
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
0.625 MAX
0.3
0.2
0.5 TYP
5X 0.35
0.25
0.5 TYP
0.433
B E A
D
4222196/A 11/2015
DSBGA - 0.625 mm max heightYZU0005
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3
SYMM
SYMM
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
C
B
A
12
0.015 C A B
SCALE 10.000
D: Max =
E: Max =
1.358 mm, Min =
0.99 mm, Min =
1.297 mm
0.93 mm
www.ti.com
EXAMPLE BOARD LAYOUT
5X ( )0.25
(0.5) TYP
(0.433) TYP
( )
METAL
0.25 0.05 MAX
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
( )
SOLDER MASK
OPENING
0.25
0.05 MIN
4222196/A 11/2015
DSBGA - 0.625 mm max heightYZU0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
SOLDER MASK DETAILS
NOT TO SCALE
13
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
C
2
A
B
NON-SOLDER MASK
DEFINED
(PREFERRED) SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(0.433) TYP
(0.5) TYP
5X ( 0.25) (R ) TYP0.05
METAL
TYP
4222196/A 11/2015
DSBGA - 0.625 mm max heightYZU0005
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
C
12
A
B
3
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4206925/F
www.ti.com
PACKAGE OUTLINE
C
6X 0.35
0.25
1.6 0.1
6X 0.3
0.2
2X
1.3
1 0.1
4X 0.65
0.8
0.7
0.05
0.00
B2.1
1.9 A
2.1
1.9
(0.2) TYP
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
7
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1)
4X (0.65)
(1.95)
6X (0.3)
6X (0.45)
(1.6)
(R0.05) TYP
( 0.2) VIA
TYP
(1.1)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
7
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.3)
6X (0.45)
4X (0.65) (0.7)
(1)
(1.95)
(R0.05) TYP
(0.45)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
SYMM
1
34
6
SYMM
METAL
7
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