Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Quick Start Procedure
DESCRIPTION
The EPC9006 development board is a 100 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) eld
eect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge conguration using
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
2. With power o, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
THERMAL CONSIDERATIONS
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi-
ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Logic and
Dead-time
Adjust
LM5113
Gate
Driver
Gate Drive
Supply Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
< 70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
6, 100
EPC
EFFICIENT POWER CONVERSION
6, 100
Do not use probe ground lead
Do not let probe tip touch
back of low-side die!
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to fa-
cilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1 Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range 70* V
VOUT Switch Node Output Voltage 100 V
IOUT Switch Node Output Current 5* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 30 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100#ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block Diagram of EPC9006 Development Board
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Quick Start Procedure
DESCRIPTION
The EPC9006 development board is a 100 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) eld
eect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge conguration using
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
2. With power o, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
THERMAL CONSIDERATIONS
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi-
ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Logic and
Dead-time
Adjust
LM5113
Gate
Driver
Gate Drive
Supply Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
< 70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
6, 100
EPC
EFFICIENT POWER CONVERSION
6, 100
Do not use probe ground lead
Do not let probe tip touch
back of low-side die!
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to fa-
cilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1 Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range 70* V
VOUT Switch Node Output Voltage 100 V
IOUT Switch Node Output Current 5* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 30 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100#ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block Diagram of EPC9006 Development Board
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Quick Start Procedure
DESCRIPTION
The EPC9006 development board is a 100 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) eld
eect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge conguration using
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
2. With power o, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
THERMAL CONSIDERATIONS
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi-
ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Logic and
Dead-time
Adjust
LM5113
Gate
Driver
Gate Drive
Supply Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
< 70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
6, 100
EPC
EFFICIENT POWER CONVERSION
6, 100
Do not use probe ground lead
Do not let probe tip touch
back of low-side die!
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to fa-
cilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1 Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range 70* V
VOUT Switch Node Output Voltage 100 V
IOUT Switch Node Output Current 5* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 30 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100#ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block Diagram of EPC9006 Development Board
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Quick Start Procedure
DESCRIPTION
The EPC9006 development board is a 100 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) eld
eect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge conguration using
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
2. With power o, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
THERMAL CONSIDERATIONS
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi-
ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Logic and
Dead-time
Adjust
LM5113
Gate
Driver
Gate Drive
Supply Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
< 70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
6, 100
EPC
EFFICIENT POWER CONVERSION
6, 100
Do not use probe ground lead
Do not let probe tip touch
back of low-side die!
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to fa-
cilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1 Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range 70* V
VOUT Switch Node Output Voltage 100 V
IOUT Switch Node Output Current 5* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 30 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100#ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block Diagram of EPC9006 Development Board
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
100 V Half-Bridge with Gate Drive, using EPC2007
Rev. 2.0
SW OUT
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X
R12
1 Ohm
70V Max
GND
1
TP3
CON1
C16
4.7uF,
50V
R11 1 Ohm
C12
0.1uF,
25V
C13
1uF, 25V
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
TP1
Keystone 5015
C15
Opt.
R13
Opt.
C17
4.7uF, 50V
R2
Zero
R14
Optional
R15
Zero
VDD
HB
HOH
HOL
HI
LI
VSS
LOL
GND
HS
LOH
U2
LM5113
R5
33
C7
100p
D2
SDM03U40
R4
22
C6
100p
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3
MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
D6
Opt.
C19
Optional
D5
Opt.
GND
A
B
Y
VDD
U4
NC7SZ08L6X
EPC2007
Q1
EPC2007
Q2
1
Table 2 : Bill of Material
Item Qty Reference Part Description Manufacturer / Part #
1 4 C4, C10, C11, C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 TDK, C1608C0G1H101J
3 1 C12 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1608X5R1E104K
4 2 C16, C17 Capacitor, 2.2uF, 10%, 100V, X5R Taiyo Yuden, HMK325B7225K
5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
6 4 J1, J2, J9, TP3 (See Note 1) Connector FCI, 68001-236HLF
7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
8 2 Q1, Q2 eGaN® FET EPC, EPC2007
9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
10 2 R2, R15 Resistor, 0 Ohm, 1/10W Panasonic, ERJ-3GEY0R00V
11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0
12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0
13 2 R11, R12 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
14 2 TP1, TP2 Test Point Keystone Elect, 5015
15 1 TP3 Connector 1 pin of Tyco, 4-103185-0
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 R13, R14 Optional Resistor
21 0 C15, C19 Optional Capacitor
22 0 D5, D6 Optional Diode
23 0 P1, P2 Optional Potentiometer
Note 1: 36 pin Header to be cut as follows:
J1: cut 2 pins used
J2 & J9: cut 4 pins used
TP3: cut 1 pin used
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
100 V Half-Bridge with Gate Drive, using EPC2007
Rev. 2.0
SW OUT
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X
R12
1 Ohm
70V Max
GND
1
TP3
CON1
C16
4.7uF,
50V
R11 1 Ohm
C12
0.1uF,
25V
C13
1uF, 25V
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
TP1
Keystone 5015
C15
Opt.
R13
Opt.
C17
4.7uF, 50V
R2
Zero
R14
Optional
R15
Zero
VDD
HB
HOH
HOL
HI
LI
VSS
LOL
GND
HS
LOH
U2
LM5113
R5
33
C7
100p
D2
SDM03U40
R4
22
C6
100p
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3
MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
D6
Opt.
C19
Optional
D5
Opt.
GND
A
B
Y
VDD
U4
NC7SZ08L6X
EPC2007
Q1
EPC2007
Q2
1
Table 2 : Bill of Material
Item Qty Reference Part Description Manufacturer / Part #
1 4 C4, C10, C11, C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 TDK, C1608C0G1H101J
3 1 C12 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1608X5R1E104K
4 2 C16, C17 Capacitor, 2.2uF, 10%, 100V, X5R Taiyo Yuden, HMK325B7225K
5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
6 4 J1, J2, J9, TP3 (See Note 1) Connector FCI, 68001-236HLF
7 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
8 2 Q1, Q2 eGaN® FET EPC, EPC2007
9 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
10 2 R2, R15 Resistor, 0 Ohm, 1/10W Panasonic, ERJ-3GEY0R00V
11 1 R4 Resistor, 22 Ohm, 1%, 1/8W Stackpole, RMCF0603FT22R0
12 1 R5 Resistor, 47 Ohm, 1%, 1/8W Stackpole, RMCF0603FT47R0
13 2 R11, R12 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
14 2 TP1, TP2 Test Point Keystone Elect, 5015
15 1 TP3 Connector 1 pin of Tyco, 4-103185-0
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 R13, R14 Optional Resistor
21 0 C15, C19 Optional Capacitor
22 0 D5, D6 Optional Diode
23 0 P1, P2 Optional Potentiometer
Note 1: 36 pin Header to be cut as follows:
J1: cut 2 pins used
J2 & J9: cut 4 pins used
TP3: cut 1 pin used
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Quick Start Procedure
DESCRIPTION
The EPC9006 development board is a 100 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) eld
eect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge conguration using
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
2. With power o, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
THERMAL CONSIDERATIONS
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambi-
ent temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Logic and
Dead-time
Adjust
LM5113
Gate
Driver
Gate Drive
Supply Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
< 70 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
6, 100
EPC
EFFICIENT POWER CONVERSION
6, 100
Do not use probe ground lead
Do not let probe tip touch
back of low-side die!
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to fa-
cilitate simple waveform measurement and eciency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notication
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1 Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
VIN Bus Input Voltage Range 70* V
VOUT Switch Node Output Voltage 100 V
IOUT Switch Node Output Current 5* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 30 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 100#ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Figure 1: Block Diagram of EPC9006 Development Board