Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI
Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
AD5066
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
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FEATURES
Low power quad 16-bit nanoDAC, ±1 LSB INL
Low total unadjusted error of ±0.1 mV typically
Low zero code error of 0.05 mV typically
Individually buffered reference pins
2.7 V to 5.5 V power supply
Specified over full code range of 0 to 65535
Power-on reset to zero scale or midscale
Per channel power-down with 3 power-down functions
Hardware LDAC with software LDAC override function
CLR
Small 16-lead TSSOP
function to programmable code
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
GENERAL DESCRIPTION
The AD5066 is a low power, 16-bit quad-channel, unbuffered
voltage output nanoDAC® offering relative accuracy specifica-
tions of ±1 LSB INL with individual reference pins and can
operate from a single 2.7 V to 5.5 V supply. The AD5066 also
offers a differential accuracy specification of ±1 LSB DNL.
Reference buffers are also provided on-chip. The part uses a
versatile 3-wire, low power Schmitt trigger serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and most DSP interface
standards. The AD5066 incorporates a power-on reset circuit
that ensures the DAC output powers up to zero scale or
midscale and remains there until a valid write to the device
takes place.
Total unadjusted error for the part is <0.8 mV. Zero code error
for the part is 0.05 mV typically.
The AD5066 contains a power-down feature that reduces the
current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode.
The outputs of all DACs can be updated simultaneously using
the hardware LDAC function, with the added functionality of
user software selectable DAC channels to update simultaneously.
There is also an asynchronous CLR that clears all DACs to a
software-selectable code—0 V, midscale, or full scale.
PRODUCT HIGHLIGHTS
1. Quad channel available in 16-lead TSSOP, ±1 LSB INL.
2. Individually buffered voltage reference pins.
3. TUE = ±0.8 mV max and zero code error = 0.1 mV max.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No. Description
AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP
AD5025/AD5045/AD50651 Dual,12-/14-/16-bit buffered nanoDAC,
TSSOP
AD5024/AD5044/AD50641 Quad 16-bit nanoDAC, TSSOP
AD50621 Single, 16-bit nanoDAC, SOT-23
AD50631 Single, 16-bit nanoDAC, MSOP
AD5061 Single,16-bit nanoDAC, ±4 LSB INL, SOT-23
AD5040/AD50601 14-/16-bit nanoDAC, SOT-23
1 ±1 LSB INL
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
LOGIC
INPUT
REGISTER
DIN
LDAC
GND
V
DD
LDAC
V
REF
A
SYNC
SCLK
AD5066
CLR
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
DAC
REGISTER DAC A
INPUT
REGISTER DAC
REGISTER DAC B
INPUT
REGISTER DAC
REGISTER DAC C
DAC D
INPUT
REGISTER DAC
REGISTER
V
REF
B
V
REF
CV
REF
D
POR
POWER-DOWN LOGIC
POWER-ON RESET
06845-001
Figure 1.
AD5066
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Digital-to-Analog Converter .................................................... 15
DAC Architecture....................................................................... 15
Reference Buffer ......................................................................... 15
Serial Interface ............................................................................ 15
Input Shift Register .................................................................... 15
Power-On Reset .......................................................................... 17
Clear Code Register ................................................................... 18
LDAC Function ........................................................................... 18
Power Supply Bypassing and Grounding ................................ 19
Microprocessor Interfacing ....................................................... 19
Applications Information .............................................................. 21
Using a Reference as a Power Supply ....................................... 21
Bipolar Operation....................................................................... 21
Using the AD5066 with a Galvanically Isolated Interface .... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Change to Minimum SYNC
7/09—Revision 0: Initial Version
High Time, Single
Channel Update Parameter, Table 4 ............................................... 5
AD5066
Rev. A | Page 3 of 24
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.0 V ≤ VREFA, VREFB, VREFC, VREFD ≤ VDD − 0.4 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
A Grade1 B Grade1
Unit Conditions/Comments
Min Typ Max Min Typ Max
STATIC PERFORMANCE2
Resolution 16 16 Bits
Relative Accuracy (INL) ±0.5 ±4 ±0.5 ±1 LSB TA = −40°C to +105°C
±0.5 ±4 ±0.5 ±2 TA = −40°C to +125°C
Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB
Total Unadjusted Error (TUE) ±0.1 ±0.8 ±0.1 ±0.8 mV VDD = 2.7 V, VREF = 2 V
Zero-Code Error 0.05 0.1 0.05 0.1 mV All 0s loaded to the DAC register
Zero-Code Error Drift3 ±0.5 ±0.5 µV/°C
Full-Scale Error ±0.01 ±0.05 ±0.01 ±0.05 % FSR All 1s loaded to the DAC register
Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR
Gain Error Drift3 ±0.5 ±0.5 ppm ppm of FSR/°C
DC Crosstalk3 1 5 1 5 μV Due to single-channel full-scale
output change
5 25 5 25 μV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VREF 0 VREF V
DC Output Impedance (Normal
Mode)
8 8 kΩ Output impedance tolerance ± 10%
DC Output Impedance DAC in power-down mode
Output Connected to 100 kΩ
Network
100 100 kΩ Output impedance tolerance ± 20 kΩ
Output Connected to 1 kΩ
Network
1 1 kΩ Output impedance tolerance ± 400 Ω
Power-Up Time4 2.9 2.9 µs
DC PSRR −120 −120 dB VDD ± 10%, DAC = full scale
REFERENCE INPUTS
Reference Input Range 2 VDD − 0.4 2 VDD − 0.4 V
Reference Current 0.002 ±1 0.002 ±1 µA Per DAC channel
Reference Input Impedance 40 40 MΩ Per DAC channel
LOGIC INPUTS3
Input Current5 ±1 ±1 µA
Input Low Voltage, VINL 0.8 0.8 V
Input High Voltage, VINH 2.2 2.2 V
Pin Capacitance 4 4 pF
POWER REQUIREMENTS
VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
DAC active, excludes load current
IDD VIH = VDD and VIL = GND
Normal Mode6 2.5 3 2.5 3 mA
All Power-Down Modes7 0.4 0.4 µA
1 Temperature range is −40°C to +125°C, typical at 25°C.
2 Linearity calculated using a code range of 0 to 65,535; output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded.
5 Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.
6 Interface inactive. All DACs active. DAC outputs unloaded.
7 All four DACs powered down.
AD5066
Rev. A | Page 4 of 24
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 2.0 V ≤ VREFA, VREFB, VREFC, VREFD ≤ VDD − 0.4 V all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2 Min Typ Max Unit Conditions/Comments3
DYNAMIC PERFORMACE
Output Voltage Settling Time 7.5 10 µs ¼ to ¾ scale settling to ±2 LSB, single channel update, output
unloaded
Output Voltage Settling Time 12 15 µs ¼ to ¾ scale settling to ±2 LSB, all channel update, output
unloaded
Slew Rate 1.7 V/µs
Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry
Reference Feedthrough −70 dB VREF = 3 V ± 0.5 V p-p, frequency = 60 Hz to 20 MHz
Digital Feedthrough 0.02 nV-sec
Digital Crosstalk 1.7 nV-sec
Analog Crosstalk 3.7 nV-sec
DAC-to-DAC Crosstalk 5.4 nV-sec
Total Harmonic Distortion −83 dB VREF = 3 V ± 0.2 V p-p, frequency = 10 kHz
Output Noise Spectral Density 30 nV/√Hz DAC code = 0x8000, 1 kHz
25 nV/√Hz DAC code = 0x8000, 10 kHz
Output Noise 4.7 μV p-p 0.1 Hz to 10 Hz
1 Temperature range is −40°C to +125°C, typical at +25°C.
2 See the Terminology section.
3 Guaranteed by design and characterization; not production tested.
AD5066
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to
5.5 V, all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 4.
Parameter1 Symbol Min Typ Max Unit
SCLK Cycle Time t1 20 ns
SCLK High Time t2 10 ns
SCLK Low Time t3 10 ns
SYNC to SCLK Falling Edge Set-Up Time t4 17 ns
Data Set-Up Time t5 5 ns
Data Hold Time t6 5 ns
SCLK Falling Edge to SYNC Rising Edge t7 5 30 ns
Minimum SYNC High Time t8
Single Channel Update 3 µs
All Channel Update 8 µs
SYNC Rising Edge to SCLK Fall Ignore t9 17 ns
LDAC Pulse Width Low t10 20 ns
SCLK Falling Edge to LDAC Rising Edge t11 20 ns
CLR Pulse Width Low t12 10 ns
SCLK Falling Edge to LDAC Falling Edge t13 10 ns
CLR Pulse Activation Time t14 10.6 µs
1 Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
t4t3
SCLK
SYNC
DIN
t1
t2
t5
t6
t7
t8
DB31
t9
t10
t11
LDAC
1
LDAC
2
t13
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
CLR
t12
t1
4
V
OUT
DB0
06845-003
Figure 2. Serial Write Operation
AD5066
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
VOUTx to GND −0.3 V to VDD + 0.3 V
VREFx to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ MAX) +150°C
TSSOP Package
Power Dissipation (TJ MAX − TA)/θJA
θ
JA
Thermal Impedance 150.4°C/W
Reflow Soldering Peak Temperature
SnPb 240°C
Pb-Free 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5066
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
V
DD
V
REF
B
V
OUT
C
V
OUT
A
V
REF
A
POR
16
15
14
13
12
11
10
9
DIN
GND
V
OUT
B
V
REF
C
V
REF
D
V
OUT
D
SCLK
AD5066
TOP VIEW
(No t t o Scal e)
LDAC
SYNC
CLR
06845-004
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 LDAC Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.
When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd
clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but
the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt, and the write sequence is ignored by the device.
3 VDD Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.
4 VREFB External Reference Voltage Input for DAC B.
5 VREFA External Reference Voltage Input for DAC A.
6 VOUTA Unbuffered Analog Output Voltage from DAC A.
7 VOUTC Unbuffered Analog Output Voltage from DAC C.
8 POR Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying
this pin to VDD powers the DAC outputs to midscale.
9 VREFC External Reference Voltage Input for DAC C.
10 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11 VREFD External Reference Voltage Input for DAC D.
12 VOUTD Unbuffered Analog Output Voltage from DAC D.
13 VOUTB Unbuffered Analog Output Voltage from DAC B.
14 GND Ground Reference Point for All Circuitry on the Part.
15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
AD5066
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
010,000 20,000 30,000 40,000 50,000 60,000
INL ERRO R ( LSB)
CODE
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-105
Figure 4. INL Error vs. Code
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
010,000 20,000 30,000 40,000 50,000 60,000
DNL E RROR (L S B)
CODE
VDD = 5V
VREF = 4. 096V
TA = 25° C
06845-106
Figure 5. DNL Error vs. Code
Figure 6. Total Unadjusted Error vs. Code
–0.5
–0.4
–0.3
–0.2
0
0.1
–0.1
0.2
0.3
0.4
0.5
2345
INL (LSB)
REFERENCE VOLTAGE (V)
MIN INL
MAX INL
V
DD
= 5V
T
A
= 25° C
06845-108
Figure 7. INL vs. Reference Input Voltage
–0.5
–0.4
–0.3
–0.2
0
0.1
–0.1
0.2
0.3
0.4
0.5
2345
DNL ( LSB)
REFERENCE VOLTAGE (V)
MIN DNL
MAX DNL
V
DD
= 5.5V
T
A
= 25° C
06845-109
Figure 8. DNL vs. Reference Input Voltage
–100
–80
–60
–40
–20
0
20
40
60
80
100
2345
TOTAL UNADJUSTED E RROR (µV)
REFERENCE VOLT AGE (V)
MAX TUE
MI N TUE
V
DD
= 5.5V
T
A
= 25° C
06845-110
Figure 9. Total Unadjusted Error vs. Reference Input Voltage
AD5066
Rev. A | Page 9 of 24
GAIN ERROR (%FSR)
REFERENCE VOLTAGE (V)
–0.010
–0.005
0
0.005
0.010
2345
V
DD
= 5.5V
T
A
= 25° C
06845-111
Figure 10. Gain Error Vs. Reference Input Voltage
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
2345
ZE RO-SCALE E RROR (mV )
REFERENCE VOLT AGE (V)
VDD = 5.5V
TA = 25° C
06845-112
Figure 11. Zero-Code Error Vs. Reference Input Voltage
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
–40 –20 020 40 60 80 100 120
INL (LSB)
TEMPERATURE (°C)
MAX INL
MI N INL
V
DD
= 5V
V
REF
= 4.096V
06845-113
Figure 12. INL vs. Temperature
–1.2
–0.8
–1.0
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
–40 –20 020 40 60 80 100 120
DNL ( LSB)
TEMPERATURE (°C)
MAX DNL
MI N DNL
VDD = 5V
VREF = 4. 096V
06845-114
Figure 13. DNL vs. Temperature
–100
–80
–60
–40
–20
0
20
40
60
80
100
–40 –20 020 40 60 80 100 120
TOTAL UNADJUSTED E RROR (µ V )
TEMPERATURE (°C)
MAX TUE
MI N TUE
V
DD
= 5V
V
REF
= 4.096V
06845-115
Figure 14. Total Unadjusted Error vs. Temperature
–50
–40
–30
–20
–10
0
10
20
30
40
50
–40 –20 020 40 60 80 100 120
ZERO-SCALE ERROR (µV)
TEMPERATURE (°C)
V
DD
= 5V
V
REF
= 4.096V
06845-116
Figure 15. Zero-Code Error vs. Temperature
AD5066
Rev. A | Page 10 of 24
–0.0020
–0.0015
–0.0010
–0.0005
0.0005
0
0.0010
0.0015
0.0020
–40 –20 020 40 60 80 100 120
GAIN ERRO R ( %FSR)
TEMPERATURE (°C)
VDD = 5V
VREF = 4. 096V
06845-117
Figure 16. Gain Error vs. Temperature
–0.010
–0.005
0
0.005
0.010
2.73.2 3.7 4.2 4.7 5.2
ERRO R (%FSR)
V
DD
(V)
FULL-SCALE ERROR
GAIN ERROR
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-118
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
0
5
10
15
20
2.7 3.7 4.7
ZERO-SCALE Error (µV)
V
DD
(V)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-119
Figure 18. Zero-Code Error vs. Supply Voltage
7
2.45
HITS
I
DD
POWER-UP (mA)
6
5
4
3
2
1
02.50 2.55 2.60 2.65 2.70
V
DD
= 5V
DAC OUTPUT UNLO ADE D
T
A
= 25° C
06845-120
Figure 19. IDD Histogram VDD = 5.5 V
06845-139
60
50
40
30
20
10
00.2 0.4 0.6
IDD P OW E RDOW N (µA)
HITS
0.8 1.0
+125°C IDD PO WERDO WN
+25°C IDD PO WERDOW N
–40°C IDD POW E RDOWN
VDD = 5V
TA = 25° C
DAC OUTPUT UNLO ADE D
Figure 20. IDD Power-Down Histogram
0
1
2
3
4
5
010,000 20,000 30,000 40,000
DAC CODE
IDD ( mA)
50,000 60,000
06845-121
VDD = 5.5V
VREF = 4. 096V
TA = 25° C
Figure 21. IDD vs. Code
AD5066
Rev. A | Page 11 of 24
0
1
2
3
4
5
–40 –20 020 40
TEMPERATURE (°C)
60 80 100 120
I
DD
(mA)
06845-122
V
DD
= 5.5V
V
REF
= 4.096V
T
A
= 25° C
CODE = M IDSCALE
Figure 22. IDD vs. Temperature
2.7 3.0 3.5 4.0 4.5
SUPPLY VOLT AGE (V) 5.0 5.5
0
1
2
3
4
5
I
DD
(mA)
06845-123
V
REF
= 4.096V
T
A
= 25° C
CODE = M IDSCALE
Figure 23. IDD vs. Supply Voltage
DIGITAL INPUT VOLTAGE (V)
IDD (mA)
0
2
4
6
8
10
0 1
23456
06845-124
VDD = 5.5V
VREF = 4. 096V
TA = 25° C
Figure 24. IDD vs. Digital Input Voltage
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
012345678910
OUTPUT VOLTAGE (V)
TIME (µs)
1/4 TO 3/4
3/4 TO 1/4
06845-125
V
DD
= 4.5V
V
REF
= 4.096V
OUTPUT AM P LI FI E R = AD797
T
A
= 25° C
DAC LOAD = 9p F
Figure 25. Settling Time
CH1 2.00V
CH3 2.00V CH2 2.00V M10.00ms A CH1 640mV
T 30.20%
V
DD
V
REF
V
OUT
06845-126
V
REF
= 4.096V
T
A
= 25°C
Figure 26. POR to 0 V
CH1 2.00V
CH3 2.00V CH2 2.00V M10.00ms A CH1 640mV
T 30.20%
V
DD
V
REF
V
OUT
06845-127
V
DD
= 5.5V
V
REF
= 4.096V
Figure 27. POR to MS
AD5066
Rev. A | Page 12 of 24
CH1 5V CH2 500mV M2µs A CH2 1.2V
2
1
T 55%
CH1 = SCL K
CH2 = V
OUT
V
DD
= 5V
POWER-UP TO MI DSCALE
OUTPUT UNLO ADE D
06845-128
Figure 28. Exiting PD to MS
–15
–10
–5
0
5
10
15
–2 0246810
TIME (µs)
GLITCH AMPLITUDE (mV)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
CODE = 0x8000 TO 0x7FF F
OUTPUT UNLO ADE D WI TH 5kΩ AND 200pF
06845-129
Figure 29. Glitch
–15
–10
–5
0
5
10
15
–2 0246810
TIME (µs)
GLITCH AMPLITUDE (mV)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-130
Figure 30. Analog Crosstalk
–15
–10
–5
0
5
10
15
–2 0246810
TIME (µs)
GLITCH AMPLITUDE (mV)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-131
Figure 31. Digital Crosstalk
–20
–15
–10
–5
0
5
10
20
15
–2 0246810
TIME (µs)
GLITCH AMPLITUDE (mV)
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
06845-132
Figure 32. DAC-to-DAC Crosstalk
4
3
2
1
0
–1
–2
–3
–4 0 1 4 7
OUTPUT VOLTAGE (µV)
Time (Secon ds)
2 5 8
36910
06845-133
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25° C
Figure 33. 1/f Noise
AD5066
Rev. A | Page 13 of 24
0
–20
–50
–80
–100 510 30 40 55
06845-016
V
OUT
LEVEL (d B)
FRE QUENCY ( kHz )
–90
–70
–60
–10
–30
–40
20 50
V
DD
= 5V,
T
A
= 25ºC
DAC LOADED W IT H M IDSCALE
V
REF
= 3.0V ± 200mV p-p
Figure 34. Total Harmonic Distortion
CH1 5.00V CH2 2.00V M2.00ms A CH1 1. 80V
T 10.20%
CLR
VOUT
06845-135
Figure 35. Hardware CLR
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
1.5 1.6 1.7 1.8 1.9 22.1 2.2 2.3 2.4
OUTPUT VOLTAGE (V)
TIME (µs)
3/4 TO 1/4
1/4 TO 3/4
06845-136
VDD = 4.5V
VREF = 4. 096V
TA = 25° C
Figure 36. Slew Rate
CH1 50.0mV CH2 5.00V M4.00µs A CH2 1. 80V
T 9.800%
LAST SCLK
V
OUT
CH1 PEAK TO P E AK
155mV
06845-137
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25°C
Figure 37. Glitch Upon Entering Power Down
CH1 50.0mV CH2 5.00V M4.00µs A CH2 1. 80V
T 9.800%
LAST SCLK
V
OUT
CH1 PEAK TO P E AK
159mV
06845-138
V
DD
= 5V
V
REF
= 4.096V
T
A
= 25°C
Figure 38. Glitch Upon Exiting Power Down
AD5066
Rev. A | Page 14 of 24
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy or INL is a measure of the maximum
deviation in LSBs from a straight line passing through the
endpoints of the DAC transfer function. Figure 4, Figure 5,
and Figure 6 show typical INL vs. code plots.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono-
tonicity. Figure 7, Figure 8, and Figure 9 show typical DNL vs.
code plots.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5066, because the output of the DAC cannot go below
0 V. Zero-code error is expressed in millivolts. Figure 17 shows
a typical zero-code error vs. supply voltage plot.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in microvolts
per degrees Celsius.
Full-Scale Error
Full-scale error is a measure of the output error when a full-
scale code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovolts
per second and is measured when the digital input code is
changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Figure 28.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. DC PSRR is the ratio of the
change in VOUT to a change in VDD for full-scale output of the
DAC. It is measured in decibels.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC
Digital Feedthrough
is high). It is expressed in
decibels.
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(SYNC
Digital Crosstalk
held high). It is specified in nanovolts per second and
measured with one simultaneous DIN and SCLK pulse loaded
to the DAC.
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolts per second.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high and then pulsing
DAC-to-DAC Crosstalk
LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolts per second.
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC
Total Harmonic Distortion (THD)
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolts per second.
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as
the reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in
decibels.
AD5066
Rev. A | Page 15 of 24
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5066 is a quad 16-bit, serial input, voltage output
nanoDAC. The part operates from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5066 in a 32-bit word format via
a 3-wire serial interface. The AD5066 incorporates a power-on
reset circuit to ensure the DAC output powers up to a known
output state. The devices also have a software power-down mode
that reduces the typical current consumption to typically 400 nA.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
N
REFIN
OUT
D
VV
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 39. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either GND or the VREF buffer
output. The remaining 12 bits of the data word drive the S0 to
S11 switches of a 12-bit voltage mode R-2R ladder network.
2R
S0
V
REF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
V
OUT
12-BI T R-2R L ADDE R FOUR MS Bs DECODED
INT O 15 E Q UAL
SEGMENTS
06845-005
Figure 39. DAC Ladder Structure
REFERENCE BUFFER
The AD5066 operates with an external reference. Each of the
four on-board DACs has a dedicated voltage reference pin that
is buffered. The reference input pin has an input range of 2 V
to VDD − 0.4 V. This input voltage is then used to provide a
buffered reference for the DAC core.
SERIAL INTERFACE
The AD5066 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. See Figure 2 for a timing diagram
of a typical write sequence.
INPUT SHIFT REGISTER
The input shift register is 32 bits wide (see Figure 40). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 8), and finally the bit data-word. The
data-word comprises of a 16-bit input code followed by four don’t
care bits (see Figure 40). These data bits are transferred to the
Input register on the 32nd falling edge of SCLK. Commands can
be executed on individually selected DAC channels or on all DACs.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 Write to Input Register n
0 0 0 1 Transfer contents of Input Register n to
DAC Register n
0 0 1 0 Write to Input Register n and update all
DAC Registers
0 0 1 1 Write to Input Register n and update
DAC Register n
0 1 0 0 Power down/power up DAC
0 1 0 1 Load clear code register
0 1 1 0 Load LDAC register
0 1 1 1 Reset (power-on reset)
1 0 0 0 Reserved
1 0 0 1 Reserved
1 1 1 1 Reserved
Table 8. DAC Input Register Address Bits
Address (n)
Selected DAC Channel
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
1 1 1 1 All DACs
ADDRESS BITSCOMM AND BITS
C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X
XXXX
DB31 (MSB) DB0 (L S B)
DATA BI TS
06845-007
Figure 40. Input Shift Register Content
AD5066
Rev. A | Page 16 of 24
The write sequence begins by bringing the SYNC line low.
Bringing the SYNC line low enables the DIN and SCLK input
buffers. Data from the DIN line is clocked into the 32-bit shift
register on the falling edge of SCLK. The serial clock frequency
can be as high as 50 MHz, making the AD5066 compatible with
high speed DSPs. On the 32nd falling clock edge, the last data bit
is clocked in, and the programmed function is executed, that is,
a change in the input register contents (see Table 8) and/or a
change in the mode of operation. At this stage, the SYNC line
can be kept low or be brought high. In either case, it must be
brought high for a minimum of 2 μs (single-channel update, see
the t8 parameter in Table 4) before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Idle SYNC high between write sequences for even lower power
operation of the part.
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The input shift register is reset, and the write sequence is seen
as invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 42).
Power-Down Modes
The AD5066 can be configured through software, in one of
four different modes: normal mode (default) and three separate
power-down modes (see Table 9). Any or all DACs can be
powered down. Command 0100 is reserved for the power-
down function (see Table 7). These power-down modes are
software-programmable by setting two bits, Bit DB9 and
Bit DB8, in the input shift register. Table 9 shows how the state
of the bits corresponds to the mode of operation of the device.
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 10 for the contents of the input
shift register during power-down/power-up operation.
When Bit DB9 and Bit DB8 in the control register are set to 0,
the part is configured in normal mode with its normal power
consumption of 2.5 mA at 5 V. However, for the three power-
down modes, the supply current falls to 0.4 µA if all the channels
are powered down. Not only does the supply current fall, but
the output pin is also internally switched from the output of the
DAC to a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ or
a 100 kΩ resistor, or it is left open-circuited (three-state). The
output stage is illustrated in Figure 41.
RESISTOR
NETWORK
V
OUT
DAC
POWER-DOWN
CIRCUITRY
06845-008
Figure 41. Output Stage During Power-Down Mode
The bias generator, DAC core, and other associated linear
circuitry are shut down when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down mode. The time to exit power-down mode is
typically 2.9 µs (see Figure 27).
Table 9. Modes of Operation
DB9 DB8 Operating Mode
0 0 Normal operation
Power-down modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state
SCLK
DIN
DB31 DB0
INVALI D WRI TE S E QUENCE:
SYNC HI GH BEFO RE 32
ND
FALLING EDGE VALID W RIT E S E QUENCE :
OUT P UT UPDATES ON T HE 32
ND
FALLING EDGE
DB31 DB0
SYNC
06845-017
Figure 42. SYNC Interrupt Facility
AD5066
Rev. A | Page 17 of 24
POWER-ON RESET
The AD5066 contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the POR
pin low, the AD5066 output powers up to 0 V; by connecting
the POR pin high, the AD5066 output powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB LSB
DB31 to
DB28 DB27 DB26 DB25 DB24
DB23 to
DB20
DB10 to
DB19 DB9 DB8
DB4 to
DB7 DB3 DB2 DB1 DB0
X 0 1 0 0 X X PD1 PD0 X DAC D DAC C DAC B DAC A
Don’t
cares
Command bits (C2 to C0) Address bits
(A3 to A0)—
don’t cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel
selection—set bit to 1 to select
AD5066
Rev. A | Page 18 of 24
CLEAR CODE REGISTER
The AD5066 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly (see
Table 11). This function can be used in system calibration to
load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the control register (see Table 11).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 7).
Table 11. Clear Code Register
DB1 (CR1) DB0 (CR0) Clears to Code
0 0 0x0000
0 1 0x8000
1 0 0xFFFF
1 1 No operation
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time (the falling edge of CLR to when
the output starts to change) is typically 10.6 µs. See Table 13 for
contents of the input shift register during the loading clear code
register operation.
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 2. There are two
methods of using the hardware LDAC pin: synchronously
(LDAC permanently low) and asynchronously (LDAC pulsed).
Synchronous LDAC: LDAC is held permanently low. After new
data is read, the DAC registers are updated on the falling edge
of the 32nd SCLK pulse, provided LDAC is held low.
Asynchronous LDAC: LDAC is held high then pulsed low to
update. The outputs are not updated at the same time that the
input registers are written to. When LDAC is pulsed low, the
DAC registers are updated with the contents of the input
registers.
Command 0001, 0010 and 0011 (see Table 7) update the DAC
Register/Registers, regardless of the level of the LDAC pin
Software LDAC Function
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel is
0; that is, the LDAC pin works normally. Setting the bits to 1
updates the DAC channel regardless of the state of the hardware
LDAC pin, so that it effectively sees the hardware LDAC pin
as being tied low (see Table 12 for the LDAC register mode of
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.
Table 12. Load LDAC
LDAC Bits
(DB3 to
DB0)
Register
LDAC
Pin LDAC Operation
0 1/0 Determined by LDAC pin
1 X1 DAC channels update, overrides the LDAC
pin; DAC channels see LDAC as 0
1 X = don’t care.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 14). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
Table 13. 32-Bit Input Shift Register Contents for Clear Code Function
MSB LSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0
X 0 1 0 1 X X X X X 1/0 1/0
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register
(CR1 to CR0)
Table 14. 32-Bit Input Shift Register Contents for LDAC
MSB
Overwrite Function
LSB
DB31
to DB28 DB27 DB26 DB25 DB24 DB23 to DB20
DB4
to DB19 DB3 DB2 DB1 DB0
X 0 1 1 0 X X DAC D DAC C DAC B DAC A
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Setting LDAC bit to 1 override LDAC pin
AD5066
Rev. A | Page 19 of 24
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND con-
nection, make the connection at one point only and as close as
possible to the AD5066.
Bypass the power supply to the AD5066 with 10 µF and 0.1 µF
capacitors. The capacitors should be physically as close as
possible to the device, with the 0.1 µF capacitor, ideally, right up
against the device. The 10 µF capacitors are the tantalum bead
type. It is important that the 0.1 µF capacitor has low effective
series resistance and low effective series inductance, typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield the clocks and other fast switching digital
signals from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at
right angles to each other to reduce feedthrough effects through
the board. The best board layout technique is the microstrip
technique, where the component side of the board is dedicated
to the ground plane only, and the signal traces are placed on
the solder side. However, this is not always possible with a
2-layer board.
MICROPROCESSOR INTERFACING
AD5066 to Blackfin® ADSP-BF53X Interface
Figure 43 shows a serial interface between the AD5066 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multipro-
cessor communications. Using SPORT0 to connect to the
AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, TSCLK0 drives the SCLK
of the parts, and TFS0 drives SYNC.
AD5066*
ADSP-BF53x*
SYNCTFS0
DINDT0PRI
SCLKTSCLK0
*ADDITIONAL PINS OMITTED FOR CLARITY.
06845-009
Figure 43. AD5066 to Blackfin ADSP-BF53X Interface
AD5066 to 68HC11/68L11 Interface
Figure 44 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
DIN of the DAC. A port line (PC7) drives the SYNC signal.
AD5066*
68HC11/68L11*
SYNCPC7
SCLKSCK
DINMOSI
*ADDITIONAL PINS OMITTED FOR CLARITY.
06845-010
Figure 44. AD5066 to 68HC11/68L11 Interface
The setup conditions for correct operation of this interface are
as follows: The 68HC11/68L11 is configured with its CPOL bit
as 0, and the CPHA bit as 1. When data is being transmitted to
the DAC, the SYNC line is taken low (PC7). When the 68HC11/
68L11 is configured as described previously, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5066
Rev. A | Page 20 of 24
AD5066 to 80C51/80L51 Interface
Figure 45 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,
RxD drives DIN on the AD5066, and a bit-programmable pin on
the port (P3.3) drives the SYNC signal. When data is to be
transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51
transmit data in 8-bit bytes only; thus, only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second,
third, and fourth write cycle is initiated to transmit the second,
third, and fourth byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5066 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5066*
SYNCP3.3
SCLKTxD
DINRxD
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
06845-011
Figure 45. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
Figure 46 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is clocked into
the AD5066 on the falling edge of the SCLK.
AD5066*
SYNCCS
DINSK
SCLKSO
*ADDITIONAL PINS OMITTED FOR CLARITY.
MICROWIRE*
06845-012
Figure 46. AD5066 to MICROWIRE Interface
AD5066
Rev. A | Page 21 of 24
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY
Because the supply current required by the AD5066 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the parts (see Figure 47). This is espe-
cially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V or 3 V, for
example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5066. If the low dropout REF195 is used, it
must supply 2.5 mA of current to the AD5066 with no load on
the output of the DAC.
SYNC
SCLK
DIN
15V
5V 4.5V
VOUTx = 0V TO 4.5V
VDD VREF
REF195
AD5066
3-WIRE
SERIAL
INTERFACE
REF194
06845-013
Figure 47. REF195 as a Power Supply to the AD5066
BIPOLAR OPERATION
The AD5066 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 48. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achieved
using an AD8638 or AD8639 the output amplifier.
The output voltage for any input code can be calculated as
follows:
×−
+
×
×=
R1
R2
V
R1
R2R1D
VV
DDDD
O
536,65
where:
D = the input code in decimal (0 to 65,535).
VDD = 5 V.
R1 = R2 = 10 kΩ.
V5
536,65
10 −
×
=D
VO
This is an output voltage range of ±5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
3-WIRE
SERIAL INT E RFACE
R2 = 10kΩ
+5V
AD820/
OP295
+5.5V +5V
AD5066
V
DD
V
OUT
R1 = 10kΩ
V
REF
±5V
0.1µF
10µF
V
REF
–5V
06845-014
Figure 48. Bipolar Operation with the AD5066
USING THE AD5066 WITH A GALVANICALLY
ISOLATED INTERFACE
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so
the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 49). The power supply to the
part also needs to be isolated, which is done by using a
transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5066.
0.1µF
GND
DIN
SYNC
SCLK
POWER 10µF
SDI
SCLK
DATA
AD5066
V
OUT
x
V
OB
V
OA
V
OC
V
DD
V
IC
V
IB
V
IA
ADuM1300
5V
REGULATOR
06845-015
Figure 49. AD5066 with a Galvanically Isolated Interface
AD5066
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeter
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
Power-On
Reset to Code Accuracy Resolution
AD5066BRUZ −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits
AD5066BRUZ-REEL7 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits
AD5066ARUZ −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits
AD5066ARUZ-REEL7 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits
1 Z = RoHS Compliant Part.
AD5066
Rev. A | Page 23 of 24
NOTES
AD5066
Rev. A | Page 24 of 24
NOTES
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registered trademarks are the property of their respective owners.
D06845-0-8/10(A)