Ultralow Noise VGAs with
Preamplifier and Programmable RIN
AD8331/AD8332/AD8334
Rev. G
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FEATURES
Ultralow noise preamplifier (preamp)
Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz
3 dB bandwidth
AD8331: 120 MHz
AD8332, AD8334: 100 MHz
Low power
AD8331: 125 mW/channel
AD8332, AD8334: 145 mW/channel
Wide gain range with programmable postamp
−4.5 dB to +43.5 dB in LO gain mode
7.5 dB to 55.5 dB in HI gain mode
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-bit/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
AD8332 and AD8334 available in lead frame chip scale package
APPLICATIONS
Ultrasound and sonar time-gain controls
High performance automatic gain control (AGC) systems
I/Q signal processing
High speed, dual ADC drivers
GENERAL DESCRIPTION
The AD8331/AD8332/AD8334 are single-, dual-, and quad-
channel, ultralow noise linear-in-dB, variable gain amplifiers
(VGAs). Optimized for ultrasound systems, they are usable as a
low noise variable gain element at frequencies up to 120 MHz.
Included in each channel are an ultralow noise preamp (LNA),
an X-AMP® VGA with 48 dB of gain range, and a selectable gain
postamp with adjustable output limiting. The LNA gain is 19 dB
with a single-ended input and differential outputs. Using a single
resistor, the LNA input impedance can be adjusted to match a
signal source without compromising noise performance.
The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching.
FUNCTIONAL BLOCK DIAGRAM
03199-001
VOL
VOH
V
MID
LNA
48dB
ATTENUATOR
ENB
INH
LMD
V
IN
V
IPLOPLON
GAIN
AD8331/AD8332/AD8334
+
CLAMP
RCLMP
HIL
O
V
CM
3.5dB OR 15.5dB
19dB PA
VCM
BIAS VGA BIAS AND
INTERPOLATOR
GAIN
CONTROL
INTERFACE
21dB
Figure 1. Signal Path Block Diagram
60
50
40
30
20
10
0
–10
100k 1M 10M 100M 1G
GAIN (dB)
FREQUENCY (Hz)
03199-002
VGAIN = 1V
VGAIN = 0.8V
VGAIN = 0.6V
VGAIN = 0.4V
VGAIN = 0.2V
VGAIN = 0V
HI GAIN
MODE
Figure 2. Frequency Response vs. Gain
Differential signal paths result in superb second- and third-
order distortion performance and low crosstalk.
The low output-referred noise of the VGA is advantageous in
driving high speed differential ADCs. The gain of the postamp
can be pin selected to 3.5 dB or 15.5 dB to optimize gain range
and output noise for 12-bit or 10-bit converter applications. The
output can be limited to a user-selected clamping level, preventing
input overload to a subsequent ADC. An external resistor adjusts
the clamping level.
The operating temperature range is −40°C to +85°C. The
AD8331 is available in a 20-lead QSOP package, the AD8332 is
available in 28-lead TSSOP and 32-lead LFCSP packages, and
the AD8334 is available in a 64-lead LFCSP package.
AD8331/AD8332/AD8334
Rev. G | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 12
Test Circuits ..................................................................................... 20
Measurement Considerations ................................................... 20
Theory of Operation ...................................................................... 24
Overvie w ...................................................................................... 24
Low Noise Amplifier (LNA) ..................................................... 25
Variable Gain Amplifier ............................................................ 27
Postamplifier ............................................................................... 28
Applications Information .............................................................. 30
LNA—External Components .................................................... 30
Driving ADCs ............................................................................. 32
Overload ...................................................................................... 32
Optional Input Overload Protection ....................................... 32
Layout, Grounding, and Bypassing .......................................... 33
Multiple Input Matching ........................................................... 33
Disabling the LNA ...................................................................... 33
Ultrasound TGC Application ................................................... 34
High Density Quad Layout ....................................................... 34
AD8331 Evaluation Board ............................................................ 39
General Description ................................................................... 39
User-Supplied Optional Components ..................................... 39
Measurement Setup.................................................................... 39
Board Layout ............................................................................... 39
AD8331 Evaluation Board Schematics .................................... 40
AD8331 Evaluation Board PCB Layers ................................... 42
AD8332 Evaluation Board ............................................................ 43
General Description ................................................................... 43
User-Supplied Optional Components ..................................... 43
Measurement Setup.................................................................... 43
Board Layout ............................................................................... 43
Evaluation Board Schematics ................................................... 44
AD8332 Evaluation Board PCB Layers ................................... 46
AD8334 Evaluation Board ............................................................ 47
General Description ................................................................... 47
Configuring the Input Impedance ........................................... 48
Measurement Setup.................................................................... 48
Board Layout ............................................................................... 48
Evaluation Board Schematics ................................................... 49
AD8334 Evaluation Board PCB Layers ................................... 51
Outline Dimensions ....................................................................... 53
Ordering Guide .......................................................................... 55
REVISION HISTORY
10/10—Rev. F to Rev. G
Changes to Quiescent Current per Channel Parameter,
Table 1 ................................................................................................ 6
Changes to Pin 1, Table 3 ................................................................. 8
Changes to Pin 1 and Pin 28, Table 4 and Pin 4 and Pin 5,
Table 5 ................................................................................................ 9
Changes to Figure 6 and Table 6 ................................................... 10
Changes to Figure 33 ...................................................................... 16
Changes to Figure 64 ...................................................................... 22
Changes to Figure 70 ...................................................................... 24
Changes to Low Noise Amplifier (LNA) Section and
Figure 74 .......................................................................................... 25
Changes to Figure 94 ...................................................................... 38
Changes to General Descriptions Section, Figure 95 Caption,
Table 10, and Board Layout Section ............................................. 39
Changes to Figure 96 ...................................................................... 40
Changes to Figure 97 ...................................................................... 41
Changes to Figure 98 and Figure 103 ........................................... 42
Deleted AD8331 Bill of Materials Section and Table 11;
Renumbered Sequentially ............................................................. 43
Changes to Figure 104 ................................................................... 43
Changes to Figure 106 ................................................................... 45
Changes to Figure 107 ................................................................... 46
Changes to Figure 113 ................................................................... 47
Changes to Figure 114 and Board Layout Section ..................... 48
Deleted AD8332 Bill of Materials Section and Table 13;
Renumbered Sequentially ............................................................. 48
Changes to Figure 115 ................................................................... 49
Changes to Figure 116 ................................................................... 50
Changes to Figure 117 to Figure 120 ........................................... 51
Changes to Figure 121 ................................................................... 52
Deleted AD8334 Bill of Materials Section and Table 15;
Renumbered Sequentially ............................................................. 54
AD8331/AD8332/AD8334
Rev. G | Page 3 of 56
4/08—Rev. E to Rev. F
Changed RFB to RIZ Throughout ..................................................... 4
Changes to Figure 1 ........................................................................... 1
Changes to Table 1, LNA and VGA Characteristics, Output
Offset Voltage, Conditions ............................................................... 4
Changes to Quiescent Current per Channel and Power Down
Current Parameters ........................................................................... 6
Changes to Table 2 ............................................................................ 7
Changes to Table 3, Pin 1 Description ........................................... 8
Changes to Table 4, Pin 1 and Pin 28 Descriptions ...................... 9
Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................ 9
Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions ...... 10
Changes to Table 6, Pin 61 Description ....................................... 11
Changes to Typical Performance Characteristics Section,
Default Conditions .......................................................................... 12
Changes to Figure 25 ...................................................................... 15
Changes to Figure 39 ...................................................................... 17
Changes to Figure 55 Through Figure 68 ................................... 20
Changes to Theory of Operation, Overview Section ................. 24
Changes to Low Noise Amplifier Section and Figure 74 ........... 25
Changes to Active Impedance Matching Section, Figure 75,
and Figure 77 ................................................................................... 26
Changes to Figure 78 ...................................................................... 27
Changes to Equation 6, Table 7, Figure 81, and Figure 82 ......... 30
Changes to Figure 83 ...................................................................... 31
Changes to Figure 88 ...................................................................... 32
Switched Figure 89 and Figure 90 ................................................. 33
Changes to Figure 89 ...................................................................... 33
Changes to Ultrasound TGC Application Section...................... 34
Incorporated AD8331-EVAL Data Sheet, Rev. A ....................... 39
Changes to User-Supplied Optional Components Section
and Measurement Setup Section ................................................... 39
Changes to Figure 95 ...................................................................... 39
Changes to Figure 97 ...................................................................... 41
Added Figure 98 .............................................................................. 42
Incorporated AD8332-EVALZ Data Sheet, Rev. D ..................... 44
Incorporated AD8334-EVAL Data Sheet, Rev. 0 ........................ 49
Updated Outline Dimensions ........................................................ 55
Changes to Ordering Guide ........................................................... 57
4/06—Rev. D to Rev. E
Added AD8334 ................................................................... Universal
Changes to Figure 1 and Figure 2 .................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 7
Changes to Figure 7 through Figure 9 and Figure 12 ................. 12
Changes to Figure 13, Figure 14, Figure 16, and Figure 18 ....... 13
Changes to Figure 23 and Figure 24 ............................................. 14
Changes to Figure 25 through Figure 27 ...................................... 15
Changes to Figure 31 and Figure 33 through Figure 36 ............ 16
Changes to Figure 37 through Figure 42 ...................................... 17
Changes to Figure 43, Figure 44, and Figure 48 .......................... 18
Changes to Figure 49, Figure 50, and Figure 54 .......................... 19
Inserted Figure 56 and Figure 57 .................................................. 20
Inserted Figure 58, Figure 59, and Figure 61 ............................... 21
Changes to Figure 60 ...................................................................... 21
Inserted Figure 63 and Figure 65 .................................................. 22
Changes to Figure 64 ...................................................................... 22
Moved Measurement Considerations Section ............................ 23
Inserted Figure 67 and Figure 68 .................................................. 23
Inserted Figure 70 and Figure 71 .................................................. 24
Change to Figure 72 ........................................................................ 24
Changes to Figure 73 and Low Noise Amplifier Section ........... 25
Changes to Postamplifier Section ................................................. 28
Changes to Figure 80 ...................................................................... 29
Changes to LNA—External Components Section ...................... 30
Changes to Logic Inputs—ENB, MODE, and HILO Section ... 31
Changes to Output Decoupling and Overload Sections ............ 32
Changes to Layout, Grounding, and Bypassing Section ............ 33
Changes to Ultrasound TGC Application Section ..................... 34
Added High Density Quad Layout Section ................................. 34
Inserted Figure 94 ........................................................................... 38
Updated Outline Dimensions ........................................................ 39
Changes to Ordering Guide ........................................................... 40
3/06—Rev. C to Rev. D
Updated Format ................................................................. Universal
Changes to Features and General Description .............................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 6
Changes to Ordering Guide ........................................................... 34
11/03—Rev. B to Rev. C
Addition of New Part ......................................................... Universal
Changes to Figures ............................................................. Universal
Updated Outline Dimensions ........................................................ 32
5/03—Rev. A to Rev. B
Edits to Ordering Guide ................................................................. 32
Edits to Ultrasound TGC Application Section ........................... 25
Added Figure 71, Figure 72, and Figure 73.................................. 26
Updated Outline Dimensions ........................................................ 31
2/03—Rev. 0 to Rev. A
Edits to Ordering Guide ................................................................. 32
AD8331/AD8332/AD8334
Rev. G | Page 4 of 56
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating,
−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit1
LNA CHARACTERISTICS
Gain Single-ended input to differential output 19 dB
Input to output (single-ended) 13 dB
Input Voltage Range AC-coupled ±275 mV
Input Resistance RIZ = 280 Ω 50 Ω
R
IZ = 412 Ω 75 Ω
R
IZ = 562 Ω 100 Ω
R
IZ = 1.13 kΩ 200 Ω
R
IZ = ∞ 6
Input Capacitance 13 pF
Output Impedance Single-ended, either output 5 Ω
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 130 MHz
Slew Rate 650 V/μs
Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.74 nV/√Hz
Input Current Noise RIZ = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz
Noise Figure f = 10 MHz, LOP output
Active Termination Match RS = RIN = 50 Ω 3.7 dB
Unterminated RS = 50 Ω, RIZ = ∞ 2.5 dB
Harmonic Distortion at LOP1 or LOP2 VOUT = 0.5 V p-p, single-ended, f = 10 MHz
HD2 −56 dBc
HD3 −70 dBc
Output Short-Circuit Current Pin LON, Pin LOP 165 mA
LNA AND VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p
AD8331 120 MHz
AD8332, AD8334 100 MHz
−3 dB Large Signal Bandwidth VOUT = 2 V p-p
AD8331 110 MHz
AD8332, AD8334 90 MHz
Slew Rate
AD8331 LO gain 300 V/μs
HI gain 1200 V/μs
AD8332, AD8334 LO gain 275 V/μs
HI gain 1100 V/μs
Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.82 nV/√Hz
Noise Figure VGAIN = 1.0 V
Active Termination Match RS = RIN = 50 Ω, f = 10 MHz, measured 4.15 dB
R
S = RIN = 200 Ω, f = 5 MHz, simulated 2.0 dB
Unterminated RS = 50 Ω, RIZ = ∞, f = 10 MHz, measured 2.5 dB
R
S = 200 Ω, RIZ = ∞, f = 5 MHz, simulated 1.0 dB
Output-Referred Noise
AD8331 VGAIN = 0.5 V, LO gain 48 nV/√Hz
V
GAIN = 0.5 V, HI gain 178 nV/√Hz
AD8332, AD8334 VGAIN = 0.5 V, LO gain 40 nV/√Hz
V
GAIN = 0.5 V, HI gain 150 nV/√Hz
Output Impedance, Postamplifier DC to 1 MHz 1 Ω
AD8331/AD8332/AD8334
Rev. G | Page 5 of 56
Parameter Test Conditions/Comments Min Typ Max Unit1
Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V
Differential 4.5 V p-p
Output Offset Voltage
AD8331 Differential, VGAIN = 0.5 V −50 ±5 +50 mV
Common mode −125 −25 +100 mV
AD8332, AD8334 Differential, 0.05 V ≤ VGAIN ≤ 1.0 V −20 ±5 +20 mV
Common mode −125 –25 +100 mV
Output Short-Circuit Current 45 mA
Harmonic Distortion VGAIN = 0.5 V, VOUT = 1 V p-p, HI gain
AD8331
HD2 f = 1 MHz −88 dBc
HD3 −85 dBc
HD2 f = 10 MHz −68 dBc
HD3 −65 dBc
AD8332, AD8334
HD2 f = 1 MHz −82 dBc
HD3 −85 dBc
HD2 f = 10 MHz −62 dBc
HD3 −66 dBc
Input 1 dB Compression Point VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz to 10 MHz 1 dBm
Two-Tone Intermodulation Distortion (IMD3)
AD8331 VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz −80 dBc
V
GAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz −72 dBc
AD8332, AD8334 VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz −78 dBc
V
GAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz −74 dBc
Output Third-Order Intercept
AD8331 VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 38 dBm
V
GAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 33 dBm
AD8332, AD8334 VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 35 dBm
V
GAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 32 dBm
Channel-to-Channel Crosstalk (AD8332, AD8334) VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz −98 dB
Overload Recovery VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns
Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns
ACCURACY
Absolute Gain Error2 0.05 V < VGAIN < 0.10 V −1 +0.5 +2 dB
0.10 V < VGAIN < 0.95 V −1 ±0.3 +1 dB
0.95 V < VGAIN < 1.0 V −2 −1 +1 dB
Gain Law Conformance3 0.1 V < VGAIN < 0.95 V ±0.2 dB
Channel-to-Channel Gain Matching 0.1 V < VGAIN < 0.95 V ±0.1 dB
GAIN CONTROL INTERFACE (Pin GAIN)
Gain Scaling Factor 0.10 V < VGAIN < 0.95 V 48.5 50 51.5 dB/V
Gain Range LO gain −4.5 to +43.5 dB
HI gain 7.5 to 55.5 dB
Input Voltage (VGAIN) Range 0 to 1.0 V
Input Impedance 10
Response Time 48 dB gain change to 90% full scale 500 ns
COMMON-MODE INTERFACE (PIN VCMx)
Input Resistance4 Current limited to ±1 mA 30 Ω
Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV
Voltage Range VOUT = 2.0 V p-p 1.5 to 3.5 V
AD8331/AD8332/AD8334
Rev. G | Page 6 of 56
Parameter Test Conditions/Comments Min Typ Max Unit1
ENABLE INTERFACE
(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Input Resistance Pin ENB 25
Pin ENBL 40
Pin ENBV 70
Power-Up Response Time VINH = 30 mV p-p 300 μs
V
INH = 150 mV p-p 4 ms
HILO GAIN RANGE INTERFACE (PIN HILO)
Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50
OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR
LO GAIN)
Accuracy
HILO = LO RCLMP = 2.74 kΩ, VOUT = 1 V p-p (clamped) ±50 mV
HILO = HI RCLMP = 2.21 kΩ, VOUT = 1 V p-p (clamped) ±75 mV
MODE INTERFACE (PIN MODE)
Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200
POWER SUPPLY (PIN VPS1, PIN VPS2,
PIN VPSV, PIN VPSL, PIN VPOS)
Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel
AD8331 20 25 mA
AD8332 22 27.5 32 mA
AD8334 24 29.5 34
Power Dissipation per Channel No signal
AD8331 125 mW
AD8332, AD8334 138 mW
Power-Down Current VGA and LNA disabled
AD8331 50 240 400 μA
AD8332 50 300 600 μA
AD8334 50 600 1200 μA
LNA Current
AD8331 (ENBL) Each channel 7.5 11 15 mA
AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA
VGA Current
AD8331 (ENBV) 7.5 14 20 mA
AD8332, AD8334 (ENBV) 7.5 17 20 mA
PSRR VGAIN = 0 V, f = 100 kHz −68 dB
1 All dBm values are referred to 50 Ω.
2 The absolute gain refers to the theoretical gain expression in Equation 1.
3 Best-fit to linear-in-dB curve.
4 The current is limited to ±1 mA typical.
AD8331/AD8332/AD8334
Rev. G | Page 7 of 56
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V
Input Voltage (INHx) VS + 200 mV
ENB, ENBL, ENBV, HILO Voltage VS + 200 mV
GAIN Voltage 2.5 V
Power Dissipation
RU Package1 (AD8332) 0.96 W
CP-32 Package (AD8332) 1.97 W
RQ Package1 (AD8331) 0.78 W
CP-64 Package (AD8334) 0.91 W
Temperature
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
θJA
RU Package1 (AD8332) 68°C/W
CP-32 Package22 (AD8332) 33°C/W
RQ Package1 (AD8331) 83°C/W
CP-64 Package3 (AD8334) 24.2°C/W
1 4-layer JEDEC board (2S2P).
2 Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer
board J-STD-51-9.
3 Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, 4-layer
board J-STD-51-9.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8331/AD8332/AD8334
Rev. G | Page 8 of 56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03199-003
MODE
VIP
GAIN
VIN
LOP
COML
LMD
LON
VPSL
INH
1
2
3
4
5
6
7
8
9
10
RCLMP
COMM
VOH
ENBV
VCM
VPOS
VOL
HILO
ENBL
COMM
20
19
18
17
16
15
14
13
12
11
AD8331
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 3. 20-Lead QSOP Pin Configuration (AD8331)
Table 3. 20-Lead QSOP Pin Function Description (AD8331)
Pin No. Mnemonic Description
1 LMD LNA Midsupply Bypass Pin; Connect a Capacitor for Midsupply HF Bypass
2 INH LNA Input
3 VPSL LNA 5 V Supply
4 LON LNA Inverting Output
5 LOP LNA Noninverting Output
6 COML LNA Ground
7 VIP VGA Noninverting Input
8 VIN VGA Inverting Input
9 MODE Gain Slope Logic Input
10 GAIN Gain Control Voltage
11 VCM Common-Mode Voltage
12 RCLMP Output Clamping Level
13 HILO Gain Range Select (HI or LO)
14 VPOS VGA 5 V Supply
15 VOH Noninverting VGA Output
16 VOL Inverting VGA Output
17 COMM VGA Ground
18 ENBV VGA Enable
19 ENBL LNA Enable
20 COMM VGA Ground
AD8331/AD8332/AD8334
Rev. G | Page 9 of 56
03199-004
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AD8332
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)
03199-005
LOP2
COM2
VIP2
VIN2
VCM2
MODE
GAIN
RCLMP
LOP1
COM1
VIP1
VIN1
VCM1
HILO
ENBL
ENBV
LMD2
LON2
NC = NO CONNECT
VPS2
INH2
8
7
6
5
1
4
3
2
29303132 28 252627
LMD1
LON1
VPS1
INH1
14139121110
COMM
VOL2
VOH2
15 16
20
17
18
19
VOH1
VOL1
21
22
23
24
NC
VPSV
COMM
AD8332
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)
Table 4. 28-Lead TSSOP Pin Function Description (AD8332)
Pin No. Mnemonic Description
1 LMD2 CH 2 LNA Midsupply Pin; Connect a
Capacitor for Midsupply HF Bypass
2 INH2 CH2 LNA Input
3 VPS2 CH2 Supply LNA 5 V
4 LON2 CH2 LNA Inverting Output
5 LOP2 CH2 LNA Noninverting Output
6 COM2 CH2 LNA Ground
7 VIP2 CH2 VGA Noninverting Input
8 VIN2 CH2 VGA Inverting Input
9 VCM2 CH2 Common-Mode Voltage
10 GAIN Gain Control Voltage
11 RCLMP Output Clamping Resistor
12 VOH2 CH2 Noninverting VGA Output
13 VOL2 CH2 Inverting VGA Output
14 COMM VGA Ground (Both Channels)
15 VPSV VGA Supply 5 V (Both Channels)
16 VOL1 CH1 Inverting VGA Output
17 VOH1 CH1 Noninverting VGA Output
18 ENB Enable—VGA/LNA
19 HILO VGA Gain Range Select (HI or LO)
20 VCM1 CH1 Common-Mode Voltage
21 VIN1 CH1 VGA Inverting Input
22 VIP1 CH1 VGA Noninverting Input
23 COM1 CH1 LNA Ground
24 LOP1 CH1 LNA Noninverting Output
25 LON1 CH1 LNA Inverting Output
26 VPS1 CH1 LNA Supply 5 V
27 INH1 CH1 LNA Input
28 LMD1 CH 1 LNA Midsupply Pin; Connect a
Capacitor for Midsupply HF Bypass
Table 5. 32-Lead LFCSP Pin Function Description (AD8332)
Pin No. Mnemonic Description
1 LON1 CH1 LNA Inverting Output
2 VPS1 CH1 LNA Supply 5 V
3 INH1 CH1 LNA Input
4 LMD1 CH 1 LNA Midsupply Pin; Connect a
Capacitor for Midsupply HF Bypass
5 LMD2 CH 2 LNA Midsupply Pin; Connect a
Capacitor for Midsupply HF Bypass
6 INH2 CH2 LNA Input
7 VPS2 CH2 LNA Supply 5 V
8 LON2 CH2 LNA Inverting Output
9 LOP2 CH2 LNA Noninverting Output
10 COM2 CH2 LNA Ground
11 VIP2 CH2 VGA Noninverting Input
12 VIN2 CH2 VGA Inverting Input
13 VCM2 CH2 Common-Mode Voltage
14 MODE Gain Slope Logic Input
15 GAIN Gain Control Voltage
16 RCLMP Output Clamping Level Input
17 COMM VGA Ground
18 VOH2 CH2 Noninverting VGA Output
19 VOL2 CH2 Inverting VGA Output
20 NC No Connect
21 VPSV VGA Supply 5 V
22 VOL1 CH1 Inverting VGA Output
23 VOH1 CH1 Noninverting VGA Output
24 COMM VGA Ground
25 ENBV VGA Enable
26 ENBL LNA Enable
27 HILO VGA Gain Range Select (HI or LO)
28 VCM1 CH1 Common-Mode Voltage
29 VIN1 CH1 VGA Inverting Input
30 VIP1 CH1 VGA Noninverting Input
31 COM1 CH1 LNA Ground
32 LOP1 CH1 LNA Noninverting Output
AD8331/AD8332/AD8334
Rev. G | Page 10 of 56
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COM3
COM4
INH4
LMD4
NC
LON4
LOP4
VIP4
VIN4
VPS4
GAIN34
CLMP34
HILO
VCM4
VCM3
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
COM2
COM1
INH1
LMD1
NC
LON1
LOP1
VIP1
VIN1
VPS1
GAIN12
CLMP12
EN12
EN34
VCM1
VCM2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
INH2
LMD2
NC
LON2
LOP2
VIP2
VIN2
VPS2
VPS3
VIN3
VIP3
LOP3
LON3
NC
LMD3
INH3
COM12
VOH1
VOL1
VPS12
VOL2
VOH2
COM12
MODE
NC
COM34
VOH3
VOL3
VPS34
VOL4
VOH4
COM34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD8334
TOP VIEW
(Not to Scale)
03199-006
NOTES
1. THE EXPOSED PADDLE MUST BE
SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT
DISSIPATION, NOISE, AND
MECHANICAL STRENGTH BENEFITS.
2. NC = NO CONNECT.
Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)
Table 6. 64-Lead LFCSP Pin Function Description (AD8334)
Pin No. Mnemonic Description
1 INH2 CH2 LNA Input.
2 LMD2 CH 2 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass.
3 NC Not Connected.
4 LON2 CH2 LNA Feedback Output (for RIZ).
5 LOP2 CH2 LNA Output.
6 VIP2 CH2 VGA Positive Input.
7 VIN2 CH2 VGA Negative Input.
8 VPS2 CH2 LNA Supply 5 V.
9 VPS3 CH3 LNA Supply 5 V.
10 VIN3 CH3 VGA Negative Input.
11 VIP3 CH3 VGA Positive Input.
12 LOP3 CH3 LNA Positive Output.
13 LON3 CH3 LNA Feedback Output (for RIZ).
14 NC Not Connected.
15 LMD3 CH 3 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass.
16 INH3 CH3 LNA Input.
17 COM3 CH3 LNA Ground.
18 COM4 CH4 LNA Ground.
19 INH4 CH4 LNA Input.
20 LMD4 CH 4 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass.
21 NC Not Connected.
22 LON4 CH4 LNA Feedback Output (for RIZ).
23 LOP4 CH4 LNA Positive Output.
24 VIP4 CH4 VGA Positive Input.
25 VIN4 CH4 VGA Negative Input.
26 VPS4 CH4 LNA Supply 5 V.
AD8331/AD8332/AD8334
Rev. G | Page 11 of 56
Pin No. Mnemonic Description
27 GAIN34 Gain Control Voltage for CH3 and CH4.
28 CLMP34 Output Clamping Level Input for CH3 and CH4.
29 HILO Gain Select for Postamp 0 dB or 12 dB.
30 VCM4 CH4 Common-Mode Voltage—AC Bypass.
31 VCM3 CH3 Common-Mode Voltage—AC Bypass.
32 NC No Connect.
33 COM34 VGA Ground CH3 and CH4.
34 VOH4 CH4 Positive VGA Output.
35 VOL4 CH4 Negative VGA Output.
36 VPS34 VGA Supply 5 V CH3 and CH4.
37 VOL3 CH3 Negative VGA Output.
38 VOH3 CH3 Positive VGA Output.
39 COM34 VGA Ground CH3 and CH4.
40 NC No Connect.
41 MODE Gain Control Slope, Logic Input, 0 = Positive.
42 COM12 VGA Ground CH1 and CH2.
43 VOH2 CH2 Positive VGA Output.
44 VOL2 CH2 Negative VGA Output.
45 VPS12 CH2 VGA Supply 5 V CH1 and CH2.
46 VOL1 CH1 Negative VGA Output.
47 VOH1 CH1 Positive VGA Output.
48 COM12 VGA Ground CH1 and CH2.
49 VCM2 CH2 Common-Mode Voltage—AC Bypass.
50 VCM1 CH1 Common-Mode Voltage—AC Bypass.
51 EN34 Shared LNA/VGA Enable CH3 and CH4.
52 EN12 Shared LNA/VGA Enable CH1 and CH2.
53 CLMP12 Output Clamping Level Input CH1 and CH2.
54 GAIN12 Gain Control Voltage CH1 and CH2.
55 VPS1 CH1 LNA Supply 5 V.
56 VIN1 CH1 VGA Negative Input.
57 VIP1 CH1 VGA Positive Input.
58 LOP1 CH1 LNA Positive Output.
59 LON1 CH1 LNA Feedback Output (for RIZ).
60 NC Not Connected.
61 LMD1 CH 1 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass.
62 INH1 CH1 LNA Input.
63 COM1 CH1 LNA Ground.
64 COM2 CH2 LNA Ground.
EPAD The exposed paddle must be soldered to the PCB ground to ensure proper heat dissipation,
noise, and mechanical strength benefits.
AD8331/AD8332/AD8334
Rev. G | Page 12 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating,
−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
60
50
40
30
20
10
0
–10
0 0.2 0.4 0.6 0.8 1.0 1.1
GAIN (dB)
V
GAIN
(V)
03199-007
HILO = HI
HILO = LO
ASCENDING GAIN MODE
DESCENDING GAIN MODE
(WHERE AVAILABLE)
Figure 7. Gain vs. VGAIN and MODE (MODE Available on RU Package)
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 0.2 0.4 0.6 0.8 1.0 1.1
GAIN ERROR (dB)
V
GAIN
(V)
03199-008
+25°C
–40°C
+85°C
Figure 8. Absolute Gain Error vs. VGAIN at Three Temperatures
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 0.2 0.4 0.6 0.8 1.0 1.1
GAIN ERROR (dB)
V
GAIN
(V)
03199-009
1MHz
30MHz
10MHz
70MHz
50MHz
Figure 9. Absolute Gain Error vs. VGAIN at Various Frequencies
50
40
30
20
10
0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
PERCENT OF UNITS (%)
GAIN ERROR (dB)
03199-010
SAMPLE SIZE = 80 UNITS
V
GAIN
= 0.5V
Figure 10. Gain Error Histogram
03199-011
25
V
GAIN
= 0.7V
0
5
15
20
25
10
0
5
10
20
15
–0.17
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
0.19
0.21
PERCENT OF UNITS (%)
CHANNEL TO CHANNEL GAIN MATCH (dB)
SAMPLE SIZE = 50 UNITS
V
GAIN
= 0.2V
Figure 11. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
50
40
30
20
10
0
–20
–10
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-012
V
GAIN
= 1V
V
GAIN
= 0.8V
V
GAIN
= 0.6V
V
GAIN
= 0.4V
V
GAIN
= 0.2V
V
GAIN
= 0V
Figure 12. Frequency Response for Various Values of VGAIN
AD8331/AD8332/AD8334
Rev. G | Page 13 of 56
60
50
40
30
20
10
0
–10
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-013
V
GAIN
= 1V
V
GAIN
= 0.8V
V
GAIN
= 0.6V
V
GAIN
= 0.4V
V
GAIN
= 0.2V
V
GAIN
= 0V
Figure 13. Frequency Response for Various Values of VGAIN, HILO = HI
30
20
–30
–20
–10
0
10
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-014
R
IN
= R
S
= 50
R
IN
= R
S
= 75
R
IN
= R
S
= 100
R
IN
= R
S
= 200
R
IN
= R
S
= 500
R
IN
= R
S
= 1k
V
GAIN
= 0.5V
Figure 14. Frequency Response for Various Matched Source Impedances
30
–30
–20
–10
0
10
20
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-015
V
GAIN
= 0.5V
R
IZ
=
Figure 15. Frequency Response, Unterminated LNA, RS = 50 Ω
0
–120
–100
–80
–60
–40
–20
100k 1M 10M 100M
CROSSTALK (dB)
FREQUENCY (Hz)
03199-016
V
OUT
= 1V p-p
V
GAIN
= 1.0V
V
GAIN
= 0.7V
V
GAIN
= 0.4V
AD8332
AD8334
Figure 16. Channel-to-Channel Crosstalk vs.
Frequency for Various Values of VGAIN
50
0
5
10
15
20
25
30
35
40
45
100k 1M 10M 100M
GROUP DELAY (ns)
FREQUENCY (Hz)
03199-017
0.1µF
COUPLING
1µF
COUPLING
Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling
03199-018
20
–20
–10
0
10
20
–20
–10
0
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
OFFSET VOLTAGE (mV)
VGAIN (V)
T = +85°C
T = +25°C
T = –40°C
T = +85°C
T = +25°C
T = –40°C
HI GAIN
LO GAIN
Figure 18. Representative Differential Output Offset Voltage vs.
VGAIN at Three Temperatures
AD8331/AD8332/AD8334
Rev. G | Page 14 of 56
03199-019
35
SAMPLE SIZE = 100
0.2V < V
GAIN
< 0.7V
0
5
10
15
20
25
30
49.6 50.550.450.350.250.150.049.949.849.7
% TOTAL
GAIN SCALING FACTOR
Figure 19. Gain Scaling Factor Histogram
03199-020
100
10
1
0.1
100k 100M10M1M
OUTPUT IMPEDANCE ()
FREQUENCY (Hz)
SINGLE ENDED, PIN VOH OR PIN VOL
RL =
Figure 20. Output Impedance vs. Frequency
03199-021
10k
1k
100
10
100k 100M10M1M
INPUT IMPEDANCE ()
FREQUENCY (Hz)
R
IZ
= 6.65k, C
SH
= 0pF
R
IZ
= 3.01k, C
SH
= 0pF
R
IZ
= 1.1k, C
SH
= 1.2pF
R
IZ
= 549, C
SH
= 8.2pF
R
IZ
= 412, C
SH
= 12pF
R
IZ
= 270, C
SH
= 22pF
R
IZ
= , C
SH
= 0pF
Figure 21. LNA Input Impedance vs.
Frequency for Various Values of RIZ and CSH
R
IN
= 50,
R
IZ
= 270
R
IN
= 75,
R
IZ
= 412
R
IN
= 100,
R
IZ
= 549R
IN
= 200,
R
IZ
= 1.1k
R
IN
= 6k,
R
IZ
=
017
100j
50j
–50j
–100j
25j
–25j
f
= 100kHz
03199-022
Figure 22. Smith Chart, S11 vs. Frequency,
0.1 MHz to 200 MHz for Various Values of RIZ
20
15
10
5
0
–15
–10
–5
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-023
V
IN
= 10mV p-p R
IN
= 50
R
IN
= 75
R
IN
= 100
R
IN
= 200
R
IN
= 500
R
IN
= 1k
Figure 23. LNA Frequency Response, Single-Ended, for Various Values of RIN
20
15
10
5
0
–15
–10
–5
100k 1M 10M 100M 500M
GAIN (dB)
FREQUENCY (Hz)
03199-024
R
IZ
=
Figure 24. Frequency Response for Unterminated LNA, Single-Ended
AD8331/AD8332/AD8334
Rev. G | Page 15 of 56
500
400
300
200
100
0
0 0.2 0.4 0.6 0.8 1.0
OUTPUT-REFERRED NOISE (nV/ Hz)
V
GAIN
(V)
03199-025
HI GAIN
LO GAIN
AD8332
AD8334
AD8331
f
= 10MHz
Figure 25. Output-Referred Noise vs. VGAIN
2.5
2.0
1.5
1.0
0.5
100k 1M 10M 100M
FREQUENCY (Hz)
03199-026
RS = 0, RIZ = , VGAIN = 1V,
HILO = LO OR HI
INPUT-REFERRED NOISE (nV/ Hz)
Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency
100
10
1
0.1
0 0.2 0.4 0.6 0.8 1.0
V
GAIN
(V)
03199-027
R
S
= 0, R
IZ
=
,
HILO = LO OR HI, f = 10MHz
INPUT-REFERRED NOISE (nV/ Hz)
Figure 27. Short-Circuit, Input-Referred Noise vs. VGAIN
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
–50 –30 –10 10 30 50 70 90
INPUT-REFERRED NOISE (nV/ Hz)
TEMPERATURE (°C)
03199-028
R
S
= 0, R
IZ
=
,
V
GAIN
= 1V, f = 10MHz
Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature
10
1
0.1
1 10 100 1k
SOURCE RESISTANCE ()
03199-029
f = 5MHz, R
IZ
=
,
V
GAIN
= 1V
R
S
THERMAL NOISE
ALONE
INPUT-REFERRED NOISE (nV/ Hz)
Figure 29. Input-Referred Noise vs. RS
7
6
5
4
3
2
1
0
50 100 1k
NOISE FIGURE (dB)
SOURCE RESISTANCE ()
03199-030
INCLUDES NOISE OF VGA
R
IN
= 50
R
IN
= 75
R
IN
= 100
R
IN
= 200
R
IZ
=
SIMULATED RESULTS
Figure 30. Noise Figure vs. RS for Various Values of RIN
AD8331/AD8332/AD8334
Rev. G | Page 16 of 56
35
30
25
20
15
10
5
0
0 0.10.20.30.40.50.60.70.80.91.01.1
NOISE FIGURE (dB)
V
GAIN
(V)
03199-031
f = 10MHz, R
S
= 50PREAMP LIMITED
HILO = LO, R
IN
= 50
HILO = LO, R
IZ
=
HILO = HI, R
IN
= 50
HILO = HI, R
Iz
=
Figure 31. Noise Figure vs. VGAIN
30
25
20
15
10
5
0
10 15 20 25 30 35 40 45 50 55 60
NOISE FIGURE (dB)
GAIN (dB)
03199-032
f = 10MHz, R
S
= 50
HILO = LO, R
IN
= 50
HILO = LO, R
FB
=
HILO = HI, R
IN
= 50
HILO = HI, R
FB
=
Figure 32. Noise Figure vs. Gain
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
03199-113
G = 30dB
V
OUT
= 1Vp-p
HILO = HI, HD2
HILO = HI, HD3
HILO = LO, HD2
HILO = LO, HD3
Figure 33. Harmonic Distortion vs. Frequency
30
–40
–50
–60
–70
–80
–90
0 200018001600140012001000800600400200
HARMONIC DISTORTION (dBc)
R
LOAD
()
03199-034
HILO = LO, HD2
HILO = LO, HD3
HILO = HI, HD2
HILO = HI, HD3
f = 10MHz,
V
OUT
= 1V p-p
Figure 34. Harmonic Distortion vs. RLOAD
40
–50
–60
–70
–80
–90
0 10203040
HARMONIC DISTORTION (dBc)
C
LOAD
(pF)
03199-035
50
f = 10MHz,
V
OUT
= 1V p-p
HILO = LO, HD2
HILO = LO, HD3
HILO = HI, HD2
HILO = HI, HD3
Figure 35. Harmonic Distortion vs. CLOAD
20
–40
–60
–80
–100
01234
HARMONIC DISTORTION (dBc)
V
OUT
(V p-p)
03199-036
f = 10MHz,
GAIN = 30dB
HILO = LO, HD2
HILO = LO, HD3
HILO = HI, HD2 HILO = HI, HD3
Figure 36. Harmonic Distortion vs. Differential Output Voltage
AD8331/AD8332/AD8334
Rev. G | Page 17 of 56
0
–20
–40
–60
–80
–120
–100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DISTORTION (dBc)
V
GAIN
(V)
03199-037
V
OUT
= 1V p-p
INPUT RANGE
LIMITED WHEN
HILO = LO
HILO = LO, HD2
HILO = LO, HD3
HILO = HI, HD2
HILO = HI, HD3
Figure 37. Harmonic Distortion vs. VGAIN, f = 1 MHz
0
–20
–40
–60
–80
–120
–100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DISTORTION (dBc)
V
GAIN
(V)
03199-038
V
OUT
= 1V p-p
INPUT RANGE
LIMITED WHEN
HILO = LO
HILO = LO, HD2
HILO = LO, HD3
HILO = HI, HD2
HILO = HI, HD3
Figure 38. Harmonic Distortion vs. VGAIN, f = 10 MHz
10
–10
0
–20
–30
–40
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
IP1dB COMPRESSION (dBm)
V
GAIN
(V)
03199-039
f = 10MHz HILO = HI HILO = LO
Figure 39. IP1dB Compression vs. VGAIN
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
1M 10M 100M
IMD3 (dBc)
FREQUENCY (Hz)
03199-040
V
OUT
= 1V p-p COMPOSITE (
f
1
+
f
2
)
G = 30dB
HILO = LO
HILO = HI
Figure 40. IMD3 vs. Frequency
40
35
30
25
20
15
10
5
0
010.90.80.70.60.50.40.30.20.1
OUTPUT IP3 (dBm)
V
GAIN
(V)
03199-041
.0
V
OUT
= 1V p-p COMPOSITE (
f
1
+
f
2
)
1MHz HILO = HI
10MHz HILO = HI
1MHz HILO = LO
10MHz HILO = LO
Figure 41. Output Third-Order Intercept (IP3) vs. VGAIN
2mV
50mV 10ns
100
90
10
0
0
3199-042
Figure 42. Small Signal Pulse Response, G = 30 dB,
Top: Input, Bottom: Output Voltage, HILO = HI or LO
AD8331/AD8332/AD8334
Rev. G | Page 18 of 56
20mV
500mV 10ns
100
90
10
0
0
3199-043
Figure 43. Large Signal Pulse Response, G = 30 dB,
HILO = HI or LO, Top: Input, Bottom: Output Voltage
2
–2
–1
0
1
–50 50403020100–10–20–30–40
V
OUT
(V)
TIME (ns)
03199-044
G = 30dB
INPUT
INPUT IS NOT TO SCALE
C
L
= 0pF
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
Figure 44. Large Signal Pulse Response for Various Capacitive Loads,
CL = 0 pF, 10 pF, 20 pF, 50 pF
500mV
200mV 400ns
0
3199-045
Figure 45. Pin GAIN Transient Response,
Top: VGAIN, Bottom: Output Voltage
5.0
4.0
3.0
2.0
1.0
4.5
3.5
2.5
1.5
0.5
0
0545403530252015105
V
OUT
(V p-p)
R
CLMP
(k)
03199-046
0
HILO = HI
HILO = LO
Figure 46. Clamp Level vs. RCLMP
4
–4
–3
–2
–1
0
1
2
3
3020100 1020304050607080
V
OUT
(V)
TIME (ns)
03199-047
G = 40dB
INPUT
R
CLMP
= 48.1k
R
CLMP
= 16.5k
R
CLMP
= 7.15k
R
CLMP
= 2.67k
Figure 47. Clamp Level Pulse Response for Four Values of RCLMP
200mV
100ns
100
90
10
0
0
3199-048
Figure 48. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst,
VGAIN = 0.27 V VGA Output Shown
AD8331/AD8332/AD8334
Rev. G | Page 19 of 56
1V
100ns
100
90
10
0
0
3199-049
Figure 49. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst,
VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
1V
100ns
100
90
10
0
0
3199-050
Figure 50. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst,
VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
2V
200mV 1ms
0
3199-051
Figure 51. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
2V
1V 1ms
0
3199-052
Figure 52. Enable Response, Large Signal,
Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
0
–10
–20
–30
–40
–50
–60
–70
–80
100k 1M 10M 100M
PSRR (dB)
FREQUENCY (Hz)
03199-053
VPS1, V
GAIN
= 0.5V
VPSV, V
GAIN
= 0.5V
VPS1, V
GAIN
= 0V
Figure 53. PSRR vs. Frequency (No Bypass Capacitor)
140
130
120
110
100
90
80
70
60
50
40
30
20
–40 100806040200–20
QUIESCENT SUPPLY CURRENT (mA)
TEMPERATURE (°C)
03199-054
V
GAIN
= 0.5V
AD8334
AD8332
AD8331
Figure 54. Quiescent Supply Current vs. Temperature
AD8331/AD8332/AD8334
Rev. G | Page 20 of 56
TEST CIRCUITS
MEASUREMENT CONSIDERATIONS
Figure 55 through Figure 68 show typical measurement
configurations and proper interface values for measurements
with 50 Ω conditions.
Short-circuit input noise measurements are made as shown in
Figure 62. The input-referred noise level is determined by
dividing the output noise by the numerical gain between Point A
and Point B and accounting for the noise floor of the spectrum
analyzer. The gain should be measured at each frequency of
interest and with low signal levels because a 50 Ω load is driven
directly. The generator is removed when noise measurements
are made.
0
3199-055
LMD
18nF
22pF
FB*
120nH
*
FERRITE BEAD
INOUT
0.1µF
DUT
NETWORK ANALYZE
R
0.1µF
28
237
28
1:1
5050
270
INH
237
0.1µF
0.1µF
Figure 55. Test Circuit—Gain and Bandwidth Measurements
10k
10k
03199-056
LMD
18nF
22pF
FB*
120nH
*FERRITE BEAD
INOUT
0.1µF VGN
DUT
NETWORK ANALYZER
0.1µF
28
237
28
1:1
5050
INH
237
0.1µF
0.1µF
Figure 56. Test Circuit—Frequency Response for Various Matched Source Impedances
03199-057
LMD
22pF
FB*
120nH
*FERRITE BEAD
INOUT
0.1µF VGN
DUT
NETWORK ANALYZER
0.1µF
28
237
28
1:1
5050
INH
237
0.1µF
0.1µF
Figure 57. Test Circuit—Frequency Response for Unterminated LNA, RS = 50 Ω
AD8331/AD8332/AD8334
Rev. G | Page 21 of 56
03199-058
18nF
22pF
INOUT
NETWORK ANALYZER
28
237
28
1:1
5050
0.1µF
OR
1µF
237
10k
VGA
FB*
120nH
*FERRITE BEAD
LMD
0.1µF
LNA
0.1µF
OR
1µF
INH
0.1µF
OR
1µF 0.1µF
0.1µF
Figure 58. Test Circuit—Group Delay vs. Frequency for Two Values of AC Coupling
03199-059
18nF
22pF
28
237
28
0.1µF
237
50
1:1
OUT
NETWORK
ANALYZER
50
270
FB*
120nH
*FERRITE BEAD
LMD
0.1µF
DUT
0.1µF
0.1µF
INH
Figure 59. Test Circuit—LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats
03199-060
22pF
28
237
28
1:1
0.1µF
0.1µF
237
INOUT
NETWORK ANALYZER
5050
VGALNA
FB*
120nH
*FERRITE BEAD
LMD
0.1µF 0.1µF
INH
0.1µF
0.1µF
0.1µF
Figure 60. Test Circuit—Frequency Response for Unterminated LNA, Single-Ended
03199-061
18nF
22pF
28
237
28
0.1µF INH
2371:1 IN
NETWOR
K
ANALYZER
50
270
FB*
120nH
FERRITE BEAD LMD
0.1µF
DUT
0.1µF
0.1µF
Figure 61. Test Circuit—Short-Circuit, Input-Referred Noise
AD8331/AD8332/AD8334
Rev. G | Page 22 of 56
03199-062
22pF
SIGNAL GENERATOR
TO MEASURE GAIN
DISCONNECT FOR
NOISE MEASUREMENT
GAIN
1:1
0.1µF
IN
SPECTRUM
ANALYZER
50
B
A
49.9
501
FERRITE
BEAD
120nH INH
LMD
0.1µF 0.1µF
0.1µF
DUT
Figure 62. Test Circuit—Noise Figure
03199-063
22pF
AD8332
1:1
0.1µF IN
SPECTRUM
ANALYZER
50
50
SIGNAL
GENERATOR
–6dB
–6dB
28
28
1k
1k
18nF 270
LPF
INH
LMD
0.1µF 0.1µF
0.1µF
DUT
Figure 63. Test Circuit—Harmonic Distortion vs. Load Resistance
03199-114
22pF
AD8332
1:1
0.1µF
IN
SPECTRUM
ANALYZER
50
50
SIGNAL
GENERATOR
–6dB
–6dB
28
28
18nF 270
LPF
INH
LMD
0.1µF 0.1µF
0.1µF
DUT
237
237
Figure 64. Test Circuit—Harmonic Distortion vs. Load Capacitance
03199-065
INH
0.1µF
SPECTRUM
ANALYZER
INPUT
50
22pF
–6dB
SIGNAL
GENERATORS
COMBINER
–6dB
50
–6dB
50
–6dB
+22dB
+22dB
FB*
120nH
*FERRITE BEAD
18nF
28
237
237
28
274
LMD
0.1µF
DUT
0.1µF
0.1µF
1:1
Figure 65.Test Circuit—IMD3 vs. Frequency
AD8331/AD8332/AD8334
Rev. G | Page 23 of 56
0
3199-066
INH
0.1µF
OSCILLOSCOPE
IN
50
22pF
50
FB*
120nH
*FERRITE BEAD
18nF
28
237
28
237
1:1
270
LMD
0.1µF
DUT
0.1µF
0.1µF
Figure 66. Test Circuit—Pulse Response Measurements
03199-067
INH
DIFF
PROBE
0.1µF
OSCILLOSCOP
E
CH1 CH2
22pF
18nF 270
RF
SIGNAL
GENERATOR
TO PIN GAIN
OR PIN ENxx
50
50
PULSE
GENERATOR
9.5dB
FB*
120nH
*FERRITE BEAD
255
255
LMD
0.1µF
DUT
0.1µF
0.1µF
Figure 67. Test Circuit—Gain and Enable Transient Response
03199-068
INH
DIFF
PROBE
0.1µF
22pF
RF
SIGNAL
GENERATOR
50
PROBE
POWER
50
NETWORK
ANALYZER
INOUT 50
FB*
120nH
*FERRITE BEAD
18nF 270
255
255
LMD
0.1µF
0.1µF
0.1µF
TO POWER
PINS
DUT
Figure 68. Test Circuit—PSRR vs. Frequency
AD8331/AD8332/AD8334
Rev. G | Page 24 of 56
THEORY OF OPERATION
03199-071
CLAMP
LNA 2
LNA 1
INH1
LON1 LOP1
V
IP1
V
IN1 EN12
INH2
LON2
LOP2
VIP2
PA2
ATTENUATOR
–48dB
+
VGA BIAS AND
INTERPOLATOR
+ATTENUATOR
–48dB
GAIN UP/
DOWN
VMID1 CLAMP
GAIN
INT
VOH1
CLMP12
VOL1
VOL2
GAIN12
HILO
VOH2
VIN2
MODE
V
CM1
VMID2
VMID3
VCM2
VCM3
VMID4
LNA 4
LNA 3
INH3
LON3
LOP3
LMD3
LMD4
INH4
VCM
BIAS
VCM
BIAS
PA3
PA4
ATTENUATOR
–48dB
+
VGA BIAS AND
INTERPOLATOR
+ATTENUATOR
–48dB
GAIN
INT
VOH3
VOL3
VOL4
GAIN34
VOH4
CLMP34
21dB
21dB
21dB
21dB
VIP3
VIN3
VCM4EN34VIN4VIP4LON4 LOP4
AD8334
LMD1
LMD2
PA1
OVERVIEW
The AD8331/AD8332/AD8334 operate in the same way.
Figure 69, Figure 70, and Figure 71 are functional block
diagrams of the three devices
03199-069
VOL
VOH
LNA ATTENUATOR
–48dB
+
INH
V
IN
V
IPLOPLON
ENBV GAIN
AD8331
+
MODE
HILO
3.5dB/
15.5dB
RCLMP
V
MID
V
CM
VGA BIAS AND
INTERPOLATOR
ENBL
GAIN INT
VCM
BIAS
PA21dB
CLAMP
LMD
Figure 69. AD8331 Functional Block Diagram
03199-070
LNA 2
LNA 1
+19dB
INH1
LON1 LOP1
LON2 LOP2
VIP1
VIP2
VIN1
VIN2
LMD1
LMD2
INH2
LNA V
MID
PA1
PA2
ATTENUATOR
–48dB
+
VGA BIAS AND
INTERPOLATOR
+ATTENUATOR
–48dB
3.5dB/
15.5dB
ENB
GAIN
INT
VOH1
VOL1
VOH2
VOL2
GAIN
RCLMP
HILO
AD8332
V
MID
VCM1
V
MID
VCM2
CLAMP
21dB
21dB
Figure 71. AD8334 Functional Block Diagram
Each channel contains an LNA that provides user-adjustable input
impedance termination, a differential X-AMP VGA, and a pro-
grammable gain postamp with adjustable output voltage limiting.
Figure 72 shows a simplified block diagram with external
components.
Figure 70. AD8332 Functional Block Diagram
03199-072
LNA
VOL
VOH
HILO
INH
LMD LOP
LON
PREAMPLIFIER
19dB
POSTAMP
3.5dB/15.5dB
SIGNAL PATH
BIAS AND
INTERPOLATOR
VIN
VIP
RCLMP
21dB
VCM
V
MID
CLAMP
48dB
ATTENUATOR
GAIN
INTERFACE
GAIN
VCM
BIAS
Figure 72. Simplified Block Diagram
AD8331/AD8332/AD8334
Rev. G | Page 25 of 56
The linear-in-dB, gain control interface is trimmed for slope and
absolute accuracy. The gain range is +48 dB, extending from
−4.5 dB to +43.5 dB in LO gain and +7.5 dB to +55.5 dB in HI
gain mode. The slope of the gain control interface is 50 dB/V,
and the gain control range is 40 mV to 1 V. Equation 1 and
Equation 2 are the expressions for gain.
GAIN (dB) = 50 (dB/V) × VGAIN − 6.5 dB, (HILO = LO) (1)
or
GAIN (dB) = 50 (dB/V) × VGAIN + 5.5 dB, (HILO = HI) (2)
The ideal gain characteristics are shown in Figure 73.
60
50
40
30
20
10
0
–10
0 0.2 0.4 0.6 0.8 1.0 1.1
GAIN (dB)
V
GAIN
(V)
03199-073
HILO = HI
HILO = LO
ASCENDING GAIN MODE
DESCENDING GAIN MODE
(WHERE AVAILABLE)
Figure 73. Ideal Gain Control Characteristics
The gain slope is negative with MODE pulled high (where
available), as follows:
GAIN (dB) = −50 (dB/V) × VGAIN + 45.5 dB, (HILO = LO) (3)
or
GAIN (dB) = −50 (dB/V) × VGAIN + 57.5 dB, (HILO = HI) (4)
The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. If only one output is used, the gain
is 13 dB. The inverting output is used for active input impedance
termination. Each of the LNA outputs is capacitively coupled to
a VGA input. The VGA consists of an attenuator with a range of
48 dB followed by an amplifier with 21 dB of gain for a net gain
range of −27 dB to +21 dB. The X-AMP, gain interpolation
technique results in low gain error and uniform bandwidth, and
differential signal paths minimize distortion.
The final stage is a logic programmable amplifier with gains of
3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for
12-bit and 10-bit ADC applications, in terms of output-referred
noise and absolute gain range. Output voltage limiting can be
programmed by the user.
LOW NOISE AMPLIFIER (LNA)
Good noise performance in the AD8331/AD8332/AD8334
relies on a proprietary ultralow noise preamplifier at the beginning
of the signal chain, which minimizes the noise contribution in the
following VGA. Active impedance control optimizes noise per-
formance for applications that benefit from input matching.
A simplified schematic of the LNA is shown in Figure 74. INH
is capacitively coupled to the source. A bias generator establishes dc
input bias voltages of 3.25 V and centers the output common-
mode levels at 2.5 V. A capacitor CLMD (can be the same value as
the input coupling capacitor CINH) is connected from the LMD
pin to ground to decouple the LMD bus. The LMD pin is not
useable for configuring the LNA as a differential input amplifier.
03199-074
R
S
C
INH
C
SH
I
0
I
0
I
0
I
0
Q1 Q2
VPOS
VCM
BIAS
LOP
INH 3.25V 3.25V
–a –a
LON
TO
VGA
2.5V 2.5V
C
LMD
LMD
C
IZ
R
IZ
604080
Figure 74. Simplified LNA Schematic
The LNA supports differential output voltages as high as 5 V p-p,
with positive and negative excursions of ±1.25 V, about a
common-mode voltage of 2.5 V. Because the differential gain
magnitude is 9, the maximum input signal before saturation is
±275 mV or +550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Because the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
voltage noise of 0.74 nV/√Hz. This is achieved with a current
consumption of only 11 mA per channel (55 mW). On-chip
resistor matching results in precise single-ended gains of 4.5×
(9× differential), critical for accurate impedance control. The use
of a fully differential topology and negative feedback minimizes
distortion. Low HD2 is particularly important in second harmonic
ultrasound imaging applications. Differential signaling enables
smaller swings at each output, further reducing third-order
distortion.
AD8331/AD8332/AD8334
Rev. G | Page 26 of 56
Active Impedance Matching
The LNA supports active impedance matching through an external
shunt feedback resistor from Pin LON to Pin INH. The input
resistance, RIN, is given in Equation 5, where A is the single-
ended gain of 4.5, and 6 kΩ is the unterminated input impedance.
IZ
IZ
IZ
IN R
R
A
R
R
+
×
=
+
=k33
k6
k6
1 (5)
CIZ is needed in series with RIZ because the dc levels at Pin LON
and Pin INH are unequal. Expressions for choosing RIZ in terms
of RIN and for choosing CIZ are found in the Applications
Information section. CSH and the ferrite bead enhance stability
at higher frequencies, where the loop gain is diminished, and
prevent peaking. Frequency response plots of the LNA are shown
in Figure 23 and Figure 24. The bandwidth is approximately
130 MHz for matched input impedances of 50 Ω to 200 Ω and
declines at higher source impedances. The unterminated
bandwidth (when RIZ = ∞) is approximately 80 MHz.
Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a single-ended
driver for auxiliary circuits, such as those used for Doppler
ultrasound imaging. Pin LON drives RIZ. Alternatively, a
differential external circuit can be driven from the two outputs
in addition to the active feedback termination. In both cases,
important stability considerations discussed in the Applications
Information section should be carefully observed.
The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open circuit gain results when driving the VGA, and a 0.8 dB
reduction results with an additional 100 Ω load at the output.
The differential gain of the LNA is 6 dB higher. If the load is less
than 200 Ω on either side, a compensating load is recommended
on the opposite output.
LNA Noise
The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of
the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open circuit, current noise is
2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in Figure 75.
Figure 76 and Figure 77 show simulations extracted from these
results and the 4.1 dB noise figure (NF) measurement with the
input actively matched to a 50 Ω source. Unterminated (RIZ = ∞)
operation exhibits the lowest equivalent input noise and noise
figure. Figure 76 shows the noise figure vs. source resistance,
rising at low RS, where the LNA voltage noise is large compared
to the source noise, and again at high RS due to current noise.
The VGA input-referred voltage noise of 2.7 nV/√Hz is
included in all of the curves.
V
OUT
UNTERMINATED
+
V
IN
R
IN
R
S
V
OUT
RESISTIVE TERMINATION
+
V
IN
R
IN
R
S
R
S
V
OUT
ACTIVE IMPEDANCE MATCH - R
S
= R
IN
+
V
IN
R
IN
R
IZ
R
IZ
1 + 4.5
R
S
R
IN
=
03199-075
Figure 75. Input Configurations
7
6
5
4
3
2
1
0
50 100 1k
NOISE FIGURE (dB)
R
S
()
03199-076
INCLUDES NOISE OF VGA
RESISTIVE TERMINATION
(R
S
= R
IN
)
ACTIVE IMPEDANCE MATCH
UNTERMINATED
SIMULATION
Figure 76. Noise Figure vs. RS for Resistive,
Active Match, and Unterminated Inputs
7
6
5
4
3
2
1
0
50 100 1k
NOISE FIGURE (dB)
R
S
()
03199-077
INCLUDES NOISE OF VGA
R
IN
= 50
R
IN
= 75
R
IN
= 100
R
IN
= 200
R
IZ
=
(SIMULATED RESULTS)
Figure 77. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
AD8331/AD8332/AD8334
Rev. G | Page 27 of 56
The primary purpose of input impedance matching is to
improve the system transient response. With resistive termination,
the input noise increases due to the thermal noise of the matching
resistor and the increased contribution of the LNA input voltage
noise generator. With active impedance matching, however, the
contributions of both are smaller than they would be for resistive
termination by a factor of 1/(1 + LNA Gain). Figure 76 shows
their relative NF performance. In this graph, the input impedance
is swept with RS to preserve the match at each point. The noise
figures for a source impedance of 50  are 7.1 dB, 4.1 dB, and
2.5 dB, respectively, for the resistive, active, and unterminated
configurations. The noise figures for 200  are 4.6 dB, 2.0 dB,
and 1.0 dB, respectively.
Figure 77 is a plot of NF vs. RS for various values of RIN, which is
helpful for design purposes. The plateau in the NF for actively
matched inputs mitigates source impedance variations. For
comparison purposes, a preamp with a gain of 19 dB and noise
spectral density of 1.0 nV/√Hz, combined with a VGA with
3.75 nV/√Hz, yields a noise figure degradation of approximately
1.5 dB (for most input impedances), significantly worse than
the AD8331/AD8332/AD8334 performance.
The equivalent input noise of the LNA is the same for single-
ended and differential output applications. The LNA noise figure
improves to 3.5 dB at 50 Ω without VGA noise, but this is
exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually recom-
mended for stability purposes when driving external circuits on
a separate board (see the Applications Information section). In
low noise applications, a ferrite bead is even more desirable.
VARIABLE GAIN AMPLIFIER
The differential X-AMP VGA provides precise input attenuation
and interpolation. It has a low input-referred noise of 2.7 nV/√Hz
and excellent gain linearity. A simplified block diagram is shown
in Figure 78.
03199-078
VIP
GAIN
R
6dB
2R
2
00
48dB
VIN
g
m
POSTAMP
POSTAMP
+
GAIN INTERPOLATOR
(BOTH CHANNELS)
Figure 78. Simplified VGA Schematic
X-AMP VGA
The input of the VGA is a differential R-2R ladder attenuator
network with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and isolate
their common-mode voltage. The VGA inputs are biased through
the center tap connection of the ladder to VCM, which is typically
set to 2.5 V and is bypassed externally to provide a clean ac ground.
The signal level at successive stages in the input attenuator
falls from 0 dB to −48 dB in +6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps
merge to provide a smooth attenuation range from 0 dB to
−48 dB. This circuit technique results in excellent linear-in-dB
gain law conformance and low distortion levels and deviates
±0.2 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.
The X-AMP inputs are part of a gain-of-12 feedback amplifier
that completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and to
ensure excellent frequency response uniformity across gain
setting (see Figure 12 and Figure 13).
Gain Control
Position along the VGA attenuator is controlled by a single-ended
analog control voltage, VGAIN, with an input range of 40 mV to
1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V
(20 mV/dB). Values of VGAIN beyond the control range saturate
to minimum or maximum gain values. Both channels of the
AD8332 are controlled from a single gain interface to preserve
matching. Gain can be calculated using Equation 1 and Equation 2.
Gain accuracy is very good because both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is ±1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple,
trim errors, and tester limits. The gain error relative to a best-fit
line for a given set of conditions is typically ±0.2 dB. Gain matching
between channels is better than 0.1 dB (Figure 11 shows gain errors
in the center of the control range). When VGAIN < 0.1 or > 0.95,
gain errors are slightly greater.
The gain slope can be inverted, as shown in Figure 73 (except for
the AD8332 AR models). The gain drops with a slope of −50 dB/V
across the gain control range from maximum to minimum gain.
This slope is useful in applications such as automatic gain control,
where the control voltage is proportional to the measured output
signal amplitude. The inverse gain mode is selected by setting the
MODE pin to HI gain mode.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
AD8331/AD8332/AD8334
Rev. G | Page 28 of 56
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum resolvable
input signal, the output-referred noise, which depends primarily
on the VGA, limits the maximum instantaneous dynamic range
that can be processed at any one particular gain control voltage.
This limit is set in accordance with the quantization noise floor
of the ADC.
Output- and input-referred noise as a function of VGAIN are plotted
in Figure 25 and Figure 27 for the short circuited input conditions.
The input noise voltage is simply equal to the output noise divided
by the measured gain at each point in the control range.
The output-referred noise is flat over most of the gain range
because it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and the noise of the source prevail. The input-
referred noise reaches its minimum value near the maximum
gain control voltage, where the input-referred contribution of
the VGA becomes very small.
At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, because the input
capacity increases with it. The contribution of the ADC noise
floor has the same dependence as well. The important relationship
is the magnitude of the VGA output noise floor relative to that
of the ADC.
With its low output-referred noise levels, these devices ideally
drive low voltage ADCs. The converter noise floor drops 12 dB
for every two bits of resolution and drops at lower input full-
scale voltages and higher sampling rates. ADC quantization
noise is discussed in the Applications Information section.
The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage because the
contribution of its bias noise is designed to cancel in the differential
signal. A transformer can be used with single-ended applications
when low noise is desired.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is present.
Its effect is observable only in LO gain mode where the noise
floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter can be
used to remove VGAIN source noise. The filter bandwidth should be
sufficient to accommodate the desired control bandwidth.
Common-Mode Biasing
An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection because
the VCM network makes a number of important connections
internally, including the center tap of the VGA differential input
attenuator, the feedback network of the VGA fixed gain amplifier,
and the feedback network of the postamp in both gain settings.
For best results, use a 1 nF capacitor and a 0.1 µF capacitor in
parallel, with the 1 nF capacitor nearest to the VCM pin. Separate
VCM pins are provided for each channel. For dc coupling to a 3 V
ADC, the output common-mode voltage is adjusted to 1.5 V by
biasing the VCM pin.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB
(×6), set by the HILO logic pin. Figure 79 is a simplified block
diagram.
0
3199-079
Gm2
+
Gm1
VOH
VOL
VCM
Gm1
Gm2
F1
F2
Figure 79. Postamplifier Block Diagram
Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/µs in HI gain
mode and 300 V/µs in LO gain mode. The feedback networks
for HI and LO gain modes are factory trimmed to adjust the
absolute gains of each channel.
Noise
The topology of the postamp provides constant input-referred
noise with the two gain settings and variable output-referred
noise. The output-referred noise in HI gain mode increases
(with gain) by four. This setting is recommended when driving
converters with higher noise floors. The extra gain boosts the
output signal levels and noise floor appropriately. When driving
circuits with lower input noise floors, the LO gain mode optimizes
the output dynamic range.
Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and 10-bit
converters, respectively. An additional technique, described in
the Applications Information section, can extend the noise floor
even lower for possible use with 14-bit ADCs.
AD8331/AD8332/AD8334
Rev. G | Page 29 of 56
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–3 –2 –1 0 1 2 3
V
OH
,
V
OL
(V)
V
INH
(V)
03199-080
R
CLMP
=
R
CLMP
=
8.8k
8.8k
3.5k
3.5k
R
CLMP
= 1.86k
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a resistor
from RCLMP to ground. Table 8 shows a list of recommended
resistor values.
Output clamping can be used for ADC input overload protection, if
needed, or postamp overload protection when operating from a
lower common-mode level, such as 1.5 V. The user should be
aware that distortion products increase as output levels approach
the clamping levels, and the user should adjust the clamp resistor
accordingly. For additional information, see the Applications
Information section.
The accuracy of the clamping levels is approximately ±5% in LO
or HI mode. Figure 80 illustrates the output characteristics for a
few values of RCLMP.
Figure 80. Output Clamping Characteristics
AD8331/AD8332/AD8334
Rev. G | Page 30 of 56
APPLICATIONS INFORMATION
LNA—EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be bypassed to
ground and signal sourced to the INH pin, which is capacitively
coupled using 2.2 nF to 0.1 µF capacitors (see Figure 81).
The unterminated input impedance of the LNA is 6 k. The
user can synthesize any LNA input resistance between 50  and
6 k. RIZ is calculated according to Equation 6 or selected from
Table 7.
()
()
IN
IN
IZ R
R
Rk6
k33 ×
= (6)
Table 7. LNA External Component Values for Common
Source Impedances
RIN (Ω) RIZ (Nearest STD 1% Value, Ω) CSH (pF)
50 280 22
75 412 12
100 562 8
200 1.13 k 1.2
500 3.01 k None
6 k None
When active input termination is used, a decoupling capacitor (CIS)
is required to isolate the input and output bias voltages of the LNA.
The shunt input capacitor, CSH, reduces gain peaking at higher
frequencies where the active termination match is lost due to
the gain roll-off of the LNA at high frequencies. The value of CSH
diminishes as RIN increases to 500 Ω, at which point no capacitor is
required. Suggested values for CSH for 50 Ω ≤ RIN ≤ 200 Ω are
shown in Table 7.
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values can prove useful.
Figure 82 shows the interconnection details of the LNA output.
Capacitive coupling between the LNA outputs and the VGA
inputs is required because of the differences in their dc levels
and the need to eliminate the offset of the LNA. Capacitor values
of 0.1 µF are recommended. There is a 0.4 dB loss in gain
between the LNA output and the VGA input due to the 5 Ω
output resistance. Additional loading at the LOP and LON
outputs affects LNA gain.
21
22
23
24
28
25
26
27
15
16
20
17
18
19
8
7
6
5
1
4
3
2
14
13
9
12
11
10
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
0.1µF
C
IZ
*
C
SH
*
R
IZ
*
C
LMD
0.1µF
1nF
5V
5V
1nF
5V
+5V
*
*
VGA OUT
VGA OUT
5V
1nF0.1µF
LNA OUT
1nF
V
GAIN
FB
1nF0.1µF
0.1µF
0.1µF
0.1µF
1nF 0.1µF
*SEE TEXT
03199-081
LNA
SOURCE
Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)
03199-082
VIN
VIP
LOP
VCM
100
50
100
LON
RIZ
CSH
TO EXT
CIRCUIT
TO EXT
CIRCUIT
LNA
DECOUPLING
RESISTOR
LN
A
DECOUPLING
RESISTOR
50
5
5
LNA
3.25V
3.25V
2.5V
2.5V
Figure 82. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits.
Pin LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it tolerates a load capacitance up
to 100 pF with the addition of a 49.9 Ω series resistor or ferrite
75 Ω/100 MHz bead.
AD8331/AD8332/AD8334
Rev. G | Page 31 of 56
Gain Input
The GAIN pin is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ, and a bypass capacitor
from 100 pF to 1 nF is recommended.
Parallel connected devices can be driven by a common voltage
source or DAC. Decoupling should take into account any band-
width considerations of the drive waveform, using the total
distributed capacitance.
If gain control noise in LO gain mode becomes a factor, main-
taining ≤15 nV/√Hz noise at the GAIN pin ensures satisfactory
noise performance. Internal noise prevails below 15 nV/√Hz at
the GAIN pin. Gain control noise is negligible in HI gain mode.
VCM Input
The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH
defaults to 2.5 V dc. With output ac-coupled applications, the
VCM pin is unterminated; however, it must still be bypassed in
close proximity for ac grounding of internal circuitry. The VGA
outputs can be dc connected to a differential load, such as an
ADC. Common-mode output voltage levels between 1.5 V and
3.5 V can be realized at Pin VOH and Pin VOL by applying the
desired voltage at Pin VCM. DC-coupled operation is not
recommended when driving loads on a separate PC board.
The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see Figure 83). If the VCM pin is driven from an external
source, its output impedance should be <<30 Ω, and its current
drive capability should be >>2 mA. If the VCM pins of several
devices are connected in parallel, the external buffer should be
capable of overcoming their collective output currents. When a
common-mode voltage other than 2.5 V is used, a voltage-
limiting resistor, RCLMP, is needed to protect against overload.
03199-083
VCM
NEW V
CM
R
O
<< 30
100pF
2mA MAX
30
0.1µF
INTERNAL
CIRCUITRY
AC GROUNDING FOR
INTERNAL CIRCUITRY
Figure 83. VCM Interface
Logic Inputs—ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 kΩ and
can be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pin, ENB,
powers down the VGA; when pulled low, the VGA output voltages
are near ground. Multiple devices can be driven from a common
source. Consult Table 3, Table 4, Table 5, and Table 6 for infor-
mation about circuit functions controlled by the enable pins.
Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground (see Table 8
for a list of several voltage levels and corresponding resistor
values). Unconnected, the default limiting level is 4.5 V p-p.
Note that third harmonic distortion increases as waveform
amplitudes approach clipping. For lowest distortion, the clamp level
should be set higher than the converter input span. A clamp level
of 1.5 V p-p is recommended for a 1 V p-p linear output range,
2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation.
The best solution is determined experimentally. Figure 84 shows
third harmonic distortion as a function of the limiting level for
a 2 V p-p output signal. A wider limiting level is desirable in HI
gain mode.
20
–30
–40
–50
–60
–70
–80
1.52.02.53.0 4.03.5 4.5 5.0
HD3 (dBc)
CLAMP LIMIT LEVEL (V p-p)
03199-084
V
GAIN
= 0.75V
HILO = LO
HILO = HI
Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input
Table 8. Clamp Resistor Values
Clamp Level (V p-p)
Clamp Resistor Value (kΩ)
HILO = LO HILO = HI
0.5 1.21
1.0 2.74 2.21
1.5 4.75 4.02
2.0 7.5 6.49
2.5 11 9.53
3.0 16.9 14.7
3.5 26.7 23.2
4.0 49.9 39.2
4.4 100 73.2
Output Decoupling
When driving capacitive loads greater than about 10 pF, or long
circuit connections on other boards, an output network of resistors
and/or ferrite beads can be useful to ensure stability. These
components can be incorporated into a Nyquist filter such as
the one shown in Figure 81. In Figure 81, the resistor value is
84.5 Ω. For example, all the evaluation boards for this series
incorporate 100 in parallel with a 120 nH bead. Lower value
resistors are permissible for applications with nearby loads or
AD8331/AD8332/AD8334
Rev. G | Page 32 of 56
with gains less than 40 dB. The exact values of these components
can be selected empirically.
An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.
When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and to mitigate charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 85
shows a second-order, low-pass filter with a bandwidth of 20 MHz.
The capacitor is chosen in conjunction with the 10 pF input
capacitance of the ADC.
03199-085
18pF
OPTIONAL
BACKPLANE
0.1µF
0.1µF ADC
84.5
84.5
158
158
1.5µH
1.5µH
Figure 85. 20 MHz Second-Order, Low-Pass Filter
DRIVING ADCs
The output drive accommodates a wide range of ADCs. The
noise floor requirements of the VGA depend on a number of
application factors, including bit resolution, sampling rate, full-
scale voltage, and the bandwidth of the noise/antialias filter. The
output noise floor and gain range can be adjusted by selecting
HI or LO gain mode.
The relative noise and distortion performance of the two gain
modes can be compared in Figure 25 and Figure 31 through
Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full-
scale voltages as high as 4 V p-p. Because distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 36), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 86 has an output full-scale range of
2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.
03199-086
ADC
AD6644
187
2:1
187
374
VOH
VOL
LPF
4V p-p DIFF,
48nV/ Hz
2V p-p DIFF,
24nV/ Hz
Figure 86. Adjusting the Noise Floor for 14-Bit ADCs
OVERLOAD
These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.
Signals larger than ±275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 48
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.
Both stages of the VGA are susceptible to overload. Post-
amplifier limiting is more common and results in the clean-
limited output characteristics found in Figure 49. Recovery is fast in
all cases. The graph in Figure 87 summarizes the combinations of
input signal and gain that lead to the different types of overload.
03199-087
GAIN (dB)
1m
LO GAIN
MODE
15mV
–4.5
25mV
LNA OVERLOAD
X
-AMP
OVERLOAD
POSTAMP
OVERLOAD
X
-AMP
OVERLOAD
POSTAMP
OVERLOAD
29dB
43.5
INPUT AMPLITUDE (V)
0.2750.110m
24.5dB
GAIN (dB)
HI GAIN
MODE
4mV
7.5
25mV
LNA OVERLOAD
41dB
56.5
INPUT AMPLITUDE (V)
24.5dB
11m 0.2750.110m 1
Figure 87. Overload Gain and Signal Conditions
The clamp interface mentioned in the Output Clamping section
controls the maximum output swing of the postamp and its
overload response. When the clamp feature is not used, the
output level defaults to approximately 4.5 V p-p differential
centered at 2.5 V common mode. When other common-mode
levels are set through the VCM pin, the value of RCLMP should be
selected for graceful overload. A value of 8.3 kΩ or less is
recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ
for HI gain mode). This limits the output swing to just above
2 V p-p differential.
OPTIONAL INPUT OVERLOAD PROTECTION
Applications in which high transients are applied to the LNA
input can benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to manageable
levels. Figure 88 illustrates how such a diode protection scheme
can be connected.
03199-088
20
19
4
3
2
LON
VPSL
INH
COMM
ENBL
0.1µF
FB
R
SH
C
IZ
R
IZ
C
SH
2
3
1
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
BAS40-04
Figure 88. Input Overload Clamping
AD8331/AD8332/AD8334
Rev. G | Page 33 of 56
When selecting overload protection, the important parameters
are forward and reverse voltages and trr (or τrr). The Infineon
BAS40-04 series shown in Figure 88 has a τrr of 100 ps and a VF
of 310 mV at 1 mA. Many variations of these specifications can
be found in vendor catalogs.
LAYOUT, GROUNDING, AND BYPASSING
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environments. Realizing
expected performance requires attention to detail critical to
good, high speed, board design.
A multilayer board with power and ground planes is recom-
mended with blank areas in the signal layers filled with ground
plane. Be certain that the power and ground pins provided for
robust power distribution to the device are connected. Decouple
the power supply pins with surface-mount capacitors as close as
possible to each pin to minimize impedance paths to ground.
Decouple the LNA power pins from the VGA supply using
ferrite beads. Together with the capacitors, ferrite beads
eliminate undesired high frequencies without reducing the
headroom. Use a larger value capacitor for every 10 chips to
20 chips to decouple residual low frequency noise. To minimize
voltage drops, use a 5 V regulator for the VGA array.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before connecting
to the coupling capacitors connected to Pin VIN and Pin VIP.
RIZ must be placed near the LON pin as well. Resistors must be
placed as close as possible to the VGA output pins, VOL and
VOH, to mitigate loading effects of connecting traces. Values
are discussed in the Output Decoupling section.
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can be
accomplished as shown in Figure 89. A relay and low supply voltage
analog switch can be used to select between multiple sources
and their associated feedback resistors. An ADG736 dual SPDT
switch is shown in this example; however, multiple switches are
also available and users are referred to the Analog Devices
Selection Guide for switches and multiplexers.
03199-090
INH
LNA
5
200
50
LMD LOP
ADG736
LON
0.1µF
18nF
280
1.13k
AD8332
5
SELECT RIZ
Figure 89. Accommodating Multiple Sources
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground
powers down the LNA, resulting in a current reduction of about
half. In this mode, the LNA input and output pins can be left
unconnected; however, the power must be connected to all the
supply pins for the disabling circuit to function. Figure 90 illustrates
the connections using AD8331 as an example.
03199-089
15
16
20
17
18
19
8
7
6
5
1
4
3
2
9
13
10
COMM
VIP
LOP
COML
LMD
LON
VPSL
INH
COMM
ENBV
ENBL
GAIN
0.1µF
HILO
+5V
+5V
NC
VOH
VOL
VOUT
VPOS +5V
14
11
12
VCM
RCLMP
NC
NC
NC
VIN
0.1µF
AD8331
MODE
GAIN
MODE
VCM
HILO
VIN
RCLMP
Figure 90. Disabling the LNA
AD8331/AD8332/AD8334
Rev. G | Page 34 of 56
ULTRASOUND TGC APPLICATION
The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key
subsystem in such applications because it provides the means
for echo location of reflected ultrasound energy.
Figure 91 through Figure 93 are schematics of a dual, fully
differential system using the AD8332 and the AD9238 12-bit
high speed ADC with conversion speeds as high as 65 MSPS.
HIGH DENSITY QUAD LAYOUT
The AD8334 is the ideal solution for applications with limited
board space. Figure 94 represents four channels routed to and
away from this very compact quad VGA. Note that none of the
signal paths crosses and that all four channels are spaced apart
to eliminate crosstalk.
In this example, all of the components shown are 0402 size;
however, the same layout is executable at the expense of slightly
more board area. The sketch also assumes that both sides of the
printed circuit board are available for components and that the
bypass and power supply decoupling circuitry is located on the
wiring side of the board.
AD8331/AD8332/AD8334
Rev. G | Page 35 of 56
03199-091
+5VLNA
VOH1
21
25
VIN1
LON1
C78
1nF
C58
0.1µF
17
AD8332ARU
V
IN
+A
1
C49
0.1µF
2
C80
22pF
3
CFB1
18nF
C59
0.1µF
C41
0.1µF
C74
1nF
4
7
5
C53
0.1µF
VPS1 26
6COM1 23
8
C51
0.1µF
27
INH1 S1
E
IN1
C60
0.1µF
C79
22pF
L13
120nH FB
TP6
28
LMD1
C70
0.1µF
14
9
C48
0.1µF
10
C83
1nF
11
R3
(R
CLMP
)
C54
0.1µF
C55
0.1µF
12
LMD2
INH2
VPS2
LON2
VIP2
LOP2
COM2
VIN2
COMM
VCM2
GAIN
RCLMP
VOH2
VOL2
13
JP12 VPSV 15
C45
0.1µF C85
1nF
VOL1
C56
0.1µF
16
L8
120nF FB
18
ENB
+5VGA
19
HILO
20
VCM1
C43
0.1µF
C77
1nF
22
24
VIP1
LOP1
+5VLNA
VCM1
RFB1
274
RFB2
274
C50
0.1µF
S3
E
IN2
L12
120nH FB
TP5
CFB2
18nF
C68
1nF
C69
0.1µF
R27
100
L11
120nH FB
JP8
DC2H
L10
120nH FB
JP7
DC2L R26
100
+5VGA
ENABLE
HI GAIN
DISABLE
LO GAIN
L9
120nH FB
R24
100JP9
JP10
JP17
TP2 GAIN
JP5
IN2
JP6
IN1
TP7 GND
L17
SAT
L18
SAT
L19
SAT
L20
SAT
C67
SAT
C66
SAT
L1
SAT
L14
SAT
L15
SAT
L16
SAT
C64
SAT
C65
SAT
OPTIONAL 4-POLE LOW-PASS
FILTER
JP13
VCM1
+5VGA
JP10
JP16
R25
100
C42
0.1µF
V
IN
–A
TB1
+5V
TB2
GND
C46
1µF
+5VGA
L7
120nH FB
L6
120nH FB
TP4
(BLACK)
TP3
(RED)
+
+5VLNA
+5V
V
IN
+B
V
IN
–B
OPTIONAL 4-POLE LOW-PASS
FILTER
Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238
AD8331/AD8332/AD8334
Rev. G | Page 36 of 56
1
2
3
17
62
6
7
11
10
14
15
18
63
19
20
60
21
22
16
4
13
64
12
5
8
9
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VREF
VIN+_A
VIN–_A
VIN–_B
VIN+_B
AVDD
REFT_A
REFB_A
SENSE
REFT_B
REFB_B
CLK_B
DCS
DFS
PDWN_B
OEB_B
AGND
AGND
AVDD
AVDD
AGND
AGND
D5_B
D4_B
D3_B
DRGND
D2_B
D1_B
D0_B
DNC
DNC
DRVDD
D10_A
D11_A
61
59
58
57
56
55
54
53
OTR_A
U1 A/D CONVERTER AD9238
D9_A
D8_A
D6_A
D7_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
D4_B
D3_B
D2_B
D1_B
D0_B
DNC
DNC
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
D5_B
20MHz
ADCLK
+3.3VCLK
ADCLK
+3.3VAVDD
V
IN
–_B
V
IN
+_B
+
+3.3VADDIG
SG-636PCE
14
3
2
U5
74VHC04
+
+
TP9
TP 12
4312
1213
1011
U5
74VHC04
U5
74VHC04
U5
74VHC04
U5
74VHC04
U5
74VHC04
SPARES
8965
TP 13
JP1
3
2
1
V
DD
OUT
GND
OE
JP4
S2
EXT CLOCK
+
JP11JP3
JP2
SHARED
REF
+3.3VADDIG
Y
MUX_SELECT
SHARED_REF
CLK_A
PDWN_A
AVDD
OTR_A
D11_A (MSB)
DRGND
D8_A
DRVDD
D7_A
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DRVDD
D10_A
DRGND
OTR_B
D9_A
D10_B
D9_B
D8_B
D7_B
D6_B
D11_B (MSB)
DNC
DNC
OEB_A
EXT
INT
V
IN
+_A
V
IN
–_A
N
DATA
CLK
VREF
C11
10µF
6.3V
C14
0.1µF
C23
0.1µF
C25
1nF
R14
4.7k
R11
100
R10
0
R15
0
C22
0.1µF
C21
1nF
C86
0.1µF
C47
10µF
6.3V ADCLK
C2
10µF
6.3V
C18
1nF
C17
0.1µF
C52
10nF
C57
10nF
C61
18pF
C40
0.1µF
R5
33
R6
33
R4
1.5k
R12
1.5k
1.5k1.5k
C12
10µF
6.3V
R9
0
R8
33
R7
33
C19
1nF
C20
0.1µF
C63
0.1µF
C26
0.1µF
C24
1nF
C33
10µF
6.3V
C38
0.1µF
C16
0.1µF
C62
18pF
C15
1nF
C35
0.1µF
C36
0.1µF
C37
0.1µF
R20
4.7k
R17
49.9
R41
4.7k
+3.3VCLK
R19
499
R16
5k
R18
499
+
+3.3VADDIG
3
2
1
C32
0.1µF
C39
10µF
C34
10µF
6.3V
C44
1µF
C31
0.1µF
C30
0.1µF
C29
0.1µF
C1
0.1µF
OUT
V
R1
ADP3339AKC-3.3
L2
120nH FB
L3
120nH FB
L4
120nH FB
L5
120nH FB
IN
OUT
GND
312
TAB
+
+5V
03199-092
C13
1nF
U6
Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238
AD8331/AD8332/AD8334
Rev. G | Page 37 of 56
19
1
D10_A
D11_A
24
39
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20
+
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20
+
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20
++
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
VCC
GND
Y1
A1
G1
1
2
3
6
7
10
4
5
8
9
17
11
14
15
18
19
20
+
16
13
12
G2
A8
A7
A6
A5
A4
A3
A2
Y8
Y7
Y6
Y5
Y4
Y3
Y2
2
3
6
7
10
4
5
8
9
17
11
14
15
18
20
16
13
12
37
21
26 25
30
22
23
28 27
35
29
34 33
38
40
36
3132
R39
22
DATACLKA
OTR_A
D9_A
D8_A
D6_A
D7_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
D5_B
D4_B
D3_B
D2_B
D1_B
D0_B
DNC
DNC
+3.3VDVDD
+3.3VDVDD
+3.3VDVDD
DATACLK
U3
74VHC541
U10
74VHC541
U7
74VHC541
U2
74VHC541
SAM080UPM
76
61
79
58
41
80
77
73
72
78
75
74
71
63
69
68
65
64
62
66
67
70
43
59
56 55
52
60
57
54 53
45
51
48 47
44
42
46
4950
SAM080UPM
RP 9
8
7
6
5
8
7
6
5
1
4
3
2
1
4
3
2
8
7
6
5
8
7
6
5
1
4
3
2
1
4
3
2
8
7
6
5
8
7
6
5
7
6
5
8
7
6
5
4
3
2
1
4
3
2
RP 11
RP 12
RP 13
RP 14
1
4
3
2
1
4
3
2
18
RP 15
RP 16
R40
22
18
7
6
54
3
2RP 1
18
7
6
54
3
2RP2
18
7
6
54
3
2RP 3
18
7
6
54
3
2RP 4
18
7
6
54
3
2
RP 5
18
7
6
54
3
2
RP 6
18
7
6
54
3
2
RP 7
18
7
6
54
3
2
RP 8
22 × 4
22 × 4
RP 10
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
HEADER UP MALE NO SHROUD
HEADER UP MALE NO SHROUD
C3
0.1µF
C28
10µF
6.3V
C8
0.1µF
C10
0.1µF
C76
10µF
6.3V
C7
0.1µF
C9
0.1µF
C27
10µF
6.3V
C4
0.1µF
C5
0.1µF
C6
0.1µF
C75
10µF
6.3V
+3.3VDVDD
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
22 × 4
03199-093
Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238
AD8331/AD8332/AD8334
Rev. G | Page 38 of 56
2825 26 2717 18 19 21 22 23 24
15
16
8
7
6
5
1
4
3
2
14
13
9
12
11
10
50 4956 55 5154 53 52
35
36
37
38
42
39
40
41
34
33
29 30 31 32
48
47
43
46
45
44
58 575962 61 6063
64
20
POWER SUPPLY DECOUPLING
LOCATED ON WIRING SIDE
AD8334
INH2
LMD2
NC
LON2
LOP2
VIP2
VIN2
VPS2
VPS3
VIN3
VIP3
LOP3
LON3
NC
LMD3
INH3
NC
COM12
VOH1
VOL1
VPS12
VOL2
VOH2
COM12
MODE
COM34
VOH3
VOL3
VPS34
VOL4
VOH4
COM34
COM3
COM4
INH4
LMD4
NC
LON4
LOP4
VIP4
VIN4
VPS4
GAIN34
CLMP34
HILO
VCM4
VCM3
NC
COM2
COM1
INH1
LMD1
NC
LON1
LOP1
VIP1
VIN1
VPS1
GAIN12
CLMP12
EN12
EN34
VCM1
VCM2
CH1 LNA INPUT
CH2 LNA INPUT
CH3 LNA INPUT
CH4 LNA INPUT
CH1 DIFFERENTIAL
OUTPUT
CH2 DIFFERENTIAL
OUTPUT
CH3 DIFFERENTIAL
OUTPUT
CH4 DIFFERENTIAL
OUTPUT
03199-094
NC = NO CONNECT
Figure 94. Compact Signal Path and Board Layout for the AD8334
AD8331/AD8332/AD8334
Rev. G | Page 39 of 56
AD8331 EVALUATION BOARD
03199-115
GENERAL DESCRIPTION
The AD8331 evaluation board is a platform for testing and
evaluating the AD8331 variable gain amplifier (VGA). The
board is provided completely assembled and tested; the user
simply connects an input signal, VGAIN sources, and a 5 V
power supply. The AD8331-EVALZ is lead free and RoHS
compliant. Figure 95 is a photograph of the board.
USER-SUPPLIED OPTIONAL COMPONENTS
As shown in the schematic in Figure 96, the board provides for
optional components. The components shown in black are for
typical operation, and the components shown in gray are
installed at the user’s discretion.
As shipped, the LNA input impedance of the AD8331-EVALZ is
configured for 50  to accommodate most signal generators and
network analyzers. Input impedances up to 6 kΩ are realized by
changing the values of RFB and CSH. Refer to the Theory of
Operation section for details on this circuit feature. See Table 9
for typical values of input impedance and corresponding
components.
Figure 95. Photograph of AD8331-EVALZ
MEASUREMENT SETUP
The basic board connection for measuring bandwidth is shown
in Figure 97. A 5 V, 100 mA minimum power supply and a low
noise, voltage reference supply for GAIN are required. Table 10
lists jumpers, and Figure 97 shows their functions and positions.
Table 9. LNA External Component Values for Common
Source Impedances The preferred signal detection method is a differential probe
connected to VO, as shown in Figure 97. Single-ended loads can be
connected using the board edge SMA connector, VOH. Be sure to
take into account the 25.8 dB attenuation incurred when using the
board in this manner. For connection to an ADC, the 270  series
resistors can be replaced with 0  or other appropriate values.
RIN (Ω) RFB (Ω, Nearest 1% Value) CSH (pF)
50 274 22
75 412 12
100 562 8
200 1.13 k 1.2
500 3.01 k None
6 k None
Table 10. Jumper Functions
Switch Function
LNA_EN Enables the LNA when in the top position
VGA_EN Enables the VGA when in the top position
W5, W6 Connects the AD8331 outputs to the SMA connectors
GN_SLOPE Left = gain increases with VGAIN
Right = gain decreases with VGAIN
GN_HI_LO Left = high gain
Right = LO gain
The board is designed for 0603 size, surface-mount components.
Back-to-back diodes can be installed at Location D3 if desired.
To evaluate the LNA as a standalone amplifier, install optional
SMA connectors LON and LOP and capacitors C1 and C2;
typical values are 0.1 µF or smaller. At R4 and R8, 0  resistors
are installed unless capacitive loads larger than 10 pF are connected
to the SMA connectors LON and LOP (such as coaxial cables).
In that event, small value resistors (68  to 100 ) must be
installed at R4 and R8 to preserve the stability of the amplifier. BOARD LAYOUT
The evaluation board circuitry uses four conductor layers. The
two inner layers are grounded, and all interconnecting circuitry
is located on the outer layers. Figure 99 to Figure 102 illustrate
the copper patterns.
A resistor can be inserted at RCLMP if output clamping is
desired. Refer to Table 8 for appropriate values.
AD8331/AD8332/AD8334
Rev. G | Page 40 of 56
AD8331 EVALUATION BOARD SCHEMATICS
03199-116
MODE
VIP
GAIN
VIN
LOP
COML
LMD2
LON
VPS
INH
VOH
VOL
COMM
COMM
ENBV
VPOS
CLMP
HILO
VCM
C2
C1
R4
R8
LNA2
+5V
LO
+5
V
+5V
GN_SLOPE
W5
W6
GNDGND2GND1
DUT
AD8331ARQ
GND4GND3
+
1
2
3
4
5
6
7
8
9
10
20
18
17
16
15
14
13
12
11
C3
10µF
10V
L1
120nH FB
C
INH
0.1µF
CLMD
0.1µF
L2
120nH FB
CSH
22pF
C6
0.1µF
LON
LOP
C16
0.1µF
C14
0.1µF
GAIN
C34
1nF
COMPONENTS IN GRAY ARE
OPTIONAL AND USER SUPPLIED.
L4
120nH FB
VO
VOH
T1
1:1
R16
237
R20
237
C24
0.1µF
C26
0.1µF
R43
100
R44
100
L3
120nH FB
C17
0.1µF
C32
0.1µF
C18
0.1µF
ENB LNA_EN
19
GN_HI_LO
+5V
+5V
VGA_EN
INPUT
CLAMP
DIODES
3D1
BAT64-04
CFB
0.018µF
RFB
274µF
RCLMP
VCM
L5
120nH FB
PROBE
RCLMP
ENABLE
DISABLE
ENABLE
DISABLE
HI
LO
DOWN
UP
Figure 96. Schematic of the AD8331 Evaluation Board
AD8331/AD8332/AD8334
Rev. G | Page 41 of 56
GND
GND
DP8200 PRECISION VOLTAGE REFERENCE
(FOR VGAIN)
4395A ANALYZER
1103 TEKPROBE
POWER SUPPLY
E3631A
POWER SUPPLY
03199-117
+5V
DIFFERENTIAL PROBE
TO VO PINS
INSERT JUMPERS W5 AND W6
TO USE OUTPUT
TRANSFORMER AND VOH SMA
Figure 97. AD8331 Typical Board Test Connections
AD8331/AD8332/AD8334
Rev. G | Page 42 of 56
AD8331 EVALUATION BOARD PCB LAYERS
0
3199-118
Figure 98. AD8331-EVALZ Assembly
03199-199
Figure 99. Primary Side Copper
03199-200
Figure 100. Secondary Side Copper
03199-201
Figure 101. Internal Layer Ground
03199-202
Figure 102. Power Plane
03199-119
Figure 103. Top Silkscreen
AD8331/AD8332/AD8334
Rev. G | Page 43 of 56
AD8332 EVALUATION BOARD
GENERAL DESCRIPTION
The AD8332-EVALZ is a platform for the testing and evaluation of
the AD8332 variable gain amplifier (VGA). The board is shipped
assembled and tested, and users need only connect the signal
and VGAIN sources to a single 5 V power supply. Figure 104 is a
photograph of the component side of the board, and Figure 105
shows the schematic. The AD8332-EVALZ is lead free and
RoHS compliant.
03199-131
Figure 104.Photograph of the AD8332-EVALZ
USER-SUPPLIED OPTIONAL COMPONENTS
The board is built and tested using the components shown in
black in Figure 105. Provisions are made for optional components
(shown in gray) that can be installed for testing at user discretion.
The default LNA input impedance is 50 Ω to match various
signal generators and network analyzers. Input impedances up to
6 kΩ are realized by changing the values of RFBx and CSHx. For
reference, Table 11 lists the common input impedance values
and corresponding adjustments. The board is designed for 0603
size, surface-mount components.
Table 11. LNA External Component Values for Common
Source Impedances
RIN (Ω) RFB1, RFB2 (Ω Std 1% Value) CSH1, CSH2 (pF)
50 274 22
75 412 12
100 562 8
200 1.13 k 1.2
500 3.01 k None
6 k None
SMA connectors, S2, S3, S6, and S7, are provided for access to
the LNA outputs or the VGA inputs. If the LNA is used alone,
0.1 µF coupling capacitors can be installed at the C5, C9, C23,
and C24 locations. Resistors of 68 Ω to 100 Ω may be required
if the load capacitances, as seen by the LNA outputs, are larger
than approximately 10 pF.
A resistor can be inserted at RCLMP if output clamping is desired.
The peak-to-peak clamping level is adjusted by installing one of
the standard 1% resistor values listed in Table 8.
A high frequency differential probe connected to the 2-pin headers,
VOx, is the preferred method to observe a waveform at the VGA
output. A typical setup is shown in Figure 106. Single-ended loads
can be connected directly via the board edge SMA connectors.
Note that the AD8332 output amplifier is buffered with 237 Ω
resistors; therefore, be sure to compensate for attenuation if low
impedances are connected to the output SMAs.
MEASUREMENT SETUP
The basic board connections for measuring bandwidth are
shown in Figure 106. A 5 V, 100 mA (minimum) power supply
is required, and a low noise voltage reference supply is required
for VGAIN.
BOARD LAYOUT
The evaluation board circuitry uses four conductor layers.
The two inner layers are power and ground planes, and all
interconnecting circuitry is located on the outer layers. Figure 108
to Figure 111 illustrate the copper patterns.
AD8331/AD8332/AD8334
Rev. G | Page 44 of 56
EVALUATION BOARD SCHEMATICS
VCM2
RCLMP
COMM
VOL2
VOH2
VIP2
GAIN
VIN2
LOP2
COM2
LMD2
LON2
VPS2
INH2
COM1
LOP1
LMD1
LON1
VPS1
INH1
VOH1
ENB
VIP1
VCM1
VIN1
VPSV
VOL1
HILO
+5V
LO
W9
C24
C23
R9
R11
R12
R10
C5
C9
+5VLNA
LNA2
+5V
W8
RCLMP
+5
V
W4
+5V
HI
+5VLNA
W5
W12
W13
W10
W11
GND GND4GND3GND2GND1
AD8332ARUZ
+1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
28
27
26
25
24
23
22
21
20
19
18
17
16
C25
10µF
L1
120nH FB
C4
0.1µF CSH2
22pF
C2
0.1µF
L8
120nH FB
CAL2 CFB2
18nF
C6
0.1µF RFB2
274
S6
LON2
S7
LOP2
C16
0.1µF
C14
0.1µF
C10
0.1µF
VCM2
GAIN
C8
1nF
TP3
CLAMP
C20
0.1µF
L3
120nH FB
R7
100
R8
100
L4
120nH FB
VOH2
T2
1:1 R13
237
C11
0.1µF
W6
VO2
R14
237
C12
0.1µF
COMPONENTS IN GRAY ARE
OPTIONAL AND USER SUPPLIED.
C22
0.1µF
L7
120nH FB
L5
120nH FB
W7
VO1
VOH1
T1
1:1
R15
237
R16
237
C19
0.1µF
C18
0.1µF
R6
100
R5
100
L6
120nH FB
ENABLE
DISABLE
C17
0.1µF
VCM1
C15
0.1µF
C13
0.1µF
S3
LOP1
S2
LON1
RFB1
274
C7
0.1µF
CAL1
CFB1
18nF
LNA1
L2
120nH FB
C3
0.1µF
CSH1
22pF
C1
0.1µF
0
3199-096
+5V
Figure 105. Schematic of the AD8332 Evaluation Board
AD8331/AD8332/AD8334
Rev. G | Page 45 of 56
VGAIN SUPPLY
NETWORK ANALYZER
1103 TEKPROBE
POWER SUPPLY
DIFFERENTIAL PROBE
03199-120
Figure 106. AD8332 Typical Board Test Connections
AD8331/AD8332/AD8334
Rev. G | Page 46 of 56
AD8332 EVALUATION BOARD PCB LAYERS
03199-121
Figure 107. AD8332-EVALZ Assembly
03199-099
Figure 108. Primary Side Copper
03199-100
Figure 109. Secondary Side Copper
03199-101
Figure 110. Ground Plane
0
3199-102
Figure 111. Power Plane
03199-103
Figure 112. Component Side Silkscreen
AD8331/AD8332/AD8334
Rev. G | Page 47 of 56
AD8334 EVALUATION BOARD
GENERAL DESCRIPTION
The AD8334-EVALZ is a platform for the testing and evaluation of
the AD8334 variable gain amplifier (VGA). The board is shipped
assembled and tested, and users need only connect the signal
and VGAIN sources and a single 5 V power supply. Figure 113
is a photograph of the board. The AD8334-EVALZ is lead free
and RoHS compliant.
03199-122
Figure 113. AD8334-EVALZ Top View
AD8331/AD8332/AD8334
Rev. G | Page 48 of 56
CONFIGURING THE INPUT IMPEDANCE
The board is built and tested using the components shown in
black in Figure 115. Provisions are made for optional components
(shown in gray) that can be installed at user discretion. As
shipped, the input impedances of the low noise amplifiers (LNAs)
are configured for 50 Ω to match the output impedances of most
signal generators and network analyzers. Input impedances up to
6 kΩ can be realized by changing the values of the feedback
resistors, RFB1, RFB2, RFB3, RFB4, and shunt capacitors, C6, C8, C10,
and C12. For reference, Table 12 lists standard values of 1%
resistors for some typical values of input impedance. Of course,
if the user has determined that the source impedance falls
between these values, the feedback resistor value can be
calculated accordingly. Note that the board is designed to accept
standard surface-mount, size 0603 components.
Table 12. LNA External Component Values for Common
Source Impedances
RIN (Ω) RFB1, RFB2, RFB3, RFB4 (Ω, ±1%) C6, C8, C10, C12 (pF)
50 274 22
75 412 12
100 562 8
200 1.13 k 1.2
500 3.01 k No capacitor
6 k No resistor No capacitor
Driving the VGA from an External Source or Using the
LNA to Drive an External Load
Appropriate components can be installed if the user wants to
drive the VGA directly from an external source or to evaluate
the LNA output. If the LNA is used to drive off-board loads
or cables, small value series resistors (47 Ω to 100 Ω) are
recommended for LNA decoupling. These can be installed
in the R10, R11, R14, R15, R18, R19, R22, and R23 spaces.
Provisions are made for surface-mount SMA connectors that
can be used for driving from either direction. If the LNA is not
used, it is recommended that the capacitors, C16, C17, C21,
C22, C26, C27, C31, and C32, be carefully removed to avoid
driving the outputs of the LNAs.
Using the Clamp Circuit
The board is shipped with no resistors installed in the spaces
provided for clamp-circuit operation. Note that each pair of
channels shares a clamp resistor. If the output clamping is
desired, the resistors are installed in R49 and R50. The peak-to-
peak clamping level is application dependent.
Viewing Signals
The preferred signal detector is a high impedance differential
probe, such as the Tektronix P6247, 1 GHz differential probe,
connected to the 2-pin headers (VO1, VO2, VO3, or VO4), as
shown in Figure 116. The low capacitance of this probe has the
least effect on the performance of the device of any detection
method tried. The probe can also be used for monitoring input
signals at IN1, IN2, IN3, or IN4. It can be used for probing
other circuit nodes; however, be aware that the 200 kΩ input
impedance can affect certain circuits.
Differential-to-single-ended transformers are provided for
single-ended output connections. Note that series resistors are
provided to protect against accidental output overload should a
50 Ω load be connected to the connector. Of course, the effect
of these resistors is to limit the bandwidth. If the load connected
to the SMA is >500 Ω, the 237 Ω series resistors, RX1, RX2, RX3,
RX4, RX5, RX6, RX7, and RX8, can be replaced with 0 Ω values.
03199-123
Figure 114. AD8334-EVALZ Assembly
MEASUREMENT SETUP
The basic board connections for measuring bandwidth are
shown in Figure 116. A 5 V, 200 mA (minimum) power supply
is required, and a low noise voltage reference supply is required
for VGAIN.
BOARD LAYOUT
The evaluation board circuitry uses four conductor layers. The
two inner layers are ground, and all interconnecting circuitry is
located on the outer layers. Figure 117 to Figure 120 illustrate
the copper patterns.
AD8331/AD8332/AD8334
Rev. G | Page 49 of 56
EVALUATION BOARD SCHEMATICS
COM34
VOL2
VOH2
VOH1
VOL1
COM12
VPS 34
COMM34
LM D 2
LO N2
INH2
VOH3
VOH4
VOL3
VOL4
VP SV2
COM12
25 26 2717 18 19 21 22 23 24
15
16
8
7
6
5
1
4
3
2
14
13
9
12
11
10
50 4 956 55 5154 53 52
35
36
37
38
42
39
40
41
34
33
30 31 32
48
47
43
46
45
44
58 57
5962 61 60
VPS 2
VIP2
VIN2
LO P2
VPS 3
VIP3
VIN3
LM D 3
LO N3
INH3
LO P3
NC
COM3
COM4
LMD4
IN H4
VCM4
VCM3
HILO
CLMP34
LON4
VPS4
VIP4
VIN4
LOP4
NC
NC
3
NC3
MODE
LMD1
LON1
VPS1
IN H1
COM1
63
LOP1
VIP1
VIN1
EN12
VCM1
COM2
GAIN12
VCM2
CLMP12
EN34
NC
64
20
C7
0.1 µF
INH2
IN2
C8
22 pF
L7
120 nH
CF B 2
18 nF
C2
0.1 µF
LO21
R151
0
R141
0
RFB2
27 4
C69
0.1 µ F
L2
12 0 nH
C71
0.1 µF
L3
12 0 nH
C3
0.1µF
C9
0.1 µ F
INH3
C10
22 pF
L6
12 0 n H
CFB3
18 nF
LO31R181
R191RFB3
274
C26
0.1 µF
C27
0.1 µ F
C21
0.1 µF
C22
0.1 µF
IN3
CFB4
18 nF
C11
0.1 µ F
L8
12 0 n H
C12
22 pF
C4
0.1 µF
RFB4
274
C32
0.1 µ F
C31
0.1 µF
LO41
R231
R221
+5V
C1 3
0.1 µF
L4
12 0 nH
C62
0.1 µF
C6 4
0.1 µF
R50
4.02k
C55
0.1 µF
+5V
VO2
L1 3
120 nH
L1 1
120 nH
RX4
100
RX3
100
VO 1
L10
12 0 nH
L9
12 0 nH
RX2
100
RX1
100
C75
0.1 µF
L12
120 nH FB
+5V
VO 3
L14
12 0 nH
L15
12 0 nH
RX5
100
RX6
100
VO 4
L16
12 0 nH
L17
12 0 nH
RX7
100
RX8
10 0
L34
120 nH
+5 V
C77
0.1 µF
+5V
CFB1
18 nF
C5
0.1 µF
INH1
L5
12 0 nH
C6
22 pF C1
0.1 µF
RFB1
274
C17
0.1 µ F
C16
0.1 µ F
LO11
R111
R1 01
+5
V
L1
12 0 n H
C67
0.1 µF
CLMP12
R49
4. 02k
C53
0.1 µF
C8 2
1nF
C59
0.1 µF
C57
0.1 µF
IN4
IN1
HI
LO
SLOPE
D
U
E
D
E
D
C8 0
1nF
+5 V
+5 V
28 29
GAIN34 GAIN34
+5
V
EN34
EN12
HIL O
+5V
+
C14
10 µF
GND1 GND2 GND3 GND6GND5GND4
ICR4
CR4
12
3
ICR3
CR3
12
3
ICR2
CR2
12
3
ICR1
CR1
12
3
CLMP34
NOTES
1 COMPONENTS IN GRAY ARE OPTIONAL USER SUPPLIED.
2 NC = NO CONNECT.
03199-124
AD8334
NC
Figure 115. AD8334-EVALZ Schematic
AD8331/AD8332/AD8334
Rev. G | Page 50 of 56
03199-125
NETWORK ANALYZER
PRECISION VOLTAGE
REFERENCE (FOR VGAIN)
GND
GND
GAIN
CONTROL
VOLTAGE
SIGNAL INPUT
DIFFERENTIAL PROBE
POWER SUPPLY
+5V
PROBE
POWER
SUPPLY
Figure 116. AD8334 Typical Board Test Connections (One Channel Shown)
AD8331/AD8332/AD8334
Rev. G | Page 51 of 56
AD8334 EVALUATION BOARD PCB LAYERS
03199-126
Figure 117. AD8334-EVALZ Primary Side Copper
0
3199-127
Figure 118. AD8334-EVALZ Secondary Side Copper
0
3199-128
Figure 119. AD8334-EVALZ Inner Layer 1Copper
03199-129
Figure 120. AD8334-EVALZ Inner Layer 2 Copper
AD8331/AD8332/AD8334
Rev. G | Page 52 of 56
03199-130
Figure 121. AD8334-EVALZ Component Side Silkscreen
AD8331/AD8332/AD8334
Rev. G | Page 53 of 56
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AE
28 15
141
SEATING
PLANE
C
OPLANARIT
Y
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
Figure 122. 28-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-28)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-137-AD
081908-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
20 11
101
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010 (0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25)
0.069 (1.75)
0.053 (1.35)
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
Figure 123. 20-Lead Shrink Small Outline Package (QSOP)
(RQ-20)
Dimensions shown in Inches and (millimeters
AD8331/AD8332/AD8334
Rev. G | Page 54 of 56
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
011708-A
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDI
C
ATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 124. 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50 BSC 0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
082908-B
SEATING
PLANE
PIN 1
INDICATOR
0.30
0.25
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 125. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
AD8331/AD8332/AD8334
Rev. G | Page 55 of 56
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8331ARQ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQ-REEL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQ-REEL7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQZ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQZ-RL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331ARQZ-R7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20
AD8331-EVALZ Evaluation Board with AD8331ARQ
AD8332ACP-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACP-REEL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACP-REEL7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACPZ-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACPZ-R7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ACPZ-RL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2
AD8332ARU –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARU-REEL7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARUZ –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARUZ-R7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332ARUZ-RL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28
AD8332-EVALZ Evaluation Board with AD8332ARU
AD8334ACPZ –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD8334ACPZ-REEL –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD8334ACPZ-REEL7 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD8334-EVALZ Evaluation Board with AD8334ACP
1 Z = RoHS Compliant Part.
AD8331/AD8332/AD8334
Rev. G | Page 56 of 56
NOTES
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03199-0-10/10(G)