IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) * Halogen-free According to IEC 61249-2-21 Definition * Surface Mount (IRFBF20S, SiHFBF20S) * Low-Profile Through-Hole (IRFBF20L, SiHFBF20L) * Available in Tape and Reel (IRFBF20S, SiHFBF20S) * Dynamic dV/dt Rating * 150 C Operating Temperature * Fast Switching * Fully Avalanche Rated * Compliant to RoHS Directive 2002/95/EC 900 RDS(on) () VGS = 10 V 8.0 Qg (Max.) (nC) 38 Qgs (nC) 4.7 Qgd (nC) 21 Configuration Single DESCRIPTION D I2PAK (TO-262) Third generation Power MOSFETs form Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capabel of the accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRFBF20L, SiHFBF20L) is available for low-profile applications. D2PAK (TO-263) G G D S S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free D2PAK (TO-263) SiHFBF20S-GE3 IRFBF20SPbF SiHFBF20S-E3 D2PAK (TO-263) SiHFBF20STRL-GE3a IRFBF20STRLPbFa SiHFBF20STL-E3a D2PAK (TO-263) SiHFBF20STRR-GE3a IRFBF20STRRPbFa SiHFBF20STR-E3a I2PAK (TO-262) SiHFBF20L-GE3 IRFBF20LPbF SiHFBF20L-E3 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted) PARAMETER Drain-Source Voltagee Gate-Source Voltagee Continuous Drain Current SYMBOL VDS VGS VGS at 10 V TC = 25 C TC = 100 C ID Pulsed Drain Currenta,e Linear Derating Factor IDM Single Pulse Avalanche Energyb, e Repetitive Avalanche Currenta Repetitive Avalanche Energya EAS IAR EAR Maximum Power Dissipation TC = 25 C TA = 25 C PD Peak Diode Recovery dV/dtc, e dV/dt Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Mounting Torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V; starting TJ = 25 C, L = 117 mH, Rg = 25 , IAS = 1.7 A (see fig. 12). c. ISD 1.7 A, dI/dt 70 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. e. Uses IRFBF20, SiHFBF20 data and test conditions. LIMIT 900 20 1.7 1.1 6.8 0.43 180 1.7 5.4 54 3.1 1.5 - 55 to + 150 300d 10 UNIT V A W/C mJ A mJ W V/ns C N * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91121 S11-1053-Rev. B, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, steady-state)a RthJA - 40 Maximum Junction-to-Case RthJC - 2.3 UNIT C/W Note a. When mounted on 1" square PCB ( FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 A 900 - - V VDS/TJ Reference to 25 C, ID = 1 mA - 1.1 - mV/C VGS(th) VDS = VGS, ID = 250 A 2.0 - 4.0 V nA Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance IGSS IDSS RDS(on) gfs VGS = 20 V - - 100 VDS = 900 V, VGS = 0 V - - 100 VDS = 720 V, VGS = 0 V, TJ = 125 C - - 500 VGS = 10 V ID = 1.0 Ab VDS = 50 V, ID = 1.0 Ab A - - 8.0 0.6 - - S - 490 - Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VGS = 10 V ID = 1.7 A, VDS = 360 V, see fig. 6 and 13b - 55 - - 18 - - - 38 - - 4.7 Gate-Drain Charge Qgd - - 21 Turn-On Delay Time td(on) - 8.0 - - 21 - - 56 - - 32 - Rise Time Turn-Off Delay Time Fall Time www.vishay.com 2 tr td(off) tf VDD = 450 V, ID = 1.7 A, Rg = 18 , VGS = 10 V, see fig. 10b pF nC ns Document Number: 91121 S11-1053-Rev. B, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT - - 1.7 - - 6.8 - - 1.5 - 350 530 ns - 0.85 1.3 C Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 C, IS = 1.7 A, VGS = 0 Vb TJ = 25 C, IF = 1.7 A, dI/dt = 100 A/sb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Uses IRFBF20/SiHFBF20 data and test conditions. TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Document Number: 91121 S11-1053-Rev. B, 30-May-11 Fig. 2 - Typical Output Characteristics www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 4 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91121 S11-1053-Rev. B, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature RD VDS VGS D.U.T. Rg + - VDD 10 V Pulse width 1 s Duty factor 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS Fig. 8 - Maximum Safe Operating Area td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Document Number: 91121 S11-1053-Rev. B, 30-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS VDS tp VDD Rg D.U.T. + - IAS V DD VDS 10 V tp 0.01 Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current www.vishay.com 6 Document Number: 91121 S11-1053-Rev. B, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBF20S, SiHFBF20S, IRFBF20L, SiHFBF20L Vishay Siliconix Current regulator Same type as D.U.T. 50 k QG 10 V 0.2 F 12 V 0.3 F QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer + - - Rg * * * * + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + - VDD Driver gate drive Period P.W. D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91121. Document Number: 91121 S11-1053-Rev. B, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0 to 8 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail "A" Rotated 90 CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Revision: 12-Mar-12 1 Document Number: 91000