2002 Microchip Technology Inc. Preliminary DS41190A
PIC12F629/675
Data Sheet
8-Pin FLASH-Based 8-Bit
CMOS Microcontrollers
M
DS41190A - page ii Preliminary 2002 Microchip Technology Inc.
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The Microchip name and logo, the Microchip logo, FilterLab,
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© 2002, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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design and wafer fabrication facilities in
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Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside t he operating specifications contained in the data sheet.
The person doing so may be engaged in th eft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
2002 Microchip Technology Inc. Preliminary DS41190A-page 1
MPIC12F629/675
Devices included in thi s Data Sheet:
High Performance RISC CPU:
•Only 35 instructions to learn
•All single cycle instructions (200 ns), except for
progra m bran ch es w hic h are two -cy c le
•Operati ng speed:
- DC - 20 MHz oscillator/clock input
- DC - 200 ns instruction cycle
•Memory
- 1024 x 14 words of FLASH Program Memory
- 64 x 8 by tes of Data Memory (SRAM)
- 128 x 8 bytes of EEPROM data memory
•Interrupt capability
•16 special function hardware registers
•8-level deep hardware stack
•Direct, Indirect, and Re lative Addressing mode s
Peripheral Feat ures:
•6 I/O pins with individual direction control
•High current sink/source for direct LED drive
•Analog comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CVREF) module
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
•Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
- Programmable 4-channel input
- Volta ge refe renc e inpu t
•Timer0: 8-bit timer/counter with 8-bit
progra mmable prescaler
•Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as T imer1 oscillator , if INTRC Oscill ator mode
selected
•64 by tes of general purpos e RAM
Pin Diagram
Special Microcontroller Features:
•Low power Power-on Reset (POR)
•Power-up Timer (PWRT) and Oscillator Start-up
Ti mer (OST)
•Low power Brown-out Detect (BOD)
•Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
•Multiplexed MCLR pin
•Interrupt-on-pin change
•Individual programmable weak pull-ups
•Programmable code protection
•Power saving SLEEP mode
•Select ab le os cil la t or options
- RC: External RC oscillator
- INTOSC: 4 MHz internal oscillator
- EC: External Clock input
- XT: Standard crystal/resonator
- HS: High speed crystal/resonator
- LP: Power saving, low frequency cryst al
•In-Circuit Serial Programming TM (ICSPTM) via
two pins
•Four user programmable ID locations
CMOS Technology:
•Low po wer, high speed C MOS F LASH technology
•Fully static design
•Wide operating voltage range
- PIC12F629/675 - 2. 0V to 5.5V
•Industrial and Extended temperature range
•Low power consumption
- < 1.0 mA @ 5.5V, 4.0 MHz
-20µA typical @ 2.0V, 32 kHz
-< 1.0µA typical standby curr ent @ 2.0V
* 8-bit, 8-pin devices protected by Microchip’s Lo w Pin Count Patent: U.S. Patent No. 5,847,450. Addi tional U.S. and
foreign patents and applications may be issued or pending.
•PIC12F629 •PIC12F675 8-Pin PDI P, SO IC
VSS
VDD
GP5/T1CKI/
GP4/T1G/
GP3/MCLR/VPP
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/
INT/COUT
1
2
3
45
6
7
8
PIC12F629
OSC1/CLKIN
OSC2/CLKOUT
8-Pin FLASH-Based 8-Bit CMOS Microcontroller
PIC12F629/675
DS41190A-page 2 Preliminary 2002 Microchip Technology Inc.
Pin Diagrams
8-pin PDIP, SOIC
VSS
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
1
2
3
45
6
7
8
PIC12F675
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
VSS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
8-pin MLF -S
5678
4321
PIC12F629
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
VSS
GP0/AN
0/
CIN+/ICSPDAT
GP1/AN1/CIN-/
V
REF
/
ICSPCLK
GP2/AN2/T0CKI/INT/COUT
5678
4321
PIC12F675
2002 Microchip Technology Inc. Preliminary DS41190A-page 3
PIC12F629/675
Table of Contents
1.0 Device Overview. ......................................................................................................................................................................... 5
2.0 Memory O rganization....................... .. ..........................................................................................................................................7
3.0 GPIO Port............................ .......................................................................................................................................................19
4.0 Timer0 Module ................................................................. . ................................. ........................................................................ 25
5.0 Timer1 Module with Gate Control............................................................................................................................................... 28
6.0 Comparator Module............................................. .. .... .... .. ......... .. .... .... .. ......... .... .. .... ....... ............................................................ 33
7.0 Analog-to-Digital Converter (A/D) Module (PIC 12F675 only)..................................................................................................... 39
8.0 Data EEPR OM Mem o ry ....................... ................... ................... ................... ................... .......................................................... 47
9.0 Speci a l Features of the CPU.................... ................... ................... ................... ................... ...................................................... 51
10.0 Instruction Set Summary............................................................................................................................................................ 69
11.0 Development Support. .................................................................................... ............................................................................ 77
12.0 Electrical Specifications.............................................................................................................................................................. 83
13.0 Pack a g in g In fo rmation........................ ................... ........................... ................... ..................................................................... 101
Appendix A: Data Sheet Revision History........................ .... ......... .... .... .. .... ......... .... .... .... ......... .... .................................................. 107
Appendix B: Device Differences......................................... .... ....... .... .. .... .. ......... .. .... .. .... .. ......... .. .................................................... 107
Appendix C: Device Migrations .............................................. ......... .. .... .... ......... .... .. .... .... ......... ...................................................... 108
Appendix D: Migrating from other PICmicro Devices............................ .. .... ......... .. .... .... .. ......... .. .... .... .. .......................................... 108
Appendix E: Development Tool Version Requirements................... ............................................................................................... 109
Index .................................................................................................................................................................................................. 111
On-Line Support ................. .... .... .. ......... .... .. .... .... ....... .... .. .... .... ....... .... .... .. .... ....... .... .... .. ................................................................... 115
Reader Response ........................... . ................................. ................................................................................................................ 116
Product Identific ation System ........................................................................................................................................................... 117
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PIC12F629/675
DS41190A-page 4 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 5
PIC12F629/675
1.0 DEVICE OVERVIEW
This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r
the PIC12F629/675. Additional information may be
found i n th e PIC microTM Mid-Range Referenc e Manua l
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be co nside red a c omple ment a ry docu me nt to thi s Dat a
Sheet, and is highly recom m end ed re adi ng for a bett er
understanding o f the d ev ic e arc hi tec ture a nd operation
of the peripheral modules.
The PIC12F629 and PIC12F675 devices are covered
by this Data Sheet. They are identical, except the
PIC12F675 has a 10-bit A/D converter. They come in
8-pin PDIP, SOIC, and MLF-S packages. Figure 1-1
shows a blo ck dia gram of th e PIC12F629 /675 de vices .
Table 1-1 shows the Pinout Description.
FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM
FLASH
Program
Memory
1K x 14
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
64 x 8
Direct Addr 7
Addr(1)
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start- up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
8
8
Brown-out
Reset
Timer0 Timer1
8
3
Timing
Generation
GP5/T1CKI/OSC1/CLKIN
Internal
4 MHz
RAM
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT
GP1/AN1/CIN-/VREF
GP0/AN0/CIN+
EE Data
Comparator Memory
10-bit A/D
(PIC12F675 only)
CVREF
Oscillator
Note 1: Higher order bits are from STATUS register.
PIC12F629/675
DS41190A-page 6 Preliminary 2002 Microchip Technology Inc.
TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
AN0 AN A/D Channel 0 input (PIC12F675 only)
CIN+ AN Comparator input
ICS PDAT TTL CMOS Serial programming I/O
GP1/AN1/CIN-/VREF/
ICSPCLK GP1 TTL CMOS Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
AN1 AN A/D Channel 1 input (PIC12F675 only)
CIN- AN Comparator input
VREF AN External voltage reference (PIC12F675 only)
ICSPCLK ST Serial pr ogramming cl ock
GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
AN2 AN A/D Channel 2 input (PIC12F675 only)
T0CKI ST TMR0 clock input
INT ST External interrupt
COUT CMOS Comparator output
GP3/MCLR/VPP GP3 TTL Input port w/ interrupt-on-change
MCLR ST Master Clear
VPP HV Programming voltage
GP4/AN3/T1G/OSC2/
CLKOUT
GP4 TTL CMOS Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
AN3 AN A/D Channel 3 input (PIC12F675 only)
T1G ST TMR1 gate
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN
GP5 TTL CMOS Bi-directional I/O w/ programmable pull-up and
interrupt-on-change
T1CKI ST TMR1 c lock
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/RC oscillator connection
VSS VSS Power Ground reference
VDD VDD Power Positive supply
2002 Microchip Technology Inc. Preliminary DS41190A-page 7
PIC12F629/675
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h - 03FFh)
for the PIC12F629/675 devices are physically imple-
mented. Accessing a location above these boundaries
will c ause a wra p around withi n the firs t 1K x 14 sp ac e.
The RESET vector is at 0000h and the interrupt vector
is at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F629/675
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose regis-
ters and the Special Function registers. The Special
Functio n registers are located in the first 32 lo cations of
each bank. Register locations 20h-5Fh are General
Purpose re giste rs, imp leme nted as st atic RAM and a re
mapped across both banks. All other RAM is unimple-
mented and returns ‘0’ when read. RP0 (STATUS<5>)
is the bank select bit.
•RP0 = 0 Bank 0 is selected
•RP0 = 1 Bank 1 is selected
2.2. 1 GENERAL PURP OSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either d irectly or i ndirec tly, through th e File Selec t Reg-
ister FSR (see Section 2.4).
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Note: The IRP and RP1 bits STATUS<7:6> are
reser ved and shoul d always be mai ntained
as ‘0’s.
PIC12F629/675
DS41190A-page 8 Preliminary 2002 Microchip Technology Inc.
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function registers
assoc iated with th e “core” are described in this sec tion.
Those related to the operation of the peripheral
features are desc ribed in the section of that peripheral
feature.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F 62 9/67 5
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented data memory locations, read as ’0’.
1: Not a physical register .
2: PIC12F675 only.
CMCON VRCON
General
Purpose
Registers accesses
20h-5Fh
64 Bytes
EEDATA
EEADR
EECON2(1)
5Fh
60h
File
Address File
Address
WPU
IOCB
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
DFh
E0h
ADRESH(2)
ADCON0(2)
EECON1
ADRESL(2)
ANSEL(2)
2002 Microchip Technology Inc. Preliminary DS41190A-page 9
PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset Page
Bank 0
00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 18,59
01h TMR0 Timer0 Module’s Register xxxx xxxx 25
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17
03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 11
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 18
05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 19
06h —Unimplemented — —
07h —Unimplemented — —
08h —Unimplemented — —
09h —Unimplemented — —
0Ah PCLATH ———Write Buffer for Upper 5 bits of Program Counter ---0 0000 17
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 15
0Dh —Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 28
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 28
10h T1CON —TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 30
11h —Unimplemented — —
12h —Unimplemented — —
13h —Unimplemented — —
14h —Unimplemented — —
15h —Unimplemented — —
16h —Unimplemented — —
17h —Unimplemented — —
18h —Unimplemented — —
19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 33
1Ah —Unimplemented — —
1Bh —Unimplemented — —
1Ch —Unimplemented — —
1Dh —Unimplemented — —
1Eh ADRESH(3) Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 40
1Fh ADCON0(3) ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 41,59
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
PIC12F629/675
DS41190A-page 10 Preliminary 2002 Microchip Technology Inc.
Bank 1
80h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 18,59
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12,26
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17
83h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC0001 1xxx 11
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 18
85h TRISIO — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 19
86h —Unimplemented — —
87h —Unimplemented — —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah PCLATH ———Write Buffer for Upper 5 bits of Program Counter ---0 0000 17
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 14
8Dh —Unimplemented — —
8Eh PCON ——————POR BOD ---- --0x 16
8Fh —Unimplemented — —
90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 16
91h —Unimplemented — —
92h —Unimplemented — —
93h —Unimplemented — —
94h —Unimplemented — —
95h WPU — — WPU5 WPU4 —WPU2 WPU1 WPU0 --11 1111 19
96h IOCB — — IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 --00 0000 20
97h —Unimplemented — —
98h —Unimplemented — —
99h VRCON VREN —VRR —VR3 VR2 VR1 VR0 0-0- 0000 38
9Ah EEDATA Data EEPROM Data Regist er 0000 0000 47
9Bh EEADR —Data EEPROM Address Register -000 0000 47
9Ch EECON1 ————WRERR WREN WR RD ---- x000 48
9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 48
9Eh ADRESL(3) Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 40
9Fh ANSEL(3) —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 42,59
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset Page
2002 Microchip Technology Inc. Preliminary DS41190A-page 11
PIC12F629/675
2.2.2.1 STATUS Register
The S TATUS re gi ste r, shown in Re gis ter 2-1, cont a ins :
•the arit hmetic status of the ALU
•the RESET status
•the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction wi th the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bits. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.
REGISTER 2-1: STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)
Note 1: Bits IRP a nd RP1 (ST ATUS<7:6>) are n ot
used by the PIC12F629/675 and should
be maintained as clear. Use of these bits
is not rec ommended, sinc e this may af fect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: This bit is reserved and should be maintained as ‘0’
bit 6 RP1: This bit is reserved and should be maintained as ‘0’
bit 5 RP0: Register Bank Select bit (used for direct addressing)
0 = Bank 0 (00h - 7Fh)
1 = Bank 1 (80h - FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 12 Preliminary 2002 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
•TMR0/WDT prescaler
•External GP2/INT inte rrup t
•TMR0
•Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, as sign the pre scale r to th e WDT b y
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 GPPU: GPI O Pull -up Enab le bit
1 = GPIO pull-ups are disab led
0 = GPIO pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Sourc e Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Presca ler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
2002 Microchip Technology Inc. Preliminary DS41190A-page 13
PIC12F629/675
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which cont ains the various en able and fl ag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
REGISTER 2-3: INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
Note: Interru pt flag bit s are set whe n an in terrupt
conditi on occurs, regardless of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 in terrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3 GPIE: Port Change Interrupt Enable bit
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(1)
1 = TMR0 reg ister has overflow ed (must be cl eared in software)
0 = TMR0 regist er did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
Note 1: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and
should be initialized before clearing T0IF bit.
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 14 Preliminary 2002 Microchip Technology Inc.
2.2.2.4 PIE1 Regist er
The PIE1 regis te r con t ai ns th e in terrupt enable bit s, a s
shown in Register 2-4.
REGISTER 2-4: PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIE ADIE — — CMIE — — TMR1IE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)
1 = Enables the A/D converte r interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator i nterrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 15
PIC12F629/675
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5: PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
Note: Interru pt fl ag bit s are se t w he n an in terru pt
conditi on occ urs , re gardless of the st a te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interr upt flag bit s are clear prio r to enab ling
an interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIF ADIF — — CMIF — — TMR1IF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 regist er did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 16 Preliminary 2002 Microchip Technology Inc.
2.2.2.6 PCON Regist er
The Power Control (PCON) register contains flag bits
to differentiate between a:
•Power-on Reset (POR)
•Brown-out Reset (BOR)
•Watchdog Timer Reset (WDT)
•External MCL R Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6: PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh)
2.2.2.7 OSCCAL Register
The Oscill ator Calibration register (OSCCAL) is used to
calibra te the inte rnal 4 MHz oscill ato r. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7: OSCCAL — OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
——————POR BOD
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOD: Brown-out Detect Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —
bit 7 bit 0
bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0 Unimplemented: Read as '0 '
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 17
PIC12F629/675
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from th e PCL register, which is a readabl e and
writable register. The high byte (PC<12:8>) is not
directly rea dable or wr itable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figur e 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> → PCH). The lower
example in Figure 2-3 shows how the PC is loaded dur-
ing a CALL or GOTO instruction (PCLA TH<4:3> → PCH).
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by adding a n offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256-byte block). Refer to the
Application Note “Implementing a Table Read"
(AN556).
2.3.2 STACK
The PI C12F629/675 family has an 8 level de ep x 13-b it
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the stack
pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL inst ruction is execut ed, or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE instruc-
tion execution. PCLATH is not affe cted by a PUSH or
POP operation.
The st ack operates as a circular buffer . This means that
after the stack has been PUSHed eight times, the ninth
push ove rwrite s the va lue tha t was s tored fro m the firs t
push. The tenth push ov erwr i tes the se co nd push (and
so on).
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interr upt add ress.
PIC12F629/675
DS41190A-page 18 Preliminary 2002 Microchip Technology Inc.
2.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the File Select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although STATUS bits may be affected). An
ef fective 9-bit add ress is obt ained by conc atenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESS ING
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F629/675
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
CONTINUE ;yes continue
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Data
Memory
Indirect AddressingDirect Addressing
Bank S elect Locat ion Sele c t
RP1(1) RP0 6 0
From Opcode IRP(1) FSR Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Not Used
2002 Microchip Technology Inc. Preliminary DS41190A-page 19
PIC12F629/675
3.0 GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled , some or all of the pins may not be a vailable as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
3.1 GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISIO. Setting a
TRISIO bit (= 1) will mak e th e co rres pon din g GPIO pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISIO bit (= 0) will
make the corresponding GPIO pin an output (i.e., put
the contents of the output latch on the selected pin).
The exception is GP3, which is input only and its TRIS
bit will always read as ‘1’. Ex ample 3-1 shows h ow to
initialize GPIO.
Readi ng the GPIO regis ter reads the st atus of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies th at the port pins are read,
this value is modified, and then written to the port data
latch. GP3 reads ‘0’ when MCLREN = 1.
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintai ned set when usin g them as analo g
inputs.
EXAMPLE 3- 1: INITIA LI ZING GPIO
3.2 Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an inter-
rupt-on-change option and every GPIO pin, except
GP3, has a w eak pu ll-u p op tio n. Th e next two secti on s
describe these functions.
3.2.1 WEAK PULL-UP
Each of the GPIO pins, ex cept GP3, has an indivi dually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-1.
Each we ak p ull -up is au tom at ica lly turned off when th e
port pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset by the GPPU bit
(OPTION<7>).
REGISTER 3-1: WPU — WEAK PULL-UP REGISTER (ADDRESS: 95h)
Note: Additional information on I/O ports may be
found i n the PICmicro™ M id-Range Refer-
ence Manual, (DS33023)
bcf STATUS,RP0 ;Bank 0
clrf GPIO ;Init GPIO
movlw 07h ;Set GP<2:0> to
movwf CMCON ;digital IO
bsf STATUS,RP0 ;Bank 1
movlw 0Ch ;Set GP<3:2> as inputs
movwf TRISIO ;and set GP<5:4,1:0>
;as outputs
bcf STATUS,RP0 ;Bank 0
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — WPU5 WPU4 —WPU2 WPU1 WPU0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global G PPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISIO = 0).
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 20 Preliminary 2002 Microchip Technology Inc.
3.2.2 INTERRUPT-ON-CHANGE
Each o f the GP IO pins i s individual ly configu rable as a n
interrupt-on-change pin. Control bits IOCBx enable or
disable the interrupt function for each pin. Refer to
Register 3-2. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
comp ared w ith the old value la tched on the last rea d of
GPIO. The ‘mismatch’ outputs of th e last read are OR' d
together to set, or clear, the GP Port Change Interrupt
flag bit (GPIF) in the INTCON register.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of GPIO. This will end the mis-
match condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
REGISTER 3-2: IOCB — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
Note: If a change on the I/O pin should occur
when th e read o peratio n is b eing ex ecuted
(start of the Q 2 cycle), then the GPIF int er-
rupt flag may not get set.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCB<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global i nterrupt e nable s (GIE a nd GPIE) m ust be enabl ed for in dividual int errupt s to
be recognized.
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 21
PIC12F629/675
3.3 Pin Descriptions and Diagrams
Each GPIO pin is multiplexed with other functions. The
pins and their combi ned f unc tio ns a re briefly de sc ribe d
here. For specific information about individual function s
such as the comparator or the A/D, refer to the appro-
priate section in this Data Sheet.
3.3.1 GP0/AN0/CIN+
Figure 3-1 shows the d iagram for th is pi n. The GP0 pi n
is configurable to function as one of the following:
•a general purpose I/O
•an analog input for the A/D (PIC12F675 only)
•an analog input to the comparator
3.3.2 GP1/AN1/CIN-/VREF
Figure 3-1 shows the d iagram for th is pi n. The GP1 pi n
is configurable to function as one of the following:
•as a g eneral pu rpose I/ O
•an analog input for the A/D (PIC12F675 only)
•an analog input to the comparator
•a voltage reference input for the A/D (PIC12F675
only)
FIGURE 3-1: BLOCK DIAGRAM OF GP0
AND GP1 PINS
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPU
RD
WPU
RD PORT
RD
PORT
WR
PORT
WR
TRIS
RD
TRIS
WR
IOCB
RD
IOCB
Interrupt-on-Change
To Com parato r
To A/D Converter
Analog
Input Mode
GPPU
Analog
Input Mode
PIC12F629/675
DS41190A-page 22 Preliminary 2002 Microchip Technology Inc.
3.3.3 GP2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the d iagram for th is pi n. The GP2 pi n
is configurable to function as one of the following:
•a general purpose I/O
•an analog input for the A/D (PIC12F675 only)
•a digital output from the comparator
•the cloc k input for TMR0
•an external edge triggered interrupt
FIGURE 3-2: BLOCK DIAGRAM OF GP2
3.3.4 GP3/MCLR/VPP
Figur e 3-3 shows th e diag ram for th is pin . T he GP3 pin
is configurable to function as one of the following:
•a general purpo se inp ut
•as Master Clear Reset
FIGURE 3-3: BLOCK DIAGRAM OF GP3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRIS
RD
TRIS
WR
IOCB
RD
IOCB
Interrupt-on-Change
To A/D Converter
0
1
COUT
COUT
Enable
To INT
To TMR0
Analog
Input Mode
GPPU
RD PORT
Analog
Input
Mode
I/O pin
VSS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORT
RD
PORT
WR
IOCB
RD
IOCB
Interrupt-on-Change
RESET MCLRE
RD
TRIS VSS
D
EN
Q
MCLRE
2002 Microchip Technology Inc. Preliminary DS41190A-page 23
PIC12F629/675
3.3.5 GP4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the d iagram for th is pi n. The GP4 pi n
is configurable to function as one of the following:
•a general purpose I/O
•an analog input for the A/D (PIC12F675 only)
•a TMR1 gate input
•a crystal/resonator connection
•a clock output
FIGURE 3-4: BLOCK DIAGRAM OF GP4
3.3.6 GP5/T1CKI/OSC1/CLKIN
Figur e 3-5 shows th e diag ram for th is pin . T he GP5 pin
is configurable to function as one of the following:
•a general purpo se I/O
•a TMR1 clock inp ut
•a cryst al/ resonator connectio n
•a clock input
FIGURE 3-5: BLOCK DIAGRAM OF GP5
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRIS
RD
TRIS
WR
IOCB
RD
IOCB
Interrupt-on-Change
FOSC/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog
Input Mode
GPPU
RD PORT
To TMR1 T1G
INTOSC/
EXTRC/EC1
(2)
CLK
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option .
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRIS
RD
TRIS
WR
IOCB
RD
IOCB
Interrupt-on-Change
To TMR1 or CLKGEN
INTOSC
Mode
RD PORT
INTOSC
Mode
GPPU
Oscillator
Circuit
OSC2
Note 1: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
(1)
TMR1LPEN
PIC12F629/675
DS41190A-page 24 Preliminary 2002 Microchip Technology Inc.
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Addres s Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 B it 0 Value on:
POR,
BOR
V alue on all
other
RESETS
05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISIO — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111
95h WPU — — WPU5 WPU4 —WPU2 WPU1 WPU0 --11 -111 --11 -111
96h IOCB — — IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 --00 0000 --00 0000
9Fh ANSEL —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by GPIO.
2002 Microchip Technology Inc. Preliminary DS41190A-page 25
PIC12F629/675
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
•8-bit ti mer/counter
•Readable and writable
•8-bit software programmable prescaler
•Internal or external clock select
•Interrupt on overflow from FFh to 00h
•Edge select for external clock
Figure 4-1 is a bloc k diagram o f the T imer0 mod ule and
the prescaler shared with the WDT.
4.1 Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule wi ll i ncr em en t ev ery ins truction cycle (w ith ou t pre s-
caler). If TMR0 is written, the increment is inhibited for
the follow i ng two ins truc t i on cy cl es . The us er can work
around this by writing an adjusted value to the TMR0
register.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by the source edge (T0SE) control bit
(OPTIO N_REG<4>). Clearing the T0SE bit selects the
rising edge.
4.2 Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0 regis-
ter timer/c ounter ov erflows from FFh to 00h. Thi s over-
flow s ets t he T 0 I F bit . T he in t er ru pt ca n be m as k ed by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is
shut-off during SLEEP.
FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note: Additional information on the Timer0
module is avail able in the PICmicroTM Mi d-
Range Re ference Manual, (DS33023).
Note: Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
PICmicroTM Mid-Range Reference
Manual, (DS33023).
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-out
PS0 - PS2
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE , T0CS, PSA, PS0-PS2 are bits in the Option register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
PIC12F629/675
DS41190A-page 26 Preliminary 2002 Microchip Technology Inc.
4.3 Using Timer0 with an External
Clock
When no pr escal er is used, t he ex tern al clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI, with the internal phase clocks, is accom-
plishe d by sampli ng the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necess ary for T0C KI to be hi gh for at leas t 2TOSC (and
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
REGISTER 4-1: OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 GPPU: GPI O Pull -up Enab le bit
1 = GPIO pull-ups are disab led
0 = GPIO pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Sourc e Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Presca ler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
2002 Microchip Technology Inc. Preliminary DS41190A-page 27
PIC12F629/675
4.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
select abl e via the PS2:PS0 b its (OPT ION_R EG<2:0 >).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
4.4.1 SWITCHING PRESCALE R
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET, the following instruction sequence
(Example 4-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 4-1: CHANGING PRESCALER
(TIMER0→WDT)
To change prescaler from the WDT to the TMR0
module , use the se quence sh own in Exa mple 4-2. This
preca ution mus t be tak en even if the WDT is dis abled.
EXAMPLE 4-2: CHANGING PRESCALER
(WDT→TIMER0)
TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0
bcf STATUS,RP0 ;Bank 0
clrwdt ;Clear WDT
clrf TMR0 ;Clear TMR0 and
; prescaler
bsf STATUS,RP0 ;Bank 1
movlw b’00101111’ ;Required if desired
movwf OPTION_REG ; PS2:PS0 is
clrwdt ; 000 or 001
;
movlw b’00101xxx’ ;Set postscaler to
movwf OPTION_REG ; desired WDT rate
bcf STATUS,RP0 ;Bank 0
clrwdt ;Clear WDT and
; postscaler
bsf STATUS,RP0 ;Bank 1
movlw b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
movwf OPTION_REG ;
bcf STATUS,RP0 ;Bank 0
Addr e s s N a m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Value on
POR
Value on
all other
RESETS
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISIO — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Timer0 module.
PIC12F629/675
DS41190A-page 28 Preliminary 2002 Microchip Technology Inc.
5.0 TIMER1 MODULE WITH GATE
CONTROL
The PIC12F629/675 devices have a 16-bit timer.
Figure 5-1 shows the basic block diagram of the T imer1
module. Timer1 has the following features:
•16-bit timer/counter (TMR1H:TMR1L)
•Readable and writable
•Internal or external clock selection
•Synchronous or asynchronous operation
•Interrupt on overflow from FFFFh to 0000h
•Wake-up upon overflow (Asynchronous mode)
•Optional external enable input (T1G)
•Optional LP oscillator
The Timer1 Control register (T1CON), shown in
Register 5-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
FIGURE 5-1: TIMER1 BLOCK DIAGRAM
Note: Additional information on timer modules is
available in the PICmicroTM Mid-Range
Reference Manual, (DS33023).
TMR1H TMR1L
LP Oscillator T1SYNC
TMR1CS
T1CKPS<1:0> SLEEP Input
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
0
1
Synchronized
Clock Input
2
OSC1
OSC2
Set Flag bit
TMR1IF on
Overflow
TMR1
TMR1ON
TMR1GE
TMR1ON
TMR1GE
INTOSC
T1OSCEN
LPEN
w/o CLKOUT
T1G
2002 Microchip Technology Inc. Preliminary DS41190A-page 29
PIC12F629/675
5.1 Timer1 Modes of Operation
Timer1 can operate in one of three modes:
•16-bit timer with prescaler
•16-bit synchronous counter
•16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every instruc-
tion cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized
to the microcontroller system clock or run asynchro-
nously.
In Count er and Timer modul es , the c oun ter/timer clock
can be gated by the T1G input.
If an external clock os ci lla tor is ne eded (and the m ic ro-
controller is using the INTRC w/o CLKOUT), Timer1
can use the LP oscillator as a clock source.
5.2 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the inter rupt on rollo ver , you m ust set th ese bits :
•Timer1 interrupt Enab le bit (PIE1< 0>)
•PEIE bit (INTCON<6>)
•GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The pres-
cale counter is not directly readable or writable; how-
ever, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
FIGURE 5-2: TIMER1 INCREMENTING EDGE
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incr em enti ng ris ing edge.
Note: The T MR1H:TTMR1L regi st er pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter in crem ents.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
PIC12F629/675
DS41190A-page 30 Preliminary 2002 Microchip Technology Inc.
REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if T1G pin is low
0 = Timer1 is on
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Inpu t Clock Prescal e Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1 TMR1CS: Timer 1 Cloc k Source Select bit
1 = External clock from T1OSO/T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 31
PIC12F629/675
5.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the exte rnal
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read /write the timer (Sec tion 5.4.1).
5.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user shoul d keep i n mind that r eadi ng the 16-b it time r
in two 8-b it va lu es i t self, poses cert a in pro bl em s, s inc e
the timer may overflow between the reads.
For write s, it is re commend ed that the us er simply stop
the timer and w rite the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. Exam-
ples 1 2-2 an d 12-3 in the PIC micro™ Mid-Rang e MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
5.5 Timer1 Oscillator
A cryst al osci llator circ uit is buil t-in betw een pins OSC 1
(input) and OSC2 (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 osci llator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the syste m LP oscillat or, the user mu st provid e
a software time delay to ensure proper oscillator
start-up.
T ABLE 5-1: CAPACITOR SELECTION FOR
THE TIM ER1 OSCILLATOR
5.6 Timer1 Operation During SLEEP
Timer1 can only operate during SLEEP when setup in
Asynchronous Counter mo de. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
•Timer1 must be on (T1CON<0>)
•TMR1IE bit (PIE1<0>) must be set
•PEIE bit (INTCON<6> ) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON< 7 >) is se t, the de vi ce wil l wa ke -up an d jum p
to the Interrupt Service Routine on an overflow.
TABLE 5-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Note: The oscilla tor requi res a st art-up and s tabi-
lization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since eac h reso nato r/crystal ha s its own
charact eristics , the user sho uld cons ult the
resonator/crystal manufacturer for appro-
priate values of external components.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Val ue on
POR
Value on
all other
RESETS
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
PIC12F629/675
DS41190A-page 32 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 33
PIC12F629/675
6.0 COMPARATOR MODULE
The PI C12F629/675 devi ces hav e one anal og comp ar-
ator. The inputs to the co mparator are mul tip lex ed wi th
the GP0 and GP1 pins. There is an on-chip Compara-
tor Voltage Reference that can also be applied to an
input of t he compa rator . In add ition, GP2 ca n be config-
ured as the comparator output. The Comparator Con-
trol Register (CMCON), shown in Register 6-1,
contains the bits to control the comparator.
REGISTER 6-1: CMCON — COMPARATOR CONTROL REGISTER (ADDRESS: 19h)
U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—COUT —CINV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 COUT: C ompara tor Output bit
When CINV = 0:
1 = VIN+ > VIN–
0 = VIN+ < VIN–
When CINV = 1:
0 = VIN+ > VIN–
1 = VIN+ < VIN–
bit 5 Unimplemented: Read as ‘0’
bit 4 CINV: Comparator Output Inversion bi t
1 = Output inverted
0 = Output not inverted
bit 3 CIS: Comparat or In put Switch bit
When CM2:CM0 = 110 or 101:
1 = VIN– connects to CIN+
0 = VIN– connects to CIN-
bit 2-0 CM2:CM0: Comparator Mode bits
Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 34 Preliminary 2002 Microchip Technology Inc.
6.1 Comparator Operation
A single comparator is shown in Figure 6-1, along with
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN–, the output of the
comp arator is a d igital low le vel. Whe n the an alog inp ut
at VIN+ is gr eater than the anal og input VIN–, the outp ut
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 6-1
represent the uncertainty due to input offsets and
response time.
The polarity of the comparator output can be inverted
by setting the CINV bit (CMCON<4>). Clearing CINV
results in a non-inverted output. A complete table
showing the output state versus input conditions and
the polarity bit is shown in Table 6-1.
TABLE 6-1: OUTPUT STATE VS. INPUT
CONDITIONS
FIGURE 6-1: SINGLE COMPARATOR
Note: To use AN<3:0> as analog inputs, the
appropriate bits must be programmed in
the ANSEL register.
Input Conditions CINV COUT
VIN- > VIN+00
VIN- < VIN+01
VIN- > VIN+11
VIN- < VIN+10
Output
VIN-
VIN+
Output
+
–
VIN+
VIN–
Note: CINV bit (CMCON<4>) is clear.
2002 Microchip Technology Inc. Preliminary DS41190A-page 35
PIC12F629/675
6.2 Comparator Configuration
There are eigh t mod es of operat ion fo r the c omp arato r.
The CMCON register , shown in Register 6-1, is used to
select the mode. Figure 6-2 shows the eight possible
modes. The TR ISIO regis ter co ntrols the data directio n
of the comparator pins for each mode. If the compara-
tor mode is changed, the comparator output level may
no t be v al i d for a specified period of time. Refer to the
specifications in Section 12.0.
FIGURE 6-2: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a comparator mode change. Other-
wise, a false interrupt may occur.
Comparator Reset (POR Default Value - low powe r) Comparator Off (Lowest power)
CM2:CM0 = 000 CM2:CM0 = 111
Compara tor w itho ut Ou tput Compara tor w/ o Outp ut and with Interna l Referen ce
CM2:CM0 = 010 CM2:CM0 = 100
Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output
CM2:CM0 = 011 CM2:CM0 = 101
Comparator with Output Multiplexed Input with Internal Reference
CM2:CM0 = 001 CM2:CM0 = 110
A = Analog Input, ports always reads ‘0’
D = Digital Input
CIS = Comparator Input Switch (CMCON<3>)
GP1/CIN-
GP0/CIN+ Off (Read as ’0’)
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+ Off (Read as ’0’)
D
D
GP2/COUT D
GP1/CIN-
GP0/CIN+ COUT
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+ COUT
A
D
GP2/COUT D From CVREF Module
GP1/CIN-
GP0/CIN+ COUT
A
D
GP2/COUT D
From CVREF Module
GP1/CIN-
GP0/CIN+ COUT
A
A
GP2/COUT D
From CVREF Module
CIS = 0
CIS = 1
GP1/CIN-
GP0/CIN+ COUT
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+ COUT
A
A
GP2/COUT D
From CVREF Module
CIS = 0
CIS = 1
PIC12F629/675
DS41190A-page 36 Preliminary 2002 Microchip Technology Inc.
6.3 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betwee n
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 6-3: ANALOG INPUT MODE
6.4 Comparator Output
The comparator output, COUT, is read through the
CMCON re gis ter. This bit is r ead only. T he comparator
output may also be directly output to the GP2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of th ese mo des, th e output on
GP2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
The TRISIO<2> bit functions as an output enable/
disable for the GP2 pin while the comparator is in an
output mode.
FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
VA
Rs < 10K
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
Leakage
±500 nA
Vss
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to Various Junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Anal og Voltage
Note 1: When reading the GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
TTL input specification.
2: Analog le vels on any pin that is defined as
a digital input, may ca us e t he in put buffer
to consume more current than is
specified.
To GP2/T0CKI pin
RD CMCON
Set CMIF bit
RESET
To Data Bus
CINV
CVREF
D
EN
Q
D
EN
Q
RD CMCON
GP1/CIN-
GP0/CIN+
CM2:CM0
2002 Microchip Technology Inc. Preliminary DS41190A-page 37
PIC12F629/675
6.5 Comparator Reference
The com parator m od ule al so allows the se lec tio n of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON regi ster, Register 6-2, contro ls the v olt age ref-
erence module shown in Figure 6-5.
6.5.1 CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
The follow ing equati ons determi ne the output vo ltages :
VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD
VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x
VDD / 32)
6.5.2 VOLTAGE REFERENCE
ACCURACY/ERROR
The full range of VSS to VDD cannot be realized due to
the cons truction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CV REF from approach ing VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the Comparator Voltage
Referenc e can be found in Section 12.0.
FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
6.6 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-4).
6.7 Operation Duri ng SLEEP
Both the comparator and voltage reference, if enabled
before entering SLEEP mode, remain active during
SLEEP. This results in higher SLEEP currents than
shown in the power-down specifications. The addi-
tional current consumed by the comparator and the
voltage reference is shown separately in the specifica-
tions. To minimize power consumption while in SLEEP
mode, turn off the comparator, CM2:CM0 = 111, and
voltage reference, VRCON<7> = 0.
While the comparator is enabled during SLEEP, an
interrupt will wake-up the device. If the device wakes
up from SLEEP, the contents of the CMCON and
VRCON registers are not affected.
6.8 Effects of a RESET
A device RESET forces the CMCON and VRCON reg-
isters to their RESET states. This forces the compara-
tor module to be in the Comparator Reset mode,
CM2:CM0 = 000 and the voltage reference to its off
state. Thus, all potential inputs are analog inputs with
the comparator and voltage reference disabled to con-
sume the smallest current possible.
VRR
8R
VR3:VR0
16-1 Analog
8RRR RR
CVREF to
16 Stages
Comparator
Input
VREN
VDD
MUX
PIC12F629/675
DS41190A-page 38 Preliminary 2002 Microchip Technology Inc.
REGISTER 6-2: VRCON — V OLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
6.9 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a '1' to this register, a
simulated interrupt may be initiated.
The CMIE bit (PIE1<3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, th e interrupt is not enabled, th ough the
CMIF bit wil l stil l be se t if an inter r upt co nd itio n occ urs .
The user , in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.
Readi ng C M CO N will end the mismatc h c on dition, and
allow flag bit CMIF to be cleared.
TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN —VRR —VR3 VR2 VR1 VR0
bit 7 bit 0
bit 7 VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain
bit 6 Unimplemented: Read as '0'
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as '0'
bit 3-0 VR3:VR0: CVREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: If a change in the CMCON register (COUT)
should occur when a read operation is
being exe cuted (start of the Q2 cycle), then
the CMIF (PIR1<3>) in terrupt flag may not
get set.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
all other
RESETS
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
85h TRISIO — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111
99h VRCON VREN —VRR —VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
2002 Microchip Technology Inc. Preliminary DS41190A-page 39
PIC12F629/675
7.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
The analo g-to-digital converter (A/D) allows conversion
of an analog input signal to a 10-bit binary representa-
tion of that signal. The PIC12F675 has four analog
inputs, multiplexed into one sample and hold circuit.
The output of the sample and hold is connected to the
input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-1
shows th e block diagram o f the A/D on the PIC12 F675.
FIGURE 7-1: A/D BLOCK DIAGRAM
7.1 A/D Configuration and Operation
There are two registers available to control the func-
tionality of the A/D module:
1. ADCON0 (Register 7-1)
2. ANSEL (Register 7-2)
7.1.1 ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high impedance state. Likewise, set the corre-
sponding ANS bit to disable the digital input buffer.
7.1.2 CHANNEL SELECTION
There are four analog channels on the PIC12F675,
AN0 through AN3. The CHS1:CHS0 bits
(ADCON0<3 :2>) control w hich channel is co nnected to
the sample and hold circuit.
7.1.3 VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converte r: either VDD is used, or an ana log volt age
applied to VREF is used. The VCFG bit (ADCON0<6>)
controls the volta ge reference s election. If VCFG is set,
then the voltage on the VREF pin is the reference; oth-
erwise, VDD is t he reference.
7.1.4 CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
•FOSC/2
•FOSC/4
•FOSC/8
•FOSC/16
•FOSC/32
•FOSC/64
•FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be se lected to ensure a mi nimum TAD of
1.6 µs. Table 7-1 shows a few TAD calculations for
selected frequencies.
GP0/AN0
ADC
GP1/AN1/VREF
GP2/AN2
GP4/AN3
VDD
VREF
ADON
GO/DONE
VCFG = 1
VCFG = 0
CHS1:CHS0
ADRESH ADRESL
10
10
ADFM
VSS
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
PIC12F629/675
DS41190A-page 40 Preliminary 2002 Microchip Technology Inc.
TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES
7.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is
complete, the A/D module:
•Clears the GO/DONE bit
•Sets the ADIF flag (PIR1<6>)
•Generates an interrupt (if enabled).
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
register s wil l not be u pdated with the p ar tiall y comple te
A/D conversion sample. Instead, the
ADRESH:ADRESL registers wi ll re t ain th e va lue of the
previous conversion. After an aborted conversion, a
2T
AD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
7.1.6 CONVERSION OUTPUT
The A/D con version can be su pplied in two format s: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the outpu t format. Figure 7-2 shows the ou tput formats.
FIGURE 7-2: 10-BIT A/D RESULT FORMAT
A/D Clock Source (TAD) Device Frequ ency
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 µs
4 TOSC 100 200 ns(2) 800 ns(2) 1.0 µs(2) 3.2 µs
8 TOSC 001 400 ns(2) 1.6 µs2.0 µs6.4 µs
16 TOSC 101 800 ns(2) 3.2 µs4.0 µs12.8 µs(3)
32 TOSC 010 1.6 µs6.4 µs8.0 µs(3) 25.6 µs(3)
64 TOSC 110 3.2 µs12.8 µs(3) 16.0 µs(3) 51.2 µs(3)
A/D RC x11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during SLEEP.
Note: The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7bit 0bit 7bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB
bit 7bit 0bit 7bit 0
Unimplemented: Read as ‘0 10-bit A/D Result
2002 Microchip Technology Inc. Preliminary DS41190A-page 41
PIC12F629/675
REGISTER 7-1: ADCON0 — A/D CONTROL REGIS TER (ADDRESS: 1Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG — — CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
bit 7 ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6 VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-4 Unimplemented: Read as zero
bit 3-2 CHS1:CHS0: Analog Channel Select bits
00 = Channel 00 (AN0)
01 = Channel 01 (AN1)
10 = Channel 02 (AN2)
11 = Channel 03 (AN3)
bit 1 GO/DONE: A/D Conversion Status bi t
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversi on cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: A/ D Convers io n Statu s bit
1 = A/D converter module is operating
0 = A/D converter is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 42 Preliminary 2002 Microchip Technology Inc.
REGISTER 7-2: ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
—ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’.
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0 ANS3:ANS0: Analog Select bits
(Between analog or digital function on pins AN<3:0>, respectively.)
0 = Digital I/O; pin is assigned to port or special function
1 = Analog input; pin is assigned as analog input(1)
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-up s, and interrup t-on-change. The corresponding TRISIO bi t must be s et
to Input mode in order to allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 43
PIC12F629/675
7.2 A/D Acquisiti on Requirements
7.2.1 RECOMMENDED SOURCE
IMPEDANCE
The maximum recommended impedance for ana-
log sources is 2.5 kΩ. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be varied by more than 1/4 LSb or
250 µV due to leakage. This places a requirement on
the input impedance of 250 µV/100 nA = 2.5 kΩ.
7.2.2 SAMPLING TIME CALC ULATION
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog in put model is shown in Figure 7-3. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
select ed (chang ed), th is sampli ng mus t be don e before
the conversion can be started.
To calculate the minimum sampling time, Equation 7-1
may be used. This equation assume s that 1/4 LSb error
is used (4096 steps for the A/D). The 1/4 LSb error is
the maximum error allowed for the A/D to meet its spec-
ified resolution.
The CHOLD is assumed to be 25 pF for the 10-bit A/D.
FIGURE 7-3: ANALOG INPUT MODEL
CPIN
VA
Rs Port Pin
5 pF
VDD
VT = 0.6 V
VT = 0.6 V ILEAKAGE
RIC @ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
6V
Sampling Switch (RSS)
5V
4V
3V
2V
567891011
(kW)
VDD
± 100 nA
Legend CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnec t resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
PIC12F629/675
DS41190A-page 44 Preliminary 2002 Microchip Technology Inc.
EQUATION 7-1: A/D SAMPLING TIME
Example 7-1 shows the calculation of the minimum
time required to charge CHOLD. This calculation is
based on the following system assumptions:
CHOLD = 25 pF
RS = 2.5 kW
1/4 LSb error
VDD = 5V → RSS = 10 kΩ (worst case)
Temp (system max.) = 50°C
EXAMPLE 7-1: CALCULAT ING THE
MINIMUM REQUIRED
SAMPLE TIME
VHOLD VREF VREF
4096
-------------–
VREF()1e
TC–
CHOLD
------------------ RIC RSS RS++()
–
⋅==
TCCHOLD 1kΩRSS RS++()In 1
4096
------------
–=
VREF 11
4096
------------–
VREF 1e
TC–
CHOLD
------------------ RIC RSS RS++()
–
⋅=
TACQ = Amplifier Settling Time
+ Holding Capacit or Charging Time
+ Temp erature Offset †
TACQ =5 µs
+ TC
+ [(Temp - 25°C)(0.05 ms /°C)] †
TC= Holding Capacitor Cha rging Time
TC=(CHOLD) (RIC + R SS + RS) In (1/40 96)
TC= -25 pF (1 kΩ +1 0 k Ω + 2. 5 kΩ) In (1/4096)
TC= -25 pF (13.5 kΩ) In (1/4096 )
TC= -0.338 (-9.70 4)µs
TC=3.3 µs
TACQ =5 µs
+ 3.3 µs
+ [(50°C - 25°C)(0.05 µs / °C)]
TACQ =8.3 µs + 1. 25 µs
TAC = 9.55 µs
†The temperature coefficient is only required for
temperatures > 25°C.
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maxim um rec omm ended impedanc e
for analog sources is 2.5 kΩ. This is
required to meet the pin leakage spec ifi-
cation.
4: After a conversion has completed, you
must wait 2 TAD time before sam pling ca n
begin aga in. During this time, the hol ding
capa citor is n ot connected to the sele cted
A/D input channel.
2002 Microchip Technology Inc. Preliminary DS41190A-page 45
PIC12F629/675
7.3 A/D Operation During SLEEP
The A/D converter module can operate during SLEEP.
This requires the A/D clock source to be set to the inter-
nal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the co nve rsion . This allo ws the SLEEP in struc tion t o b e
execut ed, thus eliminating m uch of the switchin g noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D inter-
rupt is enab led, the d evice aw akens f rom SL EEP. If th e
A/D interrupt is not enabled, the A/D module is turned
of f, alt hou gh the AD ON bit remains set.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4 Effects of RESET
A device RESET forces all registers to their RESET
state . Thus th e A/D modu le is tu rned of f and any pen d-
ing conv ersion is aborte d. The ADRESH :ADRESL reg-
isters are unchanged.
TABLE 7-2: SUMMARY OF A/D REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
RESETS
05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx --uu uuuu
0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
1Eh ADRESH Most Significant 8 bi t s of the Lef t Shif ted A/D resu lt or 2 bi t s of the Rig ht Shif ted Resul t xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO ADON 00-- 0000 00-- 0000
85h TRISIO — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
9Eh ADRESL Least Sig nifi cant 2 bi ts of the L eft Shift ed A/ D Result or 8 bits of the Ri ght Shi fte d Resul t xxxx xxxx uuuu uuuu
9Fh ANSEL —ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplem ented read as '0'. Shaded cells are not used for A /D conv erter module.
PIC12F629/675
DS41190A-page 46 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 47
PIC12F629/675
8.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during norma l operation (full VDD range). This memo ry
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
•EECON1
•EECON2 (not a physically implemented register)
•EEDATA
•EEADR
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC12F629/675 devices have 128
bytes of dat a EEPROM w ith an add res s ra nge from 0h
to 7Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the n ew data (erase be fore write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
When the data memory is code protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
Additional information on the Data EEPROM is avail-
able in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 8-1: EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah)
REGISTER 8-2: EEADR — EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
bit 7-0 EEDATn: Byte va lue to write to or read from Data EEPROM
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit 7 bit 0
bit 7 Unimplemented: Should be set to '0'
bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC12F629/675
DS41190A-page 48 Preliminary 2002 Microchip Technology Inc.
8.1 EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The upper bit should always be ‘0’ to remain upward
compa tible with devices that have more d ata EEPROM
memory.
8.2 EECON1 AND EECON2
REGISTERS
EECON1 is the control register with four low order bits
physically implemented. The upper four bits are non-
implemented and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prev ents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On powe r-up, the WR EN bit is clear. T he WRERR bi t is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Res et during normal oper a-
tion. In th ese s ituatio ns, follo wing RESET, the user ca n
check the WRERR bit, clear it, and rewrite the location.
The data and address will be cleared, therefore, the
EEDATA and EEADR registers will need to be re-
initialized.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
REGISTER 8-3: EECON1 — EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
— — — — WRERR WREN WR RD
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 =A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD detect)
0 =The write operation completed
bit 2 WREN: EEPROM Writ e Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control b it
1 =Initiates a write cyc le (Th e bit is cleared by hardware once write is complet e. The WR bit
can only be set, not cleared, in software.)
0 =Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 49
PIC12F629/675
8.3 READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 8-1. The data
is available, in the very next cycle, in the EEDATA reg-
ister. Therefore, it can be read in the next instruction.
EEDAT A hol ds this val ue until an other read, or until it is
written to by the user (during a write operation).
EXAMPLE 8-1: DATA EEPROM READ
8.4 WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required s equence . Any number th at is not equa l to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this writ e cycle. T he WR bit will
be inhibi ted from bei ng s et u nless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPL E 8- 3: W RIT E V ER IFY
8.5.1 MAXIMIZING ENDURANCE
For applications that will exceed 10% of the minimum
specified cell endurance (parameters D120, D120A,
D130, a nd D130 A), ev ery lo ca tio n s hou ld be re fres he d
within interv als no t exce eding 1/10 of t his sp ecifi ed cel l
enduranc e. Please refer to AN790 (DS007 90) for more
details.
8.6 PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been buil t in. On power-u p, WREN is cleare d. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The writ e in iti ate sequence and the WREN bi t tog eth er
help prevent an accidental write during:
•brown-out
•power glitch
•software malfunction
bsf STATUS,RP0 ;Bank 1
movlw CONFIG_ADDR ;
movwf EEADR ;Address to read
bsf EECON1,RD ;EE Read
movf EEDATA,W ;Move data to W
bsf STATUS,RP0 ;Bank 1
bsf EECON1,WREN ;Enable write
bcf INTCON,GIE ;Disable INTs
movlw 55h ;Unlock write
movwf EECON2 ;
movlw AAh ;
movwf EECON2 ;
bsf EECON1,WR ;Start the write
bsf INTCON,GIE ;Enable INTS
Required
Sequence
bcf STATUS,RP0 ;Bank 0
: ;Any code
bsf STATUS,RP0 ;Bank 1 READ
movf EEDATA,W ;EEDATA not changed
;from previous write
bsf EECON1,RD ;YES, Read the
;value written
xorwf EEDATA,W
btfss STATUS,Z ;Is data the same
goto WRITE_ERR ;No, handle error
: ;Yes, continue
PIC12F629/675
DS41190A-page 50 Preliminary 2002 Microchip Technology Inc.
8.7 DATA EEPROM OPERATION
DURING CODE PROTECT
Data me mory can be code prot ected by program ming
the CPD bit to ‘0’.
When the data memory is code protected, the CPU is
able to read and write data to the Data EEPR OM. It is
recommended to code protect the program memory
when c ode protec ting dat a memory. This preve nts an y-
one from programming zeroes over the existing code
(which will execute as NOPs) to rea ch an added rou tine,
programmed in unused program memory, which out-
puts the contents of data memory. Programming
unused locations to ‘0’ will also help prevent data mem-
ory code protection from becoming breached.
TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-on
Reset
Value on all
other
RESETS
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000
9Bh EEADR —EEPROM Address Register -000 0000 -000 0000
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000
9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by Data EE PROM m odule.
Note 1: EEC ON 2 is not a physical register.
2002 Microchip Technology Inc. Preliminary DS41190A-page 51
PIC12F629/675
9.0 SPECIAL FEATURES OF THE
CPU
Certain special circuits that deal with the needs of real
time applications are what sets a microcontroller apart
from other pro ce ssors . The PIC12 F629/675 family has
a host of such features intended to:
•maximize sy stem reliability
•minimi ze cost through elimination of external
components
•provide power saving operating modes and offer
code protection.
These features are:
•Oscillato r selection
•RESET
- Power-on Reset (PO R)
- Power-up Timer (PWRT)
- Oscillator Start-Up Timer (OST)
- Brown-out Reset (BO R)
•Interrupts
•Watchdog Timer (WDT)
•SLEEP
•Code protection
•ID Locations
•In-Circuit Serial Programming
The PIC12F629/675 has a Watchdog Timer that is
controlled by configuration bits. It runs off its own RC
oscill ator for ad ded reli abili ty. There are two ti mers th at
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Pow er-up Timer (PWR T), which provide s a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-ou t occurs, which ca n provide at least
a 72 ms RESET. With these three functions on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode . The use r can wake-u p from
SLEEP through:
•External RESET
•Watchdog Timer wake-up
•An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select various options (see Register 9-1).
PIC12F629/675
DS41190A-page 52 Preliminary 2002 Microchip Technology Inc.
9.1 Configuration Bits
The conf iguration bits can be programmed (read as ’0’),
or left unprogrammed (read as ’1’) to select various
device configurati ons, as shown in Regi ster 9-1. These
bits are mapped in program memory location 2007h.
REGISTER 9-1: CONFIG — CONFIGURATION WORD (ADDRESS: 2007h)
Note: Address 2007h is beyond the user program
memory space. It belongs to the special con-
figuration memory space (2000h - 3FFFh),
which can be accessed only during program-
ming. See PIC12F629/675 Programming
Specification for more information.
R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
BG1 BG0 ———CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0
bit 13 bit 0
bit 13-12 BG1:BG0: Bandgap Calibration bits(1)
00 = Lowest bandgap voltage
11 = Highest bandgap voltage
bit 11-9 Unimplemented: Read as ‘0’
bit 8 CPD: Data Code Protecti on bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 7 CP: Code Protection bit(3)
1 = Program Memory code protection is disabled
0 = Program Memory code protection is enabled
bit 6 BODEN: Brown-out Detect Enable bit(4)
1 = BOD enabled
0 = BOD disabled
bit 5 MCLRE: GP3/MCLR pin function select(5)
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKO UT pin, I/O function on GP5/OSC1/CLKIN
011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crys t al /res ona tor on GP4 /OSC 2 /CLKO UT and GP5 /O SC 1/CLKI N
000 = LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing
the device.
2: The entire data EEPROM will be erased when the c ode protection is turned off.
3: The entire program EEPROM will be erased, including OSCCAL value, when the code protection is
turned off.
4: Enabling Brown-out Reset does not automatically enable Power-Up Timer.
5: When MC LR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
P = Programmed using ICSP
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc. Preliminary DS41190A-page 53
PIC12F629/675
9.2 Oscillator Configurations
9.2.1 OSCILLA T OR TYPES
The PIC12F629/675 can be operated in eight different
oscillator option modes. The user can program three
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
•LP Low Power Crystal
•XT Crystal/Resonator
•HS High Speed Crystal/Resonator
•RC Extern al Resi stor/Capacito r (2 modes)
•INTO SC Intern al Osci ll ator (2 modes )
•EC External Clock In
9.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (see Figure 9-1). The PIC12F629/675 oscil-
lator design requires the use of a parallel cut crystal.
Use of a series cut crystal may yield a frequency out-
side of the crystal manufacturers specific ations. When
in XT, LP or HS modes, the de vice can have an external
clock source to drive the OSC1 pin (see Figure 9-2).
FIGURE 9-1: CRYST AL OPERATION (OR
CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
FIGURE 9-2: EXTERNAL CLOCK INPUT
OPERAT ION (HS, XT, EC,
OR LP OSC
CONFIGURATION)
T ABLE 9-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
T ABLE 9-2: CAPACITOR SELECTION FOR
CRYST AL OSCILLATOR
Note: Additional information on oscillator config-
urations is availab le in the PICmi croTM Mid-
Range Re ference Manual, (DS33023).
Note 1: See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
2: A series resistor may be required for AT strip cut
crystals.
3: RF varies with the oscillator mode selected
(Approx. value = 10 MΩ).
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3) SLEEP
To Internal
PIC12F629/675
Logic
RS(2)
Ranges Char ac teriz ed:
Mode Freq OSC1(C1) OSC2(C2)
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristic s, the user should
consult the resonator manufacturer for
appropriate values of external
components.
Mode Freq OSC1(C1) OSC2(C2)
LP 32 kHz
200 kHz 68 - 100 pF
15 - 30 pF 68 - 100 pF
15 - 30 pF
XT 100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS 8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid over-
driving crys tals wi th low drive level specifi-
cation. Sinc e eac h crys tal has its own
charact eristics , the user sho uld cons ult the
crystal manufacturer for app ropriate values
of external components.
Clock from
External Sy stem PIC12F629/675
OSC1
OSC2(1)
Open
Note 1: Functions as GP4 in EC osc mode.
PIC12F629/675
DS41190A-page 54 Preliminary 2002 Microchip Technology Inc.
9.2.3 EXTERN AL CLOC K IN
For applications where a clock is already available else-
where, users may directly drive the PIC12F629/675
provided t hat this exte rnal clock s ource meets the A C/
DC timing requirements listed in Section 12.0.
Figure 9-2 below shows how an external clock circuit
should be configured.
9.2.4 RC OSCILLATOR
For applications where precise timing is not a require-
ment, th e RC os ci llat or o ptio n is avai lab le. The o per a-
tion and functionality of the RC oscillator is dependent
upon a number of variables. The RC oscillator fre-
quency is a function of:
•Supply voltage
•Resistor (REXT) and capacitor ( CEXT) values
•Operati ng tem pera ture .
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 9-3 shows how the R/C combination is con-
nected.
FIGURE 9-3: RC OSCILLATOR MODE
9.2.5 INTERNAL 4 MHZ OSCILLATOR
When calib rated, the interna l oscillat or provides a fixe d
4 MHz (nomin al) syst em clock . See El ectric al Speci fi-
cations, Section 12.0, for information on variation over
voltage and temperature.
9.2.5.1 Calibrating the Internal Oscillator
A calibration instruction is programmed into the last
location of program memory. This instruction is a
RETLW XX, where the literal is the calibration value.
The literal is placed in the OSCCAL register to set the
calibration of the internal oscillator. Example 9-1 dem-
onstrates how to calibrate the internal oscillator.
EXAMPLE 9-1: CALIBRATING THE
INTERNAL OSCILLATOR
9.2.6 CLKOUT
The PIC12F629/675 devices can be configured to pro-
vide a clock ou t signal in the INT OSC and RC oscil lator
modes. When configured, the oscillator frequency
divided by four (FOSC/4) is output on the GP4/OSC2/
CLKOUT pin. FOSC/4 can be used for test purposes or
to synchronize other logic.
GP4/OSC2/CLKOUT
CEXT
VDD
REXT
VSS
PIC12F629/675
GP5/OSC1/
FOSC/4
Internal
Clock
CLKIN
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the inte rnal osci llator. The calibration value
must be saved prior to eras ing part.
bsf STATUS, RP0 ;Bank 1
call 3FFh ;Get the cal value
movwf OSCCAL ;Calibrate
bcf STATUS, RP0 ;Bank 0
2002 Microchip Technology Inc. Preliminary DS41190A-page 55
PIC12F629/675
9.3 RESET
The PIC12F629/675 differentiates between various
kinds of RESET:
a) Power-on Reset (PO R)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) WDT Reset (normal operation)
e) Brown-out Detect (BOD)
Some registers are not affected in any RESET condi-
tion; the ir stat us is unk nown on POR and un changed i n
any other RESET. Most other registers are reset to a
“RESET state ” on:
•Power-on Reset
•MCLR Reset
•WDT R eset
•MCLR Reset during SLEEP
•Brown-out De tect (BOD) Reset
They are not affected by a WDT wake-up, since this is
viewed as the resumption of norm al op era tion . TO and
PD bits are set or cleared diffe rently in diffe rent RESET
situations as indicated in Table 9-4. These bits are
used in software to determine the na ture of the RESET.
See Table 9-7 for a full des cription of RESET states of
all registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own i n Figure 9-4.
The MCLR Reset path has a noise filter to detect and
ignore s ma ll p ul ses. See Table 12-4 in Elec tric al Spec -
ifications Section for pulse width specification.
FIGURE 9-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the INTRC/EC oscillator.
Brown-out
Detect BODEN
CLKIN
pin
VPP pin
10-bit Ripple Counter
Q
PIC12F629/675
DS41190A-page 56 Preliminary 2002 Microchip Technology Inc.
9.3.1 MCLR
PIC12F629/675 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pul ses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Volt ages appli ed to the p in that ex ceed i ts s pecif icatio n
can resu lt in both MCLR Resets and excessiv e c urre nt
bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .
For this rea son, Microc hip recomme nds that the MC LR
pin no long er be tied direc tly to VDD. The use of an RC
network, as shown in Figure 9-5, is suggested.
FIGURE 9-5: RECOMMENDED MCLR
CIRCUIT
9.3.2 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the POR, simply tie the
MCLR pin through a res is tor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. Se e Electrical Specifications f or details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device mus t be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607 “Power -up Trouble Shoot ing ”.
9.3.3 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up T imer operates on an internal RC
oscill ato r. Th e chip is ke pt i n RESET as lon g a s PW R T
is activ e. The PWR T del ay allo w s the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disabl e (if set) or enable (if cl eared or programm ed) the
Power-up Timer. The Power-up Timer should always
be enabled when Brown-out Reset is enabled.
The Power-Up Time delay will vary from chip to chip
and due to:
•VDD variation
•Temperature variation
•Process variation.
See DC parameters for details.
9.3.4 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.3.5 BROWN-OUT DETECT (BOD)
The PIC1 2F629/675 membe rs have on-ch ip Brown-out
Detect circuitry. A configuration bit, BODEN, can dis-
able (if c lear/progra mmed) or enab le (if set) t he Brown-
out Detect circuitry. If VDD falls below VBOR for greater
than parameter (TBOR) in Table 12-4 (see
Section 12.0). The brown-out situation will reset the
chip. A RESET is not guaranteed to occur if VDD falls
below VBOR for less than parameter (TBOR).
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until VDD rises
above BVDD (see Figure 9-6). The Power-u p T imer w ill
now be invoked, if enabled, and will keep the chip in
RESET an additiona l 72 ms.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-u p Timer will be re-initialized. Onc e VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms RESET. The Power-up Timer should always be
enabled when Brown-out D etect is enabl ed. Figu re 9-6
shows typical Brown-out situations.
Note: The POR c ircuit does not prod uce an inter-
nal RESET when VDD declines.
VDD PIC12F629/675
MCLR
R1
1 kΩ (or greater)
C1
0.1 µf
(optio nal, not critic al )
2002 Microchip Technology Inc. Preliminary DS41190A-page 57
PIC12F629/675
FIGURE 9-6: BROWN-OUT SITUATIONS
9.3.6 TIME-OUT SEQUENCE
On power-u p, the tim e-out sequ ence is as fo llows: firs t,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit sta-
tus. For example, in EC mode with PWRTE bit erased
(PWRT disabled), there will be no time-out at all.
Figure 9-7, Figure 9-8 and Figure 9-9 depict time-out
sequences.
Since the time-outs oc cur from the POR pulse, if MCLR
is kep t low long e nough , the ti me-out s w ill e xpire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC12F629/675 device
operating in parallel.
Table 9-6 shows the RESET conditions for some spe-
cial re gisters , wh ile Table 9-7 shows t he RES ET c ondi-
tions for all the registers.
9.3.7 POWER CONTROL (PCON) STATUS
REGISTER
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0, indi cating
that a brow n-o ut has occu rred. The BOD status bit is a
don’t care and is not necessarily predictable if the
brown-o ut ci rcu it is dis abl ed (by se tti ng BO DE N bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaf fec ted oth erwise. T he user m ust write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent RESET, if POR is ‘0’, i t will indicate that a Power-
on Res et must have oc curred (i.e. , VDD may have gone
too low).
72 ms(1)
VBOR
VDD
Internal
RESET
VBOR
VDD
Internal
RESET 72 ms(1)
<72 ms
72 ms(1)
VBOR
VDD
Internal
RESET
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
PIC12F629/675
DS41190A-page 58 Preliminary 2002 Microchip Technology Inc.
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Oscillator Configuration Power-up Brown-out Reset Wake-up
from SLEEP
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1
XT, HS, LP TPWRT +
1024•TOSC 1024•TOSC TPWRT +
1024•TOSC 1024•TOSC 1024•TOSC
RC, EC, INTOSC TPWRT —TPWRT ——
POR BOD TO PD
0u11Power-on Reset
1011Brown-ou t Detect
uu0uWDT Reset
uu00WDT Wake -up
uuuuMCLR Reset during normal operation
uu10MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
V alue on all
other
RESETS(1)
03h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu
8Eh PCON — — — — — — POR BOD ---- --0x ---- --uq
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT R eset 000h 0000 uuuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Detect 000h 0001 1uuu ---- --10
Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the
interrupt vector (0004h) after execution of PC+1.
2002 Microchip Technology Inc. Preliminary DS41190A-page 59
PIC12F629/675
TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on
Reset
•MCLR Reset during
normal operation
•MCLR Reset during SLEEP
•WDT Reset
•Brown-out Detec t(1)
•Wake-up from SLEEP
through interrupt
•Wake-up from SLEEP
through WDT time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h —— —
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
GPIO 05h --xx xxxx --uu uuuu --uu uuuu
PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq(2)
PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q(2,5)
T1CON 10h -000 0000 -uuu uuuu -uuu uuuu
CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
TRISIO 85h --11 1111 --11 1111 --uu uuuu
PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u
PCON 8Eh ---- --0x ---- --uu(1,6) ---- --uu
OSCCAL 90h 1000 00-- 1000 00-- uuuu uu--
WPU 95h --11 -111 --11 -111 uuuu uuuu
IOCB 96h --00 0000 --00 0000 --uu uuuu
VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu
EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu
EEADR 9Bh -000 0000 -000 0000 -uuu uuuu
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
EECON2 9Dh ---- ---- ---- ---- ---- ----
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is se t, the PC is loaded with the interrupt
vector (0004h).
4: See Table 9-6 for RESET value for specific condition.
5: If wake-up was due to data EEPROM write completing, bit 7 = 1; A/D conversion completing, bit 6 = 1;
Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a
wake-up will cause these b i ts to = u.
6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.
PIC12F629/675
DS41190A-page 60 Preliminary 2002 Microchip Technology Inc.
FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT T ime-out
OST Time-out
Internal RESET
VDD
MCLR
Internal POR
PWRT Tim e-out
OST Time-out
Internal RESET
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Tim e-out
OST Time-out
Internal RESET
2002 Microchip Technology Inc. Preliminary DS41190A-page 61
PIC12F629/675
FIGURE 9-10: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 9-11: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 9-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
FIGURE 9-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
Note 1: External Power- on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC12F629/675
VDD
Note 1: This circuit will activate RESET when VDD
goes below (Vz + 0.7 V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.
VDD 33k
10k
40k
VDD
MCLR
PIC12F629/675
Vdd x R1
R1 + R2 = 0.7 V
VDD
R2 40k
VDD
MCLR
PIC12F629/675
R1
Q1
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
2: Internal Brown-out Reset should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
VDD x R1
R1 + R2 = 0.7V
This brown-out protection circuit employs Microchip
Technology’s MCP809 microcontroller supervisor. The
MCP8XX and MCP1X X families of supervisors provide
push-pull and open collector outputs with both "active
high and active low" RESET pins . There are 7 different
trip point selections to accommodate 5.0V and 3.0V
systems.
MCLR
PIC12F629/675
VDD
Vss RST
MCP809
VDD
Bypass
Capacitor VDD
PIC12F629/675
DS41190A-page 62 Preliminary 2002 Microchip Technology Inc.
9.4 Interrupts
The PIC12F629/675 has 7 sources of interrupt:
•External Inte rrup t GP2/INT
•TMR0 Overflow Interru pt
•GPIO Change Interrupts
•Comparator Interrupt
•A/D Interrupt (PIC12F675 only)
•TMR1 Overflow Interru pt
•EEPROM Data Write Interrupt
The Interrup t Control register (INTCON) and Peripheral
Interrupt register (PIR) record individual interrupt
requests in flag bits. It also has individual and global
interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>) enables
(if set) all unmask ed interrupts, or disables (if cl eared) all
interrupts. Individual interrupts can be disabled through
their corresponding enable bits in INTCON register and
PIE register. GIE is cleared on RESET.
The return from interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which re-
enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
•INT pin interrupt
•GP port ch ange interrupt
•TMR0 overflo w interru pt.
The periphe ral interrupt flag s are contained in the sp e-
cial register PIR1. The corresponding interrupt enable
bit is contained in Special Register PIE1.
The following interrupt flags are contained in the PIR
register:
•EEPROM data write interrupt
•A/D interrupt
•Comparator interrupt
•Timer1 overflow interrupt
When an interrupt is serviced:
•The GIE is cleared to disable any further interrupt
•The return address is pushed onto the stack
•The PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bit s. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid GP2/INT
recursiv e inte rrup t s.
For external interrupt events, such as the INT pin, or
GP port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 9-15). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service Rou-
tine, the source(s) of the i nterrupt can be determined by
polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling inter-
rupts to avoid multiple interrupt requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
2002 Microchip Technology Inc. Preliminary DS41190A-page 63
PIC12F629/675
FIGURE 9-14: INTERRUPT LOGIC
TMR1IF
TMR1IE
CMIF
CMIE
T0IF
T0IE
INTF
INTE
GPIF
GPIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Inter rupt to CPU
PEIF
EEIE
EEIF
ADIF
ADIE (1)
Note 1: PIC12F675 only.
IOC-GP0
IOCB0
IOC-GP1
IOCB1
IOC-GP2
IOCB2
IOC-GP3
IOCB3
IOC-GP4
IOCB4
IOC-GP5
IOCB5
PIC12F629/675
DS41190A-page 64 Preliminary 2002 Microchip Technology Inc.
9.4.1 GP2/INT INTERRUPT
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the GP2/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCO N<4>). The INTF bit must be cleared
in software in the Interrupt Service Routine before re-
enabling this interrupt. The GP2/INT interrupt can
wake-up the proces sor from SLEEP if th e INTE bi t was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 9.7 for
details on SLEEP and Figure 9-17 for timing of wake-
up from SLEEP through GP2/INT interrupt.
9.4.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Sectio n 4.0.
9.4.3 GPIO INTERRUPT
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOCB register.
9.4.4 COMPARATOR INTERRUPT
See Secti on 6.9 for descripti on of comp arator int errupt.
9.4.5 A/D CONVERTER INTERRUPT
After a con ver sio n i s com ple te, t he ADIF fla g (PIR<6 >)
is set. T he inte rrupt ca n be en abled/ disab led by settin g
or clearing ADIE (PIE<6>).
See Section 7.0 for operation of the A/D converter
interrupt.
FIGURE 9-15: INT PIN INTERRUPT TIMING
Note: If a change on the I/O pin should occur
when th e read o peratio n is b eing ex ecuted
(start of the Q 2 cycle), then the GPIF int er-
rupt flag may not get set.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC+1 PC+1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycl e
Inst (PC) Inst (PC+1)
Inst (PC-1) Inst (0004h)
Dummy Cycl e
Inst ( PC)
—
1
4
512
3
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
2002 Microchip Technology Inc. Preliminary DS41190A-page 65
PIC12F629/675
TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS
9.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. T ypically , users may wish to save key reg-
isters d uri ng a n i nterrupt, e.g., W regis ter a nd STATUS
register. This must be implemented in software.
Example 9-2 stores and restores the STATUS and W
register s. The use r register, W_ TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1 ). The us er registe r, STATUS_TEMP, mu st be
defined in Bank 0. The Example 9-2:
•Stores the W register
•Stores the STATUS register in Bank 0
•Executes the ISR code
•Restores the STATUS (and bank select bit
register)
•Rest ores t he W r egister
EXAMPLE 9-2: SA VING THE ST A TUS AND
W REGISTERS IN RAM
9.6 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator , which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1 and OSC2 pins of the
device has be en sto ppe d (for ex ample , by ex ecuti on of
a SLEEP instruc tion). During normal ope ration, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be perm anent ly disa bled by program ming th e con-
figuration bit WDTE as clear (Section 9.1).
9.6.1 WDT PERIOD
The WDT ha s a nominal time-o ut period of 18 ms, (wi th
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the presc al er, if assigned to the WDT, and prevent
it from timing out and generating a device R ESET.
The TO bit in the STATUS registe r will be cle ared upo n
a Watchdog Timer time-out.
9.6.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (i.e., VDD = Min., Temperat ure = Max., Max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0Va lue on
POR Reset
V alue on all
other
RESETS
0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
MOVWF W_TEMP ;copy W to temp register,
could be in either bank
SWAPF STATUS,W ;swap status to be saved into W
BCF STATUS,RP0 ;change to bank 0 regardless of
current bank
MOVWF STATUS_TEMP ;save status to bank 0 register
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS ;move W into STATUS register
SWAPF W_TEMP,F ;swap W_TEMP
SWAPF W_TEMP,W ;swap W_TEMP into W
PIC12F629/675
DS41190A-page 66 Preliminary 2002 Microchip Technology Inc.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-Out
PS0 - PS2
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on
POR Reset
V alue on all
other
RESETS
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
2002 Microchip Technology Inc. Preliminary DS41190A-page 67
PIC12F629/675
9.7 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
•WDT will be cleared but keeps running
•PD bit in the STATUS register is cleared
•TO bit is set
•Osci llator driver is turned off
•I/O ports maintain the status they had before
SLEEP was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators and CVREF should be disabled. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on chip pull-ups on GPIO should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.7.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin
2. Watchdog T imer Wake-up (if WDT was enable d)
3. Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
The first ev ent will caus e a devic e RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determ ine the cause of device RESET.
The PD bit, wh ich i s set on pow er-u p, is clear ed w hen
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake -up throug h an interrupt event, th e corres pond-
ing inte rrupt enabl e bit mu st be set (enabled) . W ake-u p
is regardl ess of the st at e of the GIE bi t. If the G IE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instr u cti o n f o llo w ing SLEEP is not desirable, the user
should hav e an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note: It s hould be no ted that a RESET generate d
by a WDT time-out does not drive MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared ), but any interru pt so urce h as both
it s i nte rrup t en abl e b it a nd the correspon d-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instructi on is com pl ete ly exec ute d.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP Oscillator mode assume d.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC osc modes, but shown here for timing reference.
PIC12F629/675
DS41190A-page 68 Preliminary 2002 Microchip Technology Inc.
9.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verificati on purp os es .
9.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. Only the
Least Significant 4 bits of the ID locations are used.
9.10 In-Circuit Serial Programming
The PIC12F629/675 microcontrollers can be serially
progra mmed w hile in t he en d app licati on c ircuit. This i s
simply don e with two lines fo r clock and da ta, and three
other lines for:
•power
•ground
•programming voltag e
This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the mos t recent firmware or a custom firmware
to be programmed.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see Programming
Specification). GP0 becomes the programming clock
and GP1 becomes the programming data. Both GP0
and GP1 are Schmitt Trigger inputs in this mode.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending on
whet her t he comm and was a lo ad or a r ead. For co m-
plete details of serial programming, please refer to the
Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 9-18.
FIGURE 9-18: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
Note: The en tire dat a EEPROM an d FLA SH pro-
gram memory will be erased when the
code protection is turned off. The INTRC
calibration data is also erased. See
PIC12F629/675 Programming Specifica-
tion for more information.
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC12F629/675
VDD
VSS
GP3/MCLR/VPP
GP0
GP1
+5V
0V
VPP
CLK
Data I/O
VDD
2002 Microchip Technology Inc. Preliminary DS41190A-page 69
PIC12F629/675
10.0 INSTR UCTION SET SUMMARY
The PIC1 2F629/675 ins truction set is highly orthog onal
and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and contro l operations
Each PIC12 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands, which further specify the operation
of the instruction. The formats for each of the catego-
ries is presented in Figure 10-1, while the various
opcode fields are summarized in Table 10-1.
Table 10-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of each
instruction is also available in the PICmicro™ Mid-
Range Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W re gister . If ‘d’ is one, the result is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
design ator, which selec t s the bi t affected by th e ope ra-
tion, w hile ‘f’ represents the ad dress of the file in whic h
the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 µs. All instructions are
execut ed within a single instruction cycle, unless a con-
ditional test is true, or the program counter is changed
as a r esu lt of an in struc tion. W he n this occurs , the exe-
cution takes two instruction cycles, with the second
cycle executed as a NOP.
All instru ct ion exa mples us e the for mat ‘0xhh’ to re p-
resent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
10.1 READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For exam pl e, a CLRF GPIO instruc tion will read GPIO ,
clear all the data bits, then write the result back to
GPIO. This example w ould have the unintended result
that the condition that sets the GPIF flag would be
cleared.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future products, do not use the OPTION
and TRIS instructions.
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon't care loc ati on (= 0 or 1).
The asse mbler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Byte-orie nted file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operati ons
13 10 9 7 6 0
OPCODE b (BIT # ) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (l i te ra l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC12F629/675
DS41190A-page 70 Preliminary 2002 Microchip Technology Inc.
TABLE 10-2: PIC12F629/675 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Wat chdog Timer
Go to address
Inclusive OR literal with W
Move litera l to W
Return fro m interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
2002 Microchip Technology Inc. Preliminary DS41190A-page 71
PIC12F629/675
10.2 Instruction Descripti ons
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are ad ded to the eight-bi t literal ’k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Desc ription: Add the conten ts of the W regis ter
with regi ster ’f’. If ’d’ is 0, the resul t
is stored in the W regi ster. If ’d’ is
1, the result is stored back in
register ’f’.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W regist er. If ' d' is 1, th e resu lt
is stored back in register 'f'.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Stat us Af fe cte d: None
Description: Bit 'b ' in regist er 'f' is cleared.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Stat us Af fe cte d: None
Description: Bit 'b ' in regist er 'f' is set.
BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Stat us Af fe cte d: None
Descr ipti on : If bi t 'b' in regi ster 'f' is '0', the next
instructi on is ex ecuted.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2TCY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Stat us Af fe cte d: None
Description: If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instru ction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
PIC12F629/675
DS41190A-page 72 Preliminary 2002 Microchip Technology Inc.
CALL Call Subroutine
Syntax : [ label ] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate a ddress is loade d into P C bit s
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a two-cycle instruction.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Desc ript ion : The cont en t s of regi ste r ’f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax : [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watc hdog Timer
Syntax : [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Stat us Af fe cte d: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
COMF Complement f
Syntax : [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination )
Stat us Af fe cte d: Z
Description: The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Stat us Af fe cte d: Z
Description: Decrement register ’f’. If ’d’ is 0,
the result is stored in the W
register. If ’d’ is 1, the result is
stored back in register ’f’.
2002 Microchip Technology Inc. Preliminary DS41190A-page 73
PIC12F629/675
DECFSZ Decrement f, Skip if 0
Syntax : [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2TCY instruction.
GOTO Unconditional Branch
Syntax : [ label ] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bi ts of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax : [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W regis ter. If ’d’ is
1, the result is placed back in
register ’f’.
INCFSZ Incremen t f, Skip if 0
Syntax : [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination),
skip if result = 0
Stat us Af fe cte d: None
Description: The contents of register ’f’ are
incremen ted. If ’d’ is 0, the resu lt is
placed in the W register. If ’d’ is 1,
the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is executed instead , making
it a 2TCY instruction.
IORLW Inclusive OR Literal with W
Syntax : [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Stat us Af fe cte d: Z
Descr iption: The conten ts of the W register are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax : [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destina tion)
Stat us Af fe cte d: Z
Description: Inclusive OR the W register with
register ' f'. If 'd' is 0, the result is
placed in the W re gis ter. If 'd' is 1,
the result is placed back in
register 'f'.
PIC12F629/675
DS41190A-page 74 Preliminary 2002 Microchip Technology Inc.
MOVF Move f
Syntax : [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW Move Literal to W
Syntax : [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight-bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f
Syntax : [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Description: Move data from W register to
register 'f'.
NOP No Op eration
Syntax : [ label ] NOP
Operands: None
Operation: No operation
Stat us Af fe cte d: None
Description: No operation.
RETFIE Return from Interrupt
Syntax : [ label ] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Stat us Af fe cte d: None
RETLW Return with Literal in W
Syntax : [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Stat us Af fe cte d: None
Description: The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return ad dress).
This is a two-cycle instruction.
2002 Microchip Technology Inc. Preliminary DS41190A-page 75
PIC12F629/675
RLF Rotate Left f through Carry
Syntax : [ label ] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the re sult is placed in
the W register . If ’d’ is 1, the result is
stored back in register ’f’.
RETURN Return from Subroutine
Syntax : [ label ] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed an d t he top o f th e s t a ck
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax : [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The con ten ts of registe r ’f’ are
rotat ed one bit to the r ight throug h
the C arry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
Register fC
Register fC
SLEEP
Syntax : [ label ] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Stat us Af fe cte d: TO, PD
Descripti on: The powe r-down status bit , PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The proce ssor is put into SLEEP
mode with th e oscillator sto pped.
SUBLW Subtract W from Literal
Syntax : [ label ] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax : [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status
Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from regi ster 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
PIC12F629/675
DS41190A-page 76 Preliminary 2002 Microchip Technology Inc.
SWAPF Swap Nibbles in f
Syntax : [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in the W
register. If ’d’ is 1, the result is
placed in regi ste r ’f’.
XORLW Exclusive OR Literal with W
Syntax: [label] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit
literal 'k'. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Stat us Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
2002 Microchip Technology Inc. Preliminary DS41190A-page 77
PIC12F629/675
11.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
•Integrated Development Environment
- MPLAB® IDE Software
•Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
•Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
•In-Circuit Debugger
- MPLAB ICD
•Device Programmers
-PRO MATE
® II Universal Device Progr a mm er
- PICSTART® Plus Entry-Level Development
Programmer
•Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demons trati on Boar d
- PICDEM 17 Demonstration Board
-K
EELOQ® Demonstration Board
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
•An interface to debugging tools
- simulator
- programmer (so ld sep ara tely )
- em ulator (sold separately)
- in-circuit debugger (sold separately)
•A full-featured editor
•A project manager
•Customizable toolbar and key mapping
•A status bar
•On-line help
The MPLAB IDE allows you to :
•Edit your s ource files (either assembly or ‘C’)
•One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
•Debug us ing :
- source file s
- absolute listi ng file
- machine code
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
11.2 MPASM Assembler
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be us ed through MPLAB ID E. The MP ASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
The MPASM assembler features include:
•Integration into MPLAB IDE projects.
•User-defined macros to streamline assembly
code.
•Conditional assembly for multi-purpose source
files.
•Directives that allow complete control over the
assembly p rocess.
11.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C1 7 and MP LAB C18 Code De vel op me nt
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microc ontrollers, re spectively. Thes e compiler s provide
powerful integration capabilities and ease of use not
found with other compilers.
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC12F629/675
DS41190A-page 78 Preliminary 2002 Microchip Technology Inc.
11.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine w ill be linked in with the ap plicatio n. This allo ws
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLINK object linker features include:
•Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
•Allows a ll m emo ry are as t o be defined as sectio ns
to provide l ink -time flex ibi lity.
The MPLIB object librarian features include:
•Easier linking because single libraries can be
included instead of many smaller files.
•Helps keep code maintainable by grouping
related modules together.
•Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
11.5 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simula tor allows code deve l-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined ke y press, to an y of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MP ASM assembler . The software simulator
offers the flexibility to develop and debug code outside of
the laborat ory envir onment, making it an excelle nt multi-
project software development tool.
11.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editi ng, buildin g, downlo ading and so urce
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmic ro mi cro con trol le rs.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
11.7 ICEP IC In -Circ ui t E m u l a to r
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
T ime-Programmable (OTP) microcontrollers. The mod-
ular sy stem can su pport dif feren t subset s of PIC16 C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
applic atio n circ ui try bei ng pres en t.
2002 Microchip Technology Inc. Preliminary DS41190A-page 79
PIC12F629/675
11.8 MPLAB ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger , MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based o n the F LASH PICmicro MCUs an d can be used
to devel op for this and other PICmicro mic rocontrollers.
The MPLAB IC D u tili ze s th e in -circuit debuggi ng c apa-
bility built into the FLASH devices. This feature, along
with Microchip’s I n-Circuit Se rial Prog rammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-s tep pin g and setting break point s .
Runni ng at full sp eed enab les tes ting hardwa re in real-
time.
11.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
11.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76 X, may be suppor ted with an adap ter socket.
The PICSTART Plus development programmer is CE
compliant.
11.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s mic rocon trollers . The micro contro llers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulato r and dow nload the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
11.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 2 demonstratio n
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches , a poten tiomet er for simula ted anal og inpu t, a
serial EEPROM to d emonstrate u sage o f the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
PIC12F629/675
DS41190A-page 80 Preliminary 2002 Microchip Technology Inc.
11.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-p in PLCC micro controlle rs with an LCD Mo d-
ule. All the necessary hardware and software is
includ ed to r un the basic dem onstrat ion pro grams . The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer , o r a PICST AR T Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 3 demon stration
board to test firmware. A prototype area has been pro-
vided t o the use r for ad ding hardwa re and con necting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commo ns and 1 2 segments, tha t is capable of disp la y-
ing time, temperature and day of the week. The
PICDEM 3 d emons tration board pr ovi des an add itiona l
RS-232 interface and Windows software for showing
the demu ltiple xo r LCD signal s on a PC . A simp le seria l
interface allows the user to construct a hardware
demultip lexer for t he LC D signals.
11.14 PIC DEM 17 Demonstration Board
The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hard ware is inc luded to ru n basic d emo progra ms,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstratio n board supports download ing of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMAST ER emulator and al l of the sample progr ams
can be run and modified using either emulator . Addition-
ally, a generous prototype area is available for user
hardware.
11.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
2002 Microchip Technology Inc. Preliminary DS41190A-page 81
PIC12F629/675
TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
PIC18FXXX
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft war e To ol s
MPLAB® Integrated
Development Environment
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
MPLAB® C17 C Com pile r
9
9
MPLAB® C18 C Com pile r
9
9
MPASMTM Assembler/
MPLINKTM Obje ct Lin ke r
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Emulators
MPLAB® ICE In-Circuit Emulator
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
ICEPICTM In-Circuit Emulator
9
9
9
9
9
9
9
9
Debugger
MPLAB® ICD In-Circuit
Debugger
9
*
9
*
9
9
Programmers
PICSTART® Plus Entry Level
Devel opment Programmer
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
PRO MATE® II
Universal Device Programmer
9
9
9
9
9
9
**
9
9
9
9
9
9
9
9
9
9
9
Demo Boards and Eval Kits
PICDEMTM 1 Demonstration
Board
9
9
9
†
9
9
PICDEMTM 2 Demonstration
Board
9
†
9
†
9
9
PICDEMTM 3 Demonstration
Board
9
PICDEMTM 14A Demonstration
Board
9
PICDEMTM 17 Demonstr ation
Board
9
KEELOQ® Evaluation Kit
9
KEELOQ® Transp on d er Kit
9
microIDTM Programme r’s Kit
9
125 kHz microIDTM
Developer’s Kit
9
125 kHz Anticollision microIDTM
Developer’s Kit
9
13.56 MHz Antic olli sion
microIDTM Developer’s Kit
9
MCP2510 CAN Developer’s Kit
9
* Contact the Microchip Technology Inc. web site at www .microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC12F629/675
DS41190A-page 82 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 83
PIC12F629/675
12.0 ELECTRICAL SPECIFICATIONS
Abso lute Maximum Ratings†
Ambient temperature under bias...........................................................................................................-40 to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Volt a ge on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V
Volt a ge on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum curr ent out of VSS pin .....................................................................................................................300 mA
Maximum curr ent i nto VDD pin........................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin ..............................................................................................25 mA
Maximum current sunk by all GPIO................................................................................................................125 mA
Maximum current sourced all GPIO................................................................................................................125 mA
Note 1: Power diss ipation is calcula ted as follow s : PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series res istor of 50-100Ω shoul d be used when applying a "lo w" level to the MCLR pin, rat her than
pulling this pin d irectly to VSS
PIC12F629/675
DS41190A-page 84 Preliminary 2002 Microchip Technology Inc.
FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +85°C
FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +85°C
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
81612 2010
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
81612 2010
2002 Microchip Technology Inc. Preliminary DS41190A-page 85
PIC12F629/675
FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
0°C ≤ TA ≤ +85°C
FIGURE 12-4: PIC12F629/675 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
81612 2010
2.2
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
81612 20
PIC12F629/675
DS41190A-page 86 Preliminary 2002 Microchip Technology Inc.
12.1 DC Characteristics: PIC12F629/675-I (Industrial)
DC CHARACTERISTICS Standard Operating Conditi ons (unle ss otherw is e stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industr ial
Param
No. Sym Characteristic Min Typ†Max Units Conditions
D001
D001A
D001B
D001C
D001D
VDD Supply Voltage 2.0
2.2
2.5
3.0
4.5
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
FOSC < = 4 MHz:
PIC12F629/675 with A/D off
PIC12F675 with A/D on, 0°C to 85°C
PIC12F675 with A/D on, -40°C to 85°C
4 MHZ < FOSC < = 10 MHz
D002 VDR RAM Data Retention
Voltage(1) 1.5* —— V Device in SLEEP mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—VSS —V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05* ——V/ms See section on Power-on Reset for details
D005 VBOR —2.0 —V
D010
D011
D012
D013
IDD Supply Current(2,3) —
—
—
—
0.4
20
0.9
5.2
2.0
48
4
15
mA
µA
mA
mA
XT, RC osc configurations
FOSC = 4 MHz, VDD = 2.0V
LP osc configuration
FOSC = 32 kHz, VDD = 2.0V, WDT disabled
XT, RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
IPD Power Down Current(4)
D020 —0.9 TBD µAVDD = 2.0V, WDT disabled
D021 ——153 µAVDD = 5.5V, BOR enabled
D022 —TBD TBD µAVDD = 2.0V, Comparator enabled
D023 —118µAV
DD = 2.0V, A/D on, not converting
D024 —TBD TBD µAVDD = 2.0V, Timer1 on, 32 kHz ext. drive
D025 —TBD TBD µAVDD = 2.0V, CVREF enabled
D026 —5TBDµAV
DD = 2.0V, WDT enabled
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested
Note1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supp ly cu rrent is mainly a fun cti on o f the op erating voltag e and frequency. Other fac tor s s uc h as I/O pi n
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
3: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
4: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
2002 Microchip Technology Inc. Preliminary DS41190A-page 87
PIC12F629/675
12.2 DC Characteris tics: PIC12F629/675-E (Extended)
DC CHARACTERISTICS Standard Operating Conditi ons (unle ss otherw is e stated)
Operating temperature -40°C ≤ TA ≤ +125°C for indu strial
Param
No. Sym Characteristic Min Typ†Max Units Conditions
D001A VDD Supply Voltage 4.5 —5.5 V -40°C to +125°C
D002 VDR RAM Data Retention
Voltage(1) 1.5* —— V Device in SLEEP mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—VSS —V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05* ——V/ms See section on Power-on Reset for details
D005 VBOR —2.0 —V
D012
D013
IDD Supply Current(2,3) —
—0.9
5.2
4
15
mA
mA
XT, RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
IPD Power Down Current(4)
D020 —TBD TBD µAVDD = 4.5V, WDT disabled
D021 —TBD TBD µAV
DD = 5.0V, BOR enabled
D022 —TBD TBD µAVDD = 4.5V, Comparator enabled
D023 —TBD TBD µAVDD = 4.5V, A/D on, not converting
D024 —TBD TBD µAV
DD = 4.5V, Timer1 on, 32 kHz ext. drive
D025 —TBD TBD µAVDD = 4.5V, CVREF enabled
D026 —12 TBD µAVDD = 4.5V, WDT enabled
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested
Note1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supp ly curre nt i s m ain ly a fun cti on o f the operating volt age and f requ enc y. Other fact ors su ch as I/ O pi n
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
3: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
4: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
PIC12F629/675
DS41190A-page 88 Preliminary 2002 Microchip Technology Inc.
12.3 DC Characteristics: PIC 12F629/675-I (Industrial), PIC12F629/675-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature - 40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ†Max Units Conditions
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS —0.8 V 4.5V ≤ VDD ≤ 5.5V
D030A VSS —0.15 VDD VOtherwise
D031 with Schmitt Trigger buffer VSS —0.2 VDD V Entire rang e
D032 MCLR, OSC1 (RC mode) VSS —0.2 VDD V
D033 OSC1 (XT and LP modes) VSS —0.3 V (Note 1)
D033A OSC1 (HS mode) VSS —0.3 VDD V(Note 1)
Input High Voltage
VIH I/O ports —
D040
D040A with TTL buffer 2.0
(0.25 VDD+0.8) —
—VDD
VDD V
V4.5 V ≤ VDD ≤ 5.5 V
otherwise
D041 with Schmitt Trigger buffer 0.8VDD —VDD entire range
D042 MCLR, GP2/AN2/T0CKI/
INT/COUT 0.8VDD —VDD V
D043 OSC1 (XT and LP modes) 1.6 —VDD V(Note 1)
D043A OSC1 (HS mode) 0.7VDD —VDD V(Note 1)
D043B OSC1 (RC mode) 0.9VDD —VDD V
D070 IPUR GPIO Weak Pull-up Current 50* 250 400* µAVDD = 5.0 V, VPIN = VSS
Input Leakage Current(3)
D060 IIL I/O ports ——
±1µAVss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D060A Analog inputs ——
±TBD µAVss ≤ VPIN ≤ VDD
D060B VREF ——
±TBD µAVss ≤ VPIN ≤ VDD
D061 MCLR(2) ——
±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 ——
±5µAVss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
Output Low Voltage
D080 VOL I/O ports ——
0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
D083 OSC2/CLKOUT ——
0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
Output High Voltage
D090 VOH I/O ports VDD-0.7 ——VIOH = -3.0 mA, VDD = 4.5V (Ind.)
D092 OSC2/CLKOUT VDD-0.7 ——VIOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
* These para m eters are char acterized but not tested.
†Data in ‘Typ’ column is at 5 .0V, 25°C un less o therwise st ated . These para meters are for des ign gu idanc e only
and are not tested .
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MC LR pin is s trongly depend ent on the applied voltage level. The specified levels
represent normal operating condi tions. Higher leaka ge current may be meas ured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2002 Microchip Technology Inc. Preliminary DS41190A-page 89
PIC12F629/675
12.3 DC Characteristics: PIC12F629/675-I (Industrial ), PIC12F629/675-E (Extended) (Cont .)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ†Max Units Conditions
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin ——15* pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101 CIO All I/O pins ——50* pF
D101A CAN All analog input pins ——TBD pF
D101B CVR VREF ——TBD pF
Data EEPROM Memory
D120 EDCell Endurance(1) 100K 1M —E/W -40°C ≤ TA ≤ +85°C
D120A EDCell Endurance(1) 10K 100K —E/W +85°C ≤ TA ≤ +125°C
D121 VDRW VDD for read VMIN —5.5 V VMIN = Minimum operating
voltage
VDD for Erase/Write 4.5 —5.5 V
D122 TDEW Erase/Write cycle time —48ms
Program FLASH Memory
D130 EPEndurance(1) 10K 100K —E/W -40°C ≤ TA ≤ +85°C
D130A EPEndurance(1) 1000 10K —E/W +85°C ≤ TA ≤ +125°C
D131 VPR VDD for read VMIN —5.5 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 —5.5 V
D133 TPEW Erase/Write cycle time —24ms
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Section 8.5.1 for additional information.
PIC12F629/675
DS41190A-page 90 Preliminary 2002 Microchip Technology Inc.
12.4 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with
one of the following formats:
FIGURE 12-5: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
V
DD
/2
C
L
R
L
Pin Pin
V
SS
V
SS
C
L
RL=464Ω
CL= 50 pF for all pins
15 pF for OSC2 output
Load Cond ition 1 Load Condition 2
2002 Microchip Technology Inc. Preliminary DS41190A-page 91
PIC12F629/675
12.5 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)
FIGURE 12-6: EXTERNAL CLOCK TIMING
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ†Max Units Conditions
FOSC Ex ternal CLKIN Frequency(1) DC —200 kHz LP osc mode
DC —4MHzXT mode
DC —20 MHz HS mode
DC —20 MHz EC mode
Osci lla tor Freq uen cy(1) 5—200 kHz LP osc mode
4 MHz INTRC mode
TBD —4 MHz RC osc mode
0.1 —4 MHz XT osc mode
1—20 MHz HS osc mode
1T
OSC External CLKIN Period(1) 5—∞µsLP osc mode
50 —∞ns HS osc mode
50 —∞ns EC osc mode
250 —∞ns XT osc mode
Oscillator Perio d(1) 5 200 µsLP osc mode
250 ns INTRC mode
250 —TBD ns RC osc mode
250 —10,000 ns XT osc mode
50 —1,000 ns HS osc mode
2T
CY Instructi on Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH External CLKIN (OSC1) High
External CLKIN Low 2* ——µs LP oscillator, TOSC L/H duty cycle
20* ——ns HS oscilla tor, TOSC L/H duty cycle
100 * ——ns XT oscillat or, TOSC L/H duty cycle
4TosR,
TosF External CLKIN Rise
External CLKIN Fall — —50* ns LP oscillator
— —25* ns XT oscillat or
—— 15* ns HS oscillator
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Instruction cycle period (TCY) equals four ti mes the input osc il lat or tim e-b as e pe riod. All specifie d va lu es a r e
based on c harac teriza tion da ta f or that p arti cular oscil lator type under s ta nda rd opera ting cond itions with the
device e xecut ing co de. Exc eedin g t hese spe cif ied li mit s ma y resu lt in a n uns t able o scillat or o peratio n and/o r
higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external
clock applied to OSC1 pin. When an external clock input is us ed, the ‘max’ cycle tim e li mi t is ‘DC’ (no cloc k)
for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC12F629/675
DS41190A-page 92 Preliminary 2002 Microchip Technology Inc.
TABLE 12-2: CALIBRATED INTERNAL RC FREQUENCIES
AC Characteristics St andard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (Industrial),
-40°C ≤ TA ≤ +125°C (Extended)
Operatin g Voltage VDD range is described in Section 12.1 and
Section 12.2.
Param
No. Sym Characteristic Min* Typ(1) Max* Units Conditions
Internal Calibrated RC Frequency 3.92 4.00 4.08 MHz VDD = 5.0V, +85°C (Ind.)
VDD = 5.0V, +125°C (E xt .)
Internal Calibrated RC Frequency 3.80 4.00 4.20 MHz 2.5V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
* These parameters are characterized but not tested.
Note 1: Dat a in th e Typi cal (“Typ”) column is at 5.0V, 25°C unle ss oth erwise s tat ed. The se p arame ters are for desi gn
guidance only and are not tested.
2002 Microchip Technology Inc. Preliminary DS41190A-page 93
PIC12F629/675
FIGURE 12-7: CLKOUT AND I/O TIMING
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
OSC1
CLKOUT
I/O pi n
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
22
23
19 18
15
11
12
16
Old Value New Value
Param
No. Sym Characteristic Min Typ†Max Units Conditions
10 TosH2ckL OSC1↑ to CLKOUT↓ —75 200 ns (Note 1)
11 TosH2ckH OSC1↑ to CLKOUT↑ —75 200 ns (Note 1)
12 TckR CLK OUT rise time —35 100 ns (Note 1)
13 TckF CLKOUT fall time —35 100 ns (Note 1)
14 TckL2ioV CLKOUT↓ to Por t out v al id ——20 ns (Note 1)
15 TioV2ckH Port in valid before CLKOUT↑ TOSC + 200 ns ——ns (Note 1)
16 TckH2ioI Port in hold after CLKOUT↑ 0 ——ns (Note 1)
17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid —50 150 * ns
——300 ns
18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time) 100 ——ns
19 TioV2osH Port input valid to OSC1↑
(I/O in setup time) 0——ns
20 TioR Port output rise time —10 40 ns
21 TioF Port output fall time —10 40 ns
22 Tinp INT pin high or low time 25 ——ns
23 Trbp GPIO change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
PIC12F629/675
DS41190A-page 94 Preliminary 2002 Microchip Technology Inc.
FIGURE 12-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 12-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
BVDD
RESET (due to BOR)
VDD
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
72 ms time out(1)
35
Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to ‘0’.
2002 Microchip Technology Inc. Preliminary DS41190A-page 95
PIC12F629/675
TABLE 12-4: RESET, WATCHDOG TI MER, OSCILLATOR START-UP T IMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param
No. Sym Characteristic Min Typ†Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2
TBD —
TBD —
TBD µs
ms VDD = 5V, -40°C to +85°C
Extended temperature
31 TWDT Watchdog Timer Time-out
Period
(No Prescaler)
7*
TBD 18
TBD 33*
TBD ms
ms VDD = 5V, -40°C to +85°C
Extended temperature
32 TOST Oscillation Start-up Timer
Period —1024TOSC ——TOSC = OSC1 period
33* TPWRT Power up Timer Period 28*
TBD 72
TBD 132*
TBD ms
ms VDD = 5V, -40°C to +85°C
Extended Temperature
34 TIOZ I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset ——2.0 µs
BVDD Brown-out Reset Voltage 2.0 2.1 V
Brown-o ut Hy stere s is TBD
35 TBOR Brown-out Reset Pulse Width 100* ——µsVDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
PIC12F629/675
DS41190A-page 96 Preliminary 2002 Microchip Technology Inc.
FIGURE 12-10: TIMER0 AND TIMER1 EXTERNAL CLOC K TIMINGS
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
T0CKI
T1CKI
40
41
42
45 46
47 48
TMR0 or
TMR1
Param
No. Sym Characteristic Min Typ†Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 ——ns
With Prescaler 10 ——ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 ——ns
With Prescaler 10 ——ns
42* TT0P T0CKI Period G reater of:
20 or TCY + 40
N
——ns N = prescale value
(2, 4, ..., 256)
45* TT1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 ——ns
Synchronous,
with Pre scale r 15 ——ns
Asynchronous 30 ——ns
46* TT1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 ——ns
Synchronous,
with Pre scale r 15 ——ns
Asynchronous 30 ——ns
47* TT1P T1CKI Input
Period Synchronous Greater of:
30 or TCY + 40
N ——ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 ——ns
FT1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz
48 T CKEZ tmr1 Delay from external clock edge to timer increment 2 TOSC*—7 TOSC*—
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2002 Microchip Technology Inc. Preliminary DS41190A-page 97
PIC12F629/675
TABLE 12-6: COMPARATOR SPECIFICATIONS
TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Comparator Specifications Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Sym Characteristics Min Typ Max Units Comments
VOS Input Offset Voltage —± 5.0 ± 10 mV
VCM Input Common Mode Voltage 0 —VDD - 1.5 V
CMRR Common Mode Rejection Ratio +55* ——db
TRT Response Time(1) —150 400* ns
TMC2COV Comparator Mode Change to
Output Valid —— 10* µs
* These parameters are characterized but not tested.
Note1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
Voltage Referen ce Specifications Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Sym Characteristics Min Typ Max Units Comments
Resolution —
—VDD/24*
VDD/32 —
—LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy —
——
—± 1/4*
± 1/2* LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R) —2k* —Ω
Settling Time(1) ——10* µs
* These parameters are characterized but not tested.
Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
PIC12F629/675
DS41190A-page 98 Preliminary 2002 Microchip Technology Inc.
TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS:
Param
No. Sym Characteristic Min Typ†Max Units Conditions
A01 NRResolution ——10 bits bit
A02 EABS Total Absolute Error* ——TBD LSb VREF = 3.0V
A03 EIL Integral Error ——TBD LSb VREF = 3.0V
A04 EDL Differential Error ——TBD LSb No mis sing codes to 10 bits
VREF = 3.0V
A05 EFS Full Scale Range 2.2* —5.5* V
A06 EOFF Offset Error ——TBD LSb VREF = 3.0V
A07 EGN Gain Error ——TBD LSb VREF = 3.0V
A10 —Monotonicity —guaranteed(3) ——VSS ≤ VAIN ≤ VREF+
A21 VREF Reference V High
(VDD or VREF)VSS —VDD V
A25 VAIN Analog Input Voltage VSS —VREF V
A30 ZAIN Recommended
Impedance of Analog
Voltage Source
——2.5 kΩ
A50 IREF VREF In put Current(2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
During A/D conversion cycle.
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off , it will not consume any current other than leakage current. The power-down current spec includes any such
leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2002 Microchip Technology Inc. Preliminary DS41190A-page 99
PIC12F629/675
FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
987 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is a dded before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
6
134 (TOSC/2)(1)
1 TCY
Param
No. Sym Characteristic Min Typ†Max Units Conditions
130 TAD A/D Clock Period 1.6 ——µsTOSC based, VREF ≥ 3.0V
3.0* ——µsT
OSC based, VREF full range
130 TAD A/D Internal RC
Oscillator Perio d 3.0* 6.0 9.0* µsADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* µsAt V
DD = 5.0V
131 TCNV Conversion Time
(not including
Acqu isition Tim e)(1)
—11 —TAD Set GO bit to new data in A/D result
register
132 TACQ Acquis iti on Time (Note 2)
5*
11.5
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by mo re than 1 LS b (i.e.,
4.1 mV @ 4.096 V) from the last
sampled voltage (as stored on
CHOLD).
134 TGO Q4 to A/D Clock
Start —TOSC/2 ——If the A/ D clock sou rce is se lected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5.0V, 25 °C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for minimum conditions.
PIC12F629/675
DS41190A-page 100 Preliminary 2002 Microchip Technology Inc.
FIGURE 12-12: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No. Sym Characteristic Min Typ†Max Units Conditions
130 TAD A/D Clock Period 1.6 ——µsVREF ≥ 3.0V
3.0* ——µsVREF full range
130 TAD A/D Internal RC
Oscilla tor Perio d 3.0* 6. 0 9.0* µsADCS<1:0> = 11 (RC mode)
At VDD = 2. 5V
2.0* 4.0 6.0* µsAt VDD = 5.0V
131 TCNV Conversion Time
(not includin g
Acquisiti on Time)(1)
—11 —TAD
132 TACQ Acquisiti on Time (Note 2)
5*
11.5
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
change d by more than 1 LSb (i.e .,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
134 TGO Q4 to A/D Clock
Start —TOSC/2 + TCY ——If the A/D clock source is selec ted
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to b e
executed.
* These parameters are characterized but not tested.
†Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMP LING STOPPED
DONE
NEW_DATA
9 7 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before t he A/ D clock starts. This allows the
SLEEP instruction to be executed.
134
6
8
132
1 TCY
(TOSC/2 + TCY)(1)
1 TCY
2002 Microchip Technology Inc. Preliminary DS41190A-page 101
PIC12F629/675
13.0 PACKAGING INFORMATION
13.1 Package Marking Information
XXXXXNNN
8-Lead PDIP (Skinny DIP) Example
XXXXXXXX
YYWW /017
12F629-I
0215
XXXXYYWW
8-Lead SOIC
XXXXXXXX
NNN /0215
Example
12F629-E
017
8-Lead MLF-S
XXXXXXX
NNN
XXXXXXX
XXYYWW -E/021
017
12F629
021 5
Example
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week c ode (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microc hip p art num ber cann ot be marked on one lin e, it wil l
be carried over to the next line thu s l imi tin g the num be r of av ail abl e ch arac ters
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
PIC12F629/675
DS41190A-page 102 Preliminary 2002 Microchip Technology Inc.
13.2 Package Detail s
The following sections give the technical details of the
packages.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.2 6
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing §eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2002 Microchip Technology Inc. Preliminary DS41190A-page 103
PIC12F629/675
8-Lead Plastic Small Outline (SN) –Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004
A1
Standoff §1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
PIC12F629/675
DS41190A-page 104 Preliminary 2002 Microchip Technology Inc.
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
NOM
.050 BSC
INCHES
.194 BSC
.184 BSC
.226 BSC
.236 BSC
.008 REF.
DOverall Width
JEDEC equivalent: pending
Notes:
Drawing No. C04-113
Molded Package Width
Lead Width
*Controlling Parameter
Mold Draft Angle Top
Tie Bar Width
Lead Length R
α
B
L
D1
.014
.020
Dimension Limits
Molded Package Thickness
Pitch
Overall Height
Overall Length
Molded Package Length
Base Thickness
Standoff
Number of Pin s
A3
E1
E
A2
A1
A
.000
Units
n
p
MIN
TOP VIEW
12
A2
A
5.99 BSC
.019
12
.030
.014
.016
.024 0.35
0.50 .356
0.40
0.60
5.74 BSC
12
0.47
0.75
MILLIMETERS*
.039
.002
.031
.026
.0004
.033
0.00
8MAX MIN
1.27 BSC
0.20 REF.
4.92 BSC
4.67 BSC
0.85
0.01
0.65 0.80
0.05
1.00
MAXNOM 8
BOTTOM VIEW
n
E
E1
PIN 1
p
B
Exposed Pa d Len gth E2
Exposed Pa d Wid th D2 . 08 5 .0 91 .097 2. 16 2.31 2.46
.152 .158 .163 3.85 4.00 4.15
EXPOSED
METAL
PADS
D2
E2
A1
A3
α
L
ID
D1 D
R
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
2002 Microchip Technology Inc. Preliminary DS41190A-page 105
PIC12F629/675
8-Lead Plastic Micro Leadframe Package (MF) 6x5 mm Body (MLF-S)
L
M
M
B
SOLDER
MASK
p
PACKAGE
EDGE
Pad Width
*Controlling Parameter
Drawing N o. C04- 2113
B .014 .016 .019 0.35 0.40 0.47
Pitch MAX
Units
Dimen sion Li mits
p
INCHES
.050 BSC
MIN NOM MAX
MILLIMETERS*
MIN 1.27 BSC
NOM
Pad Length
Pad to Solder Mask L .020 .024 .030 0.50 0.60 0.75
M .005 .006 0.13 0.15
PIC12F629/675
DS41190A-page 106 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 107
PIC12F629/675
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC12F629/675 devices
listed in this data sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Feature PIC12F629 PIC12F675
A/D No Yes
PIC12F629/675
DS41190A-page 108 Preliminary 2002 Microchip Technology Inc.
APPENDIX C: DEVICE MIGRATIONS
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
Not Applicable
APPENDIX D: MIGRATING FROM
OTHER PICmicro®
DEVICES
This discusses some of the issues in migrating from
other PICmicro devices to the PIC12F6XX family of
devices.
D.1 PIC12C67X to PIC12F6XX
See Microchip website for availability
(www.microchip.com).
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with th es e p a r ameters. Due to p r oce ss dif-
ferences in the manufa cture of this device,
this device may have different perfor-
mance characteristics than its earlier ver-
sion. These differences may cause this
device to perform differently in your appli-
cation than the earlier version of this
device.
2002 Microchip Technology Inc. Preliminary DS41190A-page 109
PIC12F629/675
APPENDI X E: DEVE LOPMENT
TOOL VE RSION
REQUIREMENTS
This lists the minimum requirements (software/
firmware) of the specified development tool to support
the devices listed in this data sheet.
MPLAB® IDE: TBD
MPLAB® SIMULATOR: TBD
MPLAB® ICE 3000:
PIC12F629/675 Processor Module:
Part Number - TBD
PIC12F629/675 Device Adapter:
Socket Part Number
8-pin SOIC TBD
8-pin PDIP TBD
8-pin MLF-S TBD
MPLAB® ICD: TBD
PRO MATE® II: TBD
PICSTART® Plus: TBD
MPASMTM Assembler: TBD
MPLAB® C18 C Compiler: TBD
Note: Please read all associated README.TXT
files that are supplied with the develop-
ment tools. These "read me" files will dis -
cuss product support and any known
limitations.
PIC12F629/675
DS41190A-page 110 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 111
PIC12F629/675
INDEX
A
A/D......................................................................................39
Acquisition Requirements .................... .... .... ......... .... ..43
Block Diag ram................. ........... .................. ...............39
Configuration and Operation.......................................39
Effects of a RESET.....................................................45
Internal Sampling Switch (Rss) Impedence................43
Operation During SLEEP............................................45
PIC12F675 Converter Characteristics........................98
Sampli n g Time........................ ................... ........... ......44
Source Impedance.................. ........... .... .... ......... .... ....43
Summary o f Registers ......................... .......................45
Absolute Maximum Ratings ................................................83
AC Characteristics
Industrial and Extended........................ ......................91
Additional Pin Fun ctions .....................................................19
Interrupt-on-Change....................................................20
Weak Pu ll-up............... ................... ................... ..........19
Analog Input Connection Considerations..................... .......36
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler.....................................................77
B
Block Diagram
TMR0/WDT Pr escaler.................................................25
Block Diagrams
Analog Input Mode................................ ......................36
Compar a tor Output.................................. ...................36
Comparator Voltage Reference .......................... .. .... ..37
GP0 and GP1 Pins......................... .... .. .. .. .. .. ....... .. .. .. ..21
GP2.............................................................................22
GP3.............................................................................22
GP4.............................................................................23
GP5.............................................................................23
On-Chip Rese t Circuit........................................... ......55
RC Oscillator Mode.....................................................54
Timer1.........................................................................28
Wat chdog Timer..................... .....................................66
Brown-out
Associ a te d Re g i sters................. .................. ...............58
Brown-out Detect (BOD).....................................................56
Brown-out Reset Timing and Characteristics......................94
C
Calibrated Internal RC Frequencies....................................92
CLKOUT .............................................................................54
Code Examples
Changing Prescaler .............. .. ....... .. .. .... .. .. .. ....... .. .... ..27
Data EE PROM Read....................... ................... ........49
Data EE PROM Write ...... ........... .................. ...............49
Initia lizing GPIO..........................................................19
Saving STATUS and W Registers in RAM..................65
Write Verify..................................................................49
Code Protection ............................................................. .....68
Comparator......................................................................... 33
Associ a te d Re g i sters...... ........... ................... .............. 38
Configuration.............................................................. 35
Effects of a RESET..................................................... 37
I/O Operating Modes ............... .. .... .. .. .. ....... .. .... .. .. .. .... 35
Interrupts .................................................................... 38
Operation.................................................................... 34
Operation During SLEEP............................................ 37
Output......................................................................... 36
Reference................................................................... 37
Response Time............. ....... .. .... .. .... .. .. ....... .... .. .... .. .. .. 37
Comparator Specifications ................... ........... .................... 97
Comparator Voltage Reference Specifications................... 97
Configur ation Bits ............................................................... 52
Configuring the Voltage Reference............................... .. .. .. 37
Crystal Operation................................................................ 53
D
Data EEPROM Memory
Associ a te d Re g i sters/Bit s.................... ....................... 50
Code Protection.......................................................... 50
EEADR Register........ ................................................. 47
EECON1 Regist e r .... ........... ................... .......... .......... 47
EECON2 Regist e r .... ........... ................... .......... .......... 47
EEDATA Register .............. .......... ................... ............ 47
Data Memory Organization.............. .... .... .... ........... .... .... ...... 7
DC Characteristics
Extended .................................................................... 87
Extended and Industrial.............................................. 88
Industrial..................................................................... 86
Development Support......................................................... 77
Development Tool Version Requirements........................ 109
Device Differences............................................................ 107
Device Migrations............................................................. 108
Device Overview................................................................... 5
E
EEPROM Data Memory
Reading...................................................................... 49
Spuri o u s Write......................... ................... ................ 49
Write Verify ................................................................. 49
Writing ........................................................................ 49
Electrical Specifications...................................................... 83
Errata.................................................................................... 3
F
Firmware Instructions ......................................................... 69
G
General Purpose Register File ............................................. 7
GPIO
Associ a te d Re g i sters...... ................... ........... .............. 24
GPIO Port......................... ................... ................... ............ 19
GPIO, TRISIO Registers..................................................... 19
PIC12F629/675
DS41190A-page 112 Preliminary 2002 Microchip Technology Inc.
I
ICEPIC In -Circuit Emulator ..... ................... .................. .......78
ID Locations........................................................................68
In-Cir cuit Serial Programming.............................................68
Indirect Addressing, INDF and FSR Registers....................18
Instruction Format...............................................................69
Instruction Set.....................................................................69
ADDLW .......................................................................71
ADDWF.......................................................................71
ANDLW .......................................................................71
ANDWF.......................................................................71
BCF.............................................................................71
BSF.............................................................................71
BTFSC ........................................................................71
BTFSS ........................................................................71
CALL...........................................................................72
CLRF...........................................................................72
CLRW..........................................................................72
CLRWDT.....................................................................72
COMF .........................................................................72
DECF ..........................................................................72
DECFSZ......................................................................73
GOTO..........................................................................73
INCF............................................................................73
INCFSZ.......................................................................73
IORLW.........................................................................73
IORWF ........................................................................73
MOVF..........................................................................74
MOVLW.......................................................................74
MOVWF ......................................................................74
NOP............................................................................74
RETFIE .......................................................................74
RETLW........................................................................74
RETURN.....................................................................75
RLF .............................................................................75
RRF.............................................................................75
SLEEP ........................................................................75
SUBLW........................................................................75
SUBWF.......................................................................75
SWAPF .......................................................................76
XORLW.......................................................................76
XORWF.......................................................................76
Summary Table....................... ................... .................70
Internal 4 MHz Oscillator.....................................................54
Internal Sampling Switch (Rss) Impedence ........................43
Interrupts.............................................................................62
A/D Converte r........ ...................................... ...............64
Comparator.................................................................64
Context Saving............................................................65
GP2/INT......................................................................64
GPIO...........................................................................64
Summary o f Registers .............. ................... ...............65
TMR0 ..........................................................................64
K
KEELOQ Evaluation and Programming Tools ......................80
M
MCLR.................................................................................. 56
Memory Organization
Data EE PROM Memory................. ................... .......... 47
Migratin g fr o m oth e r PICm ic ro Devices............... ............. 108
MPLAB C17 and MPLAB C18 C Compilers ....................... 77
MPLAB ICD In-Circuit Debugger ........................................ 79
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPL AB ID E............................................ 78
MPLAB Integrated Development
Environment Software .................................................. 77
MPLINK Object Linker/MPLIB Object Librarian.................. 78
O
OPCODE Field Desc r i p tions................ ............................... 69
Oscillato r Configurat ions................. .................................... 53
Oscillato r Start-up Timer (OST).......................................... 56
P
Packaging......................................................................... 101
Details....................................................................... 102
Marking..................................................................... 101
PCL and PCLATH ............................................................... 17
Computed GOTO........................................................ 17
Stack........................................................................... 17
PICDEM 1 Low Cost PICmicro
Demonstration Board.................................................... 79
PICDEM 17 Demonstration Board. .....................................80
PICDEM 2 Low Cost PIC16CXX
Demonstration Board.................................................... 79
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board.................................................... 80
PICSTART Plus Entry Level Development
Programmer........................ ................... ................... .... 79
Pin Descriptions and Diagrams .......................................... 21
Pinout Descriptions
PIC12F629 ................................................................... 6
PIC12F675 ................................................................... 6
Power Cont rol/Status Register (PCON)........ ...................... 57
Power-Down Mode (SLEEP ) .............................................. 67
Power-on Reset (POR)....................................................... 56
Power-up Timer (PWRT).................................................... 56
Prescaler............................................................................. 27
Swit ch i n g Pr escal e r As si g n ment .... ...... ...... .. ..... ...... .. . 2 7
PRO MATE II Univer sal De vice Progr a mme r............... ...... 79
Program Mem ory O rganization......... .................................... 7
Programm ing, Device Instructions...................................... 69
2002 Microchip Technology Inc. Preliminary DS41190A-page 113
PIC12F629/675
R
RC Oscillator.......................................................................54
Read-Modify-Write Operations ...........................................69
Registers
ADCON0 (A/D Control)...............................................41
ANSEL (Analog Select)...............................................42
CMCON (Comparator Control) ...................................33
CONFIG (Configuration Wor d )......... ................... ........52
EEADR (EEPROM Address) ......................................47
EECON1 (EEPROM Control)......................................48
EEDAT (EEPROM Data).............................................47
INTCON (Interrupt Control).........................................13
IOCB (Interrupt-on-Change GPIO) .............................20
MapsPIC12F629............................................................8
PIC12F675............................................................8
OPTION_REG (Option ) ........................................12, 26
OSCCAL (Oscillator Calibration).... .......... ........... ........16
PCON (Power Control) ...............................................16
PIE1 (Peripheral Interrupt Enable 1)...........................14
PIR1 (Peripheral Interrupt 1).......................................15
STATUS ......................................................................11
T1CON (Timer1 Control)..... ........... ................... ..........30
VRCON (Voltage Reference Control) .........................38
WPU (Weak Pull-up)...................................................19
RESET................................................................................55
Revision History................................................................107
S
Softwa re Simulator (MPLAB SIM )................ ................... ....78
Speci a l Features of the CPU ............... ................... .......... ..51
Special Function Registers...................................................8
Special Functions Registers Summary.................................9
T
Time-out Sequence................................ .. .... .... .. ......... .. .... ..57
Timer0.................................................................................25
Associ a te d Re g i sters............................................ ......27
External Clock.............................................................26
Interrupt.......................................................................25
Operation ....................................................................25
T0CKI..........................................................................26
Timer1
Associ a te d Re g i sters...... ........... ................... .............. 31
Asynchronous Counter Mode..................................... 31
Reading and Writing..................... . ..................... 31
Capacitor Selection .................................................... 31
Interrupt...................................................................... 29
Modes of Ope rations......................... ................... ...... 29
Operation During SLEEP............................................ 31
Oscillator..................................................................... 31
Prescaler .................................................................... 29
Timer1 Module with Gate Control....................................... 28
Timing Diagrams
CLKOUT and I/O.................................. . ..................... 93
External Clock ............................................................ 91
INT Pin Interrupt......................................................... 64
PIC12F675 A/D Conversion (Normal Mode) .............. 99
PIC12F675 A/D Conversion Timing
(S LEE P Mode).................................................... 100
RESET, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer............................................. 94
Time- out Sequenc e on Power-up
(MCLR not Tie d to V DD)/
Case 1................................................................ 60
Case 2................................................................ 60
Time- out Sequenc e on Power-up
(MCLR Tied to VDD).............................................. 60
Timer0 and Timer1 External Clock ............................. 96
Timer1 Incremen ting Edge ................ ................... ...... 29
Timing Pa rameter Symbolo g y................. ........................... 90
V
Voltage Reference Accuracy/Error..................................... 37
W
Watchdog Timer
Summary o f Registers............... ................... .............. 66
Watchdog Timer (WDT)........................... .... ......... .... .... .. .... 65
WWW, On-Line Support....................................................... 3
PIC12F629/675
DS41190A-page 114 Preliminary 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. Preliminary DS41190A-page 115
PIC12F629/675
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used b y Micr ochip as a me ans to mak e
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and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FT P site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
fa vo rite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
•Latest Microchip Press Releases
•Technical Support Section with Frequently Asked
Questions
•Design Tips
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•Job Postin gs
•Microchi p Consultant Progra m Member Listing
•Links to other useful web sites related to
Microchip Products
•Conferences for products, Development Systems,
technical information and more
•Listing of seminars and events
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
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Plus, this line provides information on how customers
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Hot Line Numbers are:
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013001
PIC12F629/675
DS41190A-page 116 Preliminary 2002 Microchip Technology Inc.
READER RESPONSE
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DS41190A
PIC12F629/675
1. What are the be st features of this document?
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3. Do you find the organization of this data sheet ea sy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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PIC12F629/675
2002 Microchip Technology Inc. Preliminary DS41190A-page117
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC12F6XX: Standard VDD range 2.0V to 5.5V
PIC12F6XXT VDD range 2.0V to 5.5V (Tape and Reel)
Temperature R ang e I = -40°C to +85°C
E=-40
°C to +125°C
Package P = PDIP
SN = SOIC (Gull Wing, 150 mil body)
MF = MLF-S
Pattern 3-Digit Pattern Code for QTP (blank otherwise).
Examples:
a) PIC12F629 - E/P 301 = Exte nded Temp.,
PDIP package, 20 MHz, QTP pattern #301.
b) PIC12F675 - I/SO = Industrial Temp.,
SOIC package, 20 MHz.
–
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
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DS41190A-page 118 Preliminary 2002 Microchip Technology Inc.
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