130 5410074100 8-Bit Bistable Latch Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL Device Type clelmae Device Type alelaiGe Device Type ars laiGe Device Type t+ eee Device Type aes Tl. SN54100 Wo SN74100 J OIND FAIRCHILD MOTOROLA MC 74100 Pd NSC PHILIPS SIGNETICS waa Fo tt SIEMENS FLJ301 FUJITSU HITACHI MITSUBISHI NEC TOSHIBA Electrical Characteristics SN54100/SN74100 absolute maximum ratings over operating free-air temperature range We 1De iE positive togic: 1 vor }G1 Ne GND 201 202 FOP 2D ENABI 26 see funtion table Le NC--No intemai connection Supply voltage, Voce wv Operating free-air | SNS4 $5C to 125C Input voltage 5.5V temperature range [ SNT74 OC to 70C interemitter voltage (see Note 1) 5.5V Storage temperature range 65C to 150C recommended operating conditions SNS54100 SN74100 UNIT MIN NOM MAX | MIN NOM MAX Supply voltage, Voc 4.5 5 5.5 | 4.75 $ $.28 v High-level output current, Io ~ 400 400 |. uA Low-level output current, Io. 6 16 | mA Width of enabling pulse? tw 20 20 ns Data hold time, thoid 5 5 ns Setup time, tgatup 20 20 as Operating free-air temperature, T 4 55 125 0 7m, *C electrical charasteristics over recommended operating free-air temperature range PARAMETER * TEST CONDITIONS t MIN TYP$ MAX | UNIT Vin High-level input voltage 2 v Vit Low-level input voltage 0.8 v vy Input clamp voltage VCC=MIN, l=12mA ~Is]| Vv Voc=MIN, ViH=2V. v High-level outout voltage 2.4 3.4 v OH Mighrievel ou 3 Vip =0.8V, [OH =a00uA v =MIN, Vip =2V. VoL Low-level output voltage ce 4H 0.2 a4 Vv Vit, =0.8V, lor =lemA Input current at maximum ' v =MAX, Vj =5.5V 1] mA | Input voltage ce | High-tevel input O input 80 I v = Vi =2.4V BD NH current G input Gc=MAX, Vi =2.4 320 & Low-laval input O input 73.2 I v = Vv, =0.4V mA Mu current Q input co=MAX, Vi=0.4 12.8 SN54100 | 20 --$7 It ( tput t * | Voo= mA os Short-circut output curren CG =MAX SN74100 | 18 "87 Vog =MAX, 5NS54100 64 92 | Suppl t A. co Supply curren Sea Note 2 SN74100 64.106] t 16 30 oat from 0 to output O Voo=5v. Ta=28C, 14 25 ns PHL Oy =I1SpF, teLH 16 30 trom G te tput O RL= ns TPHL (0 outpu iL = 4000 7 15 Pin Assignment (Top View) ENABLE @ Yoo (03 104 108 103 209 206,204 203 NO NO c NOTES: TO OTHER LATCHES e+ 2. TO OTHER LATCHES #4 Function Table "100 (Each Latch) INPUTS OUTPUTS D G Q a u H L H H H H L x L Q Go H=high level. X =irrelevant Qq=the tevel of Q betore the high-to-low transition of G Functional Block Diagram (each latch) ' ENABLE 100 8-BIF BISTABLE. LATCH Schematic (each | atch) DATA rTO OTHER LATCHES 1 orf ax } 4. 6k - ~ You 4k 3130 GND ENABLE DATA "100 circuit This ts the voltage between two emitters of a multiple-emitter input transistor this circuit, this rating apnliss between the enable and D inputs of any latch Ig is tested with all inputs grounded and all outputs open Leto OTHER LATCHES Resistor values shown are nominal and in chms For +t For conditions shown as MIN cr MAX, use the appropriate value specified unger recommended operating conditions for the applicable device type t All typical values are at Voc Vv. Ta=25C. @ Not more than one output should be shorted at a tme. * tp =propagation delay ume, tow-to-high-level output tPHL =propagation delay time, high-to-low-level output