Freescale Semiconductor
Data Sheet: Advance Information Document Number: MPC5674F
Rev. 10.1, 06/2015
© Freescale Semiconductor, Inc., 2008-2015. All rights reserved.
MPC5674F
TEPBGA–516
27mm x 27mm
TEPBGA–324
23mm x 23mm
TEPBGA–416
27mm x 27mm
• Dual issue, 32-bit CPU core complex (e200z7)
– Compliant with the Power Architecture® embedded
category
– 16 KB I-Cache and 16 KB D-Cache
– Includes an instruction set enhancement allowing
variable length encoding (VLE), optional encoding of
mixed 16-bit and 32-bit instru ctions, for code size
footprint reduction
– Includes signal processing extension (SPE2) instruction
support for digital signal processing (DSP) and
single-precision floatin g point operations
• 4 MB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPRO M emul ation
• 256 KB on-chip general-purpose SRAM including 32 KB
of standby RAM
• Two direct memory access controller (eDMA2) blocks
– One supporting 64 channels
– One supporting 32 channels
• Interrupt controller (INTC)
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• External bus interface (EBI) for calibration and application
development (not available on all packages)
• System integration unit (SIU)
• Error correction status module (ECSM)
• Boot assist module (BAM) supports serial bootload via
CAN or SCI
• Two second-generation enhanced time processor units
(eTPU2) that share code and data RAM.
– 32 standard channels per eTPU2
– 24 KB code RAM
– 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32
unified channels (eMIOS) with each channel capable of
single action, double action, pulse width modulation
(PWM) and modulus counter operation
• Four enhanced queued analog-to-digital converters
(eQADC)
– Support for 64 analog channels
– Includes one absolute reference ADC channel
– Includes eight decimation filters
• Four deserial serial peripheral interface (DSPI) modules
• Three enhanced serial communication interface (eSCI)
modules
• Four controller area network (FlexCAN) modules
• Dual-channel FlexRay controller
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003/5001-2008 standard
• Device and board test support per Joint Test Action Group
(JTAG) (IEEE 1149.1)
• On-chip voltage regulator controller regulates supply
voltage down to 1.2 V for core logic
MPC5674F Microcontroller
Data Sheet
Covers: MPC5674F and MPC5673F
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor2
Table of Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC567xF Family Differences . . . . . . . . . . . . . . . . . . . .4
2 MPC5674F Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6
3.2 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .9
3.3 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . .14
3.4 Signal Properties and Muxing. . . . . . . . . . . . . . . . . . . .19
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21
4.2.1 General Notes for Specifications at
Maximum Junction Temperature . . . . . . . . . . . .23
4.3 EMI (Electromagnetic Interference) Characteristics . . .24
4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .2 5
4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .29
4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.6.3 Power Sequencing and POR Dependent on VDDA
30
4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .33
4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . .34
4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 35
4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 35
4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 37
4.9.1 ADC Internal Resource Measurements . . . . . . 39
4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 40
4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 44
4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 45
4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 46
4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 47
4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.12.5 External Bus Interface (EBI) Timing. . . . . . . . . 53
4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 57
4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.12.9 DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1 324-Pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 416-Pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 516-Pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 73
Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ordering Information
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 3
1 Ordering Information
1.1 Orderable Parts
Figure 1 and Table 1 describe and list the orderable part numbers for the MPC5674F.
Figure 1. MPC5674F Orderable Part Number Description
Table 1. Orderable Part Numbers
Freescale Part Number Package Description Speed (MHz)1
1For the operating mode frequency of various blocks on the devi ce, see Table 28.
Operating Temperature2
Nominal Max3 (fMAX)Min (T
L)Max (T
H)
SPC5674FK0MVR3 416 PBGA, no EBI, Pb-free 264 270 –40 °C 125 °C
SPC5674FK0MVY3 516 PBGA, w/EBI, Pb-free 264 270 –40 °C 125 °C
SPC5674FK0MVV3R 516 PBGA, w/EBI, SnPb 264 270 –40 °C 125 °C
SPC5674FK0MVV3 516 PBGA, w/EBI, SnPb 264 200 –40 °C 125 °C
SPC5674FK0MVY3R 516 PBGA, w/EBI, Pb-free 264 270 –40 °C 125 °C
SPC5674FK0MVY3 516 PBGA, w/EBI, Pb-free 264 270 –40 °C 125 °C
SPC5673FK0MVR2R 416 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVR2 416 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVV2R 324 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
SPC5673FK0MVV2 324 PBGA, no EBI, Pb-free 200 200 –40 °C 125 °C
MPC M
R
Qualification status
Core code
Device number
Fab Revision ID
Revision of Silicon
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = –40 °C to 125 °C Package Identifier
VZ = 324 BGA Pb-free
VR = 416 BGA Pb-free
VY = 516 BGA Pb-free
VV = 516 BGA SnPb
Operating Frequency
2=200MHz
3=264MHz
Tape and Reel Status
R = Tape and reel
(blank) = Trays
Qualification Status
P = Pre qu alificatio n
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Note: Not all options are
available on all
devices. Refer to
Table 1.
5674F VR
Revision of Silicon
3 = Rev 3 (ATMC)
0 = Rev 0 (TSMC14)
F 3 3
Fab Revision ID
F=ATMC
K = TSMC14
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Ordering Information
Freescale Semiconductor4
1.2 MPC567xF Family Differences
Table 2 lists the differences between the MPC567xF devices. Refer to the MPC5674F Reference Manual for a full feature list
and comparison.
2The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
3Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
Table 2. MPC567xF Family Differences
Feature MPC5674F MPC5674F MPC5673F MPC5673F
Package 416 BGA
516 BGA 324 BGA 416 BGA
516 BGA 324 BGA
Flash 4 MB 4 MB 3 MB 3 MB
SRAM 256 KB 256 KB 192 KB 192 KB
External bus Yes
(516 BGA only) No Yes
(516 BGA only) No
Serial 3 2 3 2
eSCI_A Yes Yes Yes Yes
eSCI_B Yes Yes Yes Yes
eSCI_C Yes No Yes No
SPI 4 3 4 3
DSPI_A Yes No Yes No
DSPI_B Yes Yes Yes Yes
DSPI_C Yes Yes Yes Yes
DSPI_D Yes Yes Yes Yes
eMIOS 32 channel 22 channel 32 channel 22 channel
eTPU2 64 channel 47 channel 64 channel 47 channel
eTPU_A Yes (32 ch) Yes (26 ch) Yes Yes (26 ch)
eTPU_B Yes (32 ch ) Yes (21 ch, no
TCRCLK) Yes Yes (2 1 ch, no
TCRCLK)
ADC 64 channel 48 chann el 64 channel 48 channel
eQADC_A Yes (64 ch)1
1There are are two pairs of 24 channels plus 16 shared channels. This gives 64 channels total: 40 per
ADC (since 16 are shared).
Yes (24 ch) Yes (64 ch)1Yes (24 ch)
eQADC_B Yes (24 ch) Yes (24 ch)
MPC5674F Blocks
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 5
2 MPC5674F Blocks
2.1 Block Diagram
Figure 2 shows a top-level block diagram of the MPC5674F device.
Figure 2. Block Diagram
3 Pin Assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see Appendix A,
Signal Properties and Muxing.
JTAG
MPC5674F
FlexCAN
FlexCAN
FlexCAN
FlexCAN
eSCI
DSPI
DSPI
DSPI
DSPI
eSCI
eTPU2
32
6KB
Data
24KB
Code
eMIOS
32
Channel Channel
eTPU2
32
Channel
RAM
RAM
Crossbar Switch
MPU
eDMA2 eDMA2
64 Channel 32 Channel
Interrupt
Controller SPE2
VLE
MMU
Power™
16K
I-Cache 16K
D-Cache
e200z7 Core
Nexus
FlexRay EBI
(Calibration
&
Development
Use)
ADCi
AMux
ADCi
ADC
I/O
Bridge
4MB
Flash 256KB SRAM
(32K S/B) Boot Assist
Module
SIU I/O
Bridge
ADC – Analog to digital convertor
ADCi – ADC interface
AMux – Analog multiplexer
DECFIL – Decimation filter
DSPI – Deserial/serial peripheral interface
EBI – External bus interface
ECSM – Error correction status module
eDMA2 – Enhanced direct memory access
eMIOS – Enhanced modular I/O system
eQADC – Enhanced queued A/D converter module
eSCI – Enhanced serial communications i nterface
eTPU2 – Enhanced time processing unit 2
FlexCAN– Controller area network
MMU – Memory management unit
MPU – Memory protection unit
S/B – Stand-by
SIU – System integration unit
SPE2 – Signal processing engine 2
SRAM – General-purpose st atic RAM
VLE – Variable length instruction encoding
LEGEND
eSCI
ADC
ADC
ADC
eQADC eQADC
DECFILx8
ECSM
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor6
3.1 324-ball TEPBGA Pin Assignments
Figure 3 shows the 324-ball TEPBGA pin assignments. The same information is shown in Figure 4 through Figure 5.
Figure 3. MPC5674F 324-ball TEPBGA (full diagram)
VSS
1234567891011121314
VDD RSTOUT ANA0 ANA15 VDDA_A0A
VDDEH1 VSS VDD TEST ANA2 ANA3 ANA7 VSSA_A1
B
VSS VDD ANA8 ANA10 ANA13 ANA17 ANA19 ANA21 ANA23 ANB10 ANB9C
VSS VDD ANA11 ANA14 ANA18 ANA20 ANB8 ANB13D
E
F
G
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
H
VSSVDDE2 VSS VSS
J
K
L
M
VSS VDD EMIOS18W
VSS EMIOS14Y
VDD EMIOS13AA
VSS VDD EMIOS11AB
ANA12
ANA9
ANA1 VRL_A
VDDE2
FR_A_
ANA5ANA4
ETPUA21
ANA16
ENGCLK
ANA6
ANA22
EMIOS9EMIOS8VDDVDDEH4PCSB2
BOOT-
RDYPLLCFG0RESETJCOMP
TMSMDO13TDO
TDITCK FR_A_ EMIOS5EMIOS2SCKBSCKA PCSB0
FR_A_ PCSA5 EMIOS10EMIOS3SINBSINA EMIOS0
FR_B_ PCSA0 EMIOS7EMIOS4SOUTBSOUTA EMIOS1
15 16 17 18 19 20 21 22
VRL_B ANB3 ANB6 ANB7 ANB22 VSS
ANB4 ANB5 ANB19 ANB23 VSS
ANB11 ANB12 ANB14 ANB16 ANB20 VSS
ANB17 ANB18 VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
CNRXB VSS
CNTXB CNRXD VSS VDD VDDSYN
CNRXA SCKC SINC VSS
SOUTC PCSC0 VSS
A
B
C
D
E
F
G
H
J
K
L
M
ANB2VRH_B
ANB1
ANB15
XTAL
CNTXD
ANB21
ETPUC12
ETPUB10 ETPUB11 ETPUB9
VDD VDD33_3CNRXCCNTXCEMIOS31
EMIOS30EMIOS26EMIOS23
EMIOS29EMIOS28EMIOS25
CNTXAEMIOS24EMIOS20 VDDEH4
VDD
12345678910111213141516171819202122
MSEO1 EVTIN
MDO1P
R
T
U
V
MCKO
MDO0
VDDE2
EVTO
MDO5MDO4MDO3MDO2
VDDE2MDO8MDO7MDO6
MDO15MDO11MDO10MDO9
VDD33_2MDO14VDDE2MDO12
ETPUB0 VDDEH6 ETPUB8 ETPUB6
TCRCLKB ETPUB16 ETPUB5 ETPUB4
ETPUB1 ETPUB17 ETPUB3 ETPUB2
ETPUB19 ETPUB18 VDDEH6 REGCTL
ETPUB31 ETPUB30 VSSSYN
VDD
N
P
R
T
U
V
VDDREG
REGSEL VSSFL EXTAL
VSSVDDE2 VDDE2 VSS
VSSVDDE2 VDDE2 VSS
VSS VSS
VSS VSS
W
Y
AA
AB
ETPUA23
ETPUA20
ETPUA13
ETPUA10
ETPUA5
ETPUA1
TCRCLKA
ETPUA25
ETPUA22
ETPUA14
ETPUA11
ETPUA6
ETPUA2
ETPUA26
ETPUA31
ETPUA24
ETPUA15
ETPUA12
ETPUA9
ETPUA3
VDD
ETPUA30
ETPUA27
ETPUA17
ETPUA16
ETPUA4
VSTBY
EMIOS22
EMIOS15
EMIOS17
EMIOS12
EMIOS27
EMIOS19
EMIOS21
EMIOS16
TX_EN TX_EN
RX
TX
ETPUC20
ETPUC27
ETPUC31
ETPUB7
ETPUC14
ETPUC18
ETPUC23
ETPUC30
ETPUB13
ETPUC13
ETPUC19
ETPUC22
ETPUC26
ETPUC29
ETPUB14
ETPUC9
ETPUC17
ETPUC21
ETPUC24
ETPUC25
ETPUC28
ETPUC10 ETPUC11 ETPUC4
ETPUC2
TCRCLKC
ETPUC3
ETPUC0
PLLCFG1
VDDA_ B0 REF–
BYPCB1
REF–
BYPCB VDDA_ B1 VSSA_ B0
PLLCFG2 VDDEH1
MSEO0
VDD FR_B_
TX
VSS FR_B_
RX
ETPUB12 VDDEH7
MPC5674F 324 TEPBGA
(as viewed from top through the package)
VRH_A REF–
BYPCB1
ANB0
REF–
BYPCA
VDDA_A0
VDDEH7
ETPUC1
ETPUC5
VDDEH7
ETPUA0
CFG1
VDDE2
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 7
Figure 4. MPC5674F 324-ball TEPBGA (1 of 2)
VSS
1234567891011
VDD RSTOUT ANA0 ANA15 VDDA_A0
A
VDDEH1 VSS VDD TEST ANA2 ANA3 ANA7 VSSA_A1
B
VSS VDD ANA8 ANA10 ANA13 ANA17 ANA19 ANA21
C
VSS VDD ANA11 ANA14 ANA18 ANA20
D
E
F
G
VSS VSS VSS
VSS VSS VSS
VSS VSS VSS
H
VDDE2 VSS VSS
J
K
L
M
VSS VDD
W
VSS
Y
VDD
AA
VSS VDD
AB
ANA12
ANA9
ANA1 VRL_A
VDDE2
FR_A_
ANA5ANA4
ETPUA21
ANA16
ENGCLK
ANA6
EMIOS9EMIOS8VDDVDDEH4PCSB2
BOOT-
RDYPLLCFG0RESETJCOMP
TMSMDO13TDO
TDITCK FR_A_ EMIOS5EMIOS2SCKBSCKA PCSB0
FR_A_ PCSA5 EMIOS10EMIOS3SINBSINA EMIOS0
FR_B_ PCSA0 EMIOS7EMIOS4SOUTBSOUTA EMIOS1
A
B
C
D
J
K
L
M
MSEO1 EVTI
N
MDO1
P
R
T
U
V
MCKO
MDO0
VDDE2
EVTO
MDO5MDO4MDO3MDO2
VDDE2MDO8MDO7MDO6
MDO15MDO11MDO10MDO9
VDD33_2MDO14VDDE2MDO12
N
P
VDDE2 VDDE2 VSS
VDDE2 VDDE2 VSS
W
Y
AA
AB
ETPUA23
ETPUA20
ETPUA13
ETPUA10
ETPUA5
ETPUA1
TCRCLKA
ETPUA25
ETPUA22
ETPUA14
ETPUA11
ETPUA6
ETPUA2
ETPUA26
ETPUA31
ETPUA24
ETPUA15
ETPUA12
ETPUA9
ETPUA3
VDD
ETPUA30
ETPUA27
ETPUA17
ETPUA16
ETPUA4
VSTBY
TX_EN TX_EN
RX
TX
PLLCFG1 PLLCFG2 VDDEH1
MSEO0
VDD FR_B_
TX
VSS FR_B_
RX
MPC5674F 324 TEPBGA
(as viewed from top through the package)
VRH_A
REF–
BYPCA
VDDA_A0
ETPUA0
CFG1
VDDE2
1234567891011
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor8
Figure 5. MPC5674F 324-ball TEPBGA (2 of 2)
12 13 14
A
B
ANA23 ANB10 ANB9
C
ANB8 ANB13
D
VSS
VSS
VSS
VSS
J
K
L
M
EMIOS18
W
EMIOS14
Y
EMIOS13
AA
EMIOS11
AB
ANA22
15 16 17 18 19 20 21 22
VRL_B ANB3 ANB6 ANB7 ANB22 VSS
ANB4 ANB5 ANB19 ANB23 VSS
ANB11 ANB12 ANB14 ANB16 ANB20 VSS
ANB17 ANB18 VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
CNRXB VSS
CNTXB CNRXD VSS VDD VDDSYN
CNRXA SCKC SINC VSS
SOUTC PCSC0 VSS
A
B
C
D
E
F
G
H
J
K
L
M
ANB2VRH_B
ANB1
ANB15
XTAL
CNTXD
ANB21
ETPUC12
ETPUB10ETPUB11 ETPUB9
VDD VDD33_3CNRXCCNTXCEMIOS31
EMIOS30EMIOS26EMIOS23
EMIOS29EMIOS28EMIOS25
CNTXAEMIOS24EMIOS20 VDDEH4
VDD
N
P
ETPUB0 VDDEH6 ETPUB8 ETPUB6
TCRCLKB ETPUB16 ETPUB5 ETPUB4
ETPUB1 ETPUB17 ETPUB3 ETPUB2
ETPUB19 ETPUB18 VDDEH6 REGCTL
ETPUB31 ETPUB30 VSSSYN
VDD
N
P
R
T
U
V
VDDREG
REGSEL VSSFL EXTAL
VSS
VSS
VSS VSS
VSS VSS
W
Y
AA
AB
EMIOS22
EMIOS15
EMIOS17
EMIOS12
EMIOS27
EMIOS19
EMIOS21
EMIOS16
ETPUC20
ETPUC27
ETPUC31
ETPUB7
ETPUC14
ETPUC18
ETPUC23
ETPUC30
ETPUB13
ETPUC13
ETPUC19
ETPUC22
ETPUC26
ETPUC29
ETPUB14
ETPUC9
ETPUC17
ETPUC21
ETPUC24
ETPUC25
ETPUC28
ETPUC10 ETPUC11 ETPUC4
ETPUC2
TCRCLKC
ETPUC3
ETPUC0
VDDA_ B0 REF–
BYPCB1
REF–
BYPCB VDDA_ B1VSSA_ B0
ETPUB12 VDDEH7
MPC5674F 324 TEPBGA
(as viewed from top through the package)
REF–
BYPCB1
ANB0
VDDEH7
ETPUC1
ETPUC5
VDDEH7
12 13 14 15 16 17 18 19 20 21 22
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 9
3.2 416-ball TEPBGA Pin Assignments
Figure 6 shows the 416-ball TEPBGA pin assignments in one fi gure. The same information is shown in Figure 7 through
Figure 10.
Figure 6. MPC5674F 416-ball TEPBGA (full diagram)
VSSFL
REGCTL
ETPUB26
TDO
MDO15
VDDE2
VDDE2
VDDE2
VSS
12345678910111213141516
VDD RSTOUT ANA0 ANA15
VDDA_A0
VRH_A AN28 AN32 AN36
VDDA_B0
A
VDDEH1 VSS VDD TEST ANA1 ANA5 ANA14
VDDA_A1
REF– AN24 AN27 AN29 AN33
VDDA_B1
B
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA23 AN26
AN30
AN34 AN37
C
VSS VDD ANA3 ANA12 ANA18 ANA20 AN25 AN31 AN35 AN39
D
E
F
G
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
H
VSSVDDE2 VSS VSS
J
K
L
M
VSS VDDE2 VDD
AC
VSS FR_A_ EMIOS5
AD
VSS FR_A_ EMIOS6
AE
VSS VDDE2 EMIOS7
AF
ANA7
ANA9
ANA4
MPC5674F 416-ball TEPBGA
(as viewed from top through the package)
VRL_A
VSSA_A1
PCSA1
FR_A_
ANA11ANA8
ETPUA30
ANA16
VDD
PCSA5
ANA10
ANA22
VDDEH4VDDEH3PCSB1PCSB4PCSA2
ETPUA2
VSTBYRXDATXDAVDD33_1
VDDTDIVDDE2
VDDENGCLK FR_B_ EMIOS2PCSB3SCKASOUTA PCSB0
FR_B_ PCSA0PCSA4 EMIOS3EMIOS0SCKBPCSA3 SINB
FR_B_ PCSB5VDDEH3 EMIOS4EMIOS1PCSB2SINA SOUTB
17 18 19 20 21 22 23 24 25 26
VRL_B VRH_B ANB14 ANB17 ANB21 ANB23 VSS
REF– ANB6 ANB10 ANB15 ANB18 ANB22 VSS
ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS
ANB2 ANB9 ANB13 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
VDDEH4 TXDC VSS
A
B
C
D
E
F
G
H
J
K
L
M
ANB1
AN38
ANB11ANB7
ANB8
ANB3
XTAL
VDDEH5
VSSA_B0
ANB20
ETPUC7
ETPUB15ETPUB14 VDDEH7
VDD VDDEH6VDDEH5CNRXDCNRXB
SCKCCNTXDCNTXB
PCSC0CNRXCCNRXA
SOUTCCNTXCCNTXA PCSC4
VDD
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WKPCFG VDDN
VDDEH1P
R
T
U
V
W
Y
AA
AB
PLLCFG2
RDY
RXDB
TXDB
PLLCFG0
EVTI
RESETJCOMP
MSEO1MCKOVDDE2
MDO1MDO0MSEO0EVTO
MDO5MDO4MDO3MDO2
VDDE2MDO8MDO7MDO6
MDO11MDO10MDO9
VDD33_2MDO14MDO13MDO12
VDDTMSTCK
VDDEH6 ETPUB11 ETPUB12ETPUB13
ETPUB7 ETPUB8 ETPUB9 ETPUB10
ETPUB3 ETPUB4 ETPUB5
ETPUB0 ETPUB1 ETPUB2
ETPUB19
ETPUB20
REGSEL ETPUB25 ETPUB24 ETPUB23
ETPUB29 ETPUB28 ETPUB27
VDD33_3 ETPUB30 VSSSYN
VDD
N
P
R
T
U
V
W
Y
AA
AB
ETPUB18 ETPUB17 ETPUB16
ETPUB21ETPUB22
TCRCLKB
VDDREG
ETPUB31 EXTAL
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
AC
AD
AE
AF
ETPUA27
ETPUA23
ETPUA19
ETPUA15
ETPUA11
ETPUA7
ETPUA3
TCRCLKA
ETPUA28
ETPUA24
ETPUA20
ETPUA16
ETPUA12
ETPUA8
ETPUA4
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA17
ETPUA14
ETPUA9
ETPUA5
ETPUA1
ETPUA26
ETPUA22
ETPUA18
ETPUA13
ETPUA10
ETPUA6
EMIOS8
EMIOS9
EMIOS10
EMIOS11
EMIOS14
EMIOS15
EMIOS13
EMIOS12
EMIOS18
EMIOS19
EMIOS17
EMIOS16
EMIOS22
EMIOS23
EMIOS21
EMIOS20
EMIOS27
EMIOS26
EMIOS25
EMIOS24
EMIOS31
EMIOS30
EMIOS29
EMIOS28
RX
TX_EN TX_EN
RX
TX TX
BYPCA BYPCB
ETPUC11
ETPUC15
ETPUC19
ETPUC23
ETPUC27
ETPUC31
ETPUC8
ETPUC12
ETPUC16
ETPUC20
ETPUC24
ETPUC28
ETPUC9
ETPUC13
ETPUC17
ETPUC21
ETPUC25
ETPUC29
ETPUC10
ETPUC14
ETPUC18
ETPUC22
ETPUC26
ETPUC30
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
TCRCLKC
ETPUC2
ETPUC0
ETPUB6
ETPUA0
VDDE2
BOOT–
CFG1
PLLCFG1
REF–
BYPCA1 REF–
BYPCB1
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor10
Figure 7. MPC5674F 416-ball TEPBGA (1 of 4)
12345678910111213
12345678910111213
VDD
VSS
TXDA
BOOTCFG1
ETPUA28
ETPUA24
ETPUA20
ETPUA16
ETPUA12
ETPUA8
ETPUA4
ETPUA0
VSS RSTOUT ANA0 ANA15 VDDA_A0 VRH_A AN28
VDDEH1 VDD TEST ANA1 ANA5 ANA14 VDDA_A1
REFBYPCA
AN24 AN27
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA23 AN26
VSS VDD ANA3 ANA12 ANA18 ANA20 AN25
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVDDE2 VSS VSS
ANA7
ANA9
ANA4 VRL_A
VSSA_A1
ANA11ANA8
ETPUA30
ANA16
ANA10
ANA22
ETPUA2
VSTBYRXDAVDD33_1
WKPCFG VDDRXDB
ETPUA27
ETPUA23
ETPUA19
ETPUA15
ETPUA11
ETPUA7
ETPUA3
TCRCLKA
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA17
ETPUA14
ETPUA9
ETPUA5
ETPUA1
ETPUA26
ETPUA22
ETPUA18
ETPUA13
ETPUA10
ETPUA6
A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
MPC5674F 416-ball TEPBGA
(as viewed from top through the package)
(1 of 4)
REFBYP-
CA1
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 11
Figure 8. MPC5674F 416-ball TEPBGA (2 of 4)
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
AN32 AN36 VDDA_B0
AN29 AN33 VDDA_B1
AN30 AN34 AN37
AN31 AN35 AN39
VRL_B VRH_B ANB14 ANB17 ANB21 ANB23 VSS
REFBYPCB
ANB6 ANB10 ANB15 ANB18 ANB22 VSS
ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 VSS
ANB2 ANB9 ANB13 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
ANB1
AN38
ANB11ANB7
ANB8
ANB3
VSSA_B0
ANB20
ETPUC7
ETPUB15 ETPUB14 VDDEH7
VDDEH6 ETPUB11 ETPUB12 ETPUB13
ETPUC11
ETPUC15
ETPUC19
ETPUC23
ETPUC27
ETPUC31
ETPUC8
ETPUC12
ETPUC16
ETPUC20
ETPUC24
ETPUC28
ETPUC9
ETPUC13
ETPUC17
ETPUC21
ETPUC25
ETPUC29
ETPUC10
ETPUC14
ETPUC18
ETPUC22
ETPUC26
ETPUC30
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
TCRCLKC
ETPUC2
ETPUC0
A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
MPC5674F 416-ball TEPBGA
(as viewed from top through t he package)
(2 of 4)
REFBYP-
CB1
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor12
Figure 9. MPC5674F 416-ball TEPBGA (3 of 4)
VDDE2
VDDE2
TDO
MDO15
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
VSS
VDDE2
TDI
VDD
PLLCFG1
RESET
MCKO
MSEO0
MDO3
MDO7
MDO10
MDO13
TCK
VSS VDDE2 VDD
VSS EMIOS5
EMIOS6
VSS EMIOS7
PCSA1
VDD
PCSA5
VDDEH4VDDEH3PCSB1PCSB4PCSA2VDDVDDE2
ENGCLK FR_B_TX EMIOS2PCSB3SCKASOUTA PCSB0
FR_B_RX PCSA0PCSA4 EMIOS3EMIOS0SCKBPCSA3 SINB
PCSB5VDDEH3 EMIOS4EMIOS1PCSB2SINA SOUTB
VDDEH1PLLCFG2
RDY
TXDB
PLLCFG0
EVTI
JCOMP
MSEO1VDDE2
MDO1MDO0EVTO
MDO5MDO4MDO2
VDDE2MDO8MDO6
MDO11MDO9
VDD33_2MDO14MDO12
VDDTMS
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
EMIOS8
EMIOS9
EMIOS10
EMIOS11
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12345678910111213
MPC5674F 416-ball TEPBGA
(as viewed from top through the package)
(3 of 4)
VDDE2
VDDE2
FR_B_
TX_EN
FR_A_TX
FR_A_RX
FR_A_
TX_EN
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 13
Figure 10. MPC5674F 416-ball TEPBGA (4 of 4)
REGCTL
ETPUB26
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
VDDEH4 TXDC VSS
XTAL
VDDEH5
VDD VDDEH6VDDEH5CNRXDCNRXB
SCKCCNTXDCNTXB
PCSC0CNRXCCNRXA
SOUTCCNTXCCNTXA PCSC4
VDD
ETPUB7 ETPUB8 ETPUB9 ETPUB10
ETPUB3 ETPUB4 ETPUB5
ETPUB0 ETPUB1 ETPUB2
ETPUB19
ETPUB20
REGSEL ETPUB25 ETPUB24 ETPUB23
ETPUB29 ETPUB28 ETPUB27
VDD33_3 ETPUB30 VSSSYN
VDD
ETPUB18 ETPUB17 ETPUB16
ETPUB21ETPUB22
TCRCLKB
ETPUB31 EXTAL
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
EMIOS14
EMIOS15
EMIOS13
EMIOS12
EMIOS18
EMIOS19
EMIOS17
EMIOS16
EMIOS22
EMIOS23
EMIOS21
EMIOS20
EMIOS27
EMIOS26
EMIOS25
EMIOS24
EMIOS31
EMIOS30
EMIOS29
EMIOS28
ETPUB6
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
MPC5674F 416-ball TEPBGA
(as viewed from top through t he package)
(4 of 4)
VDDREG
VSSFL
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor14
3.3 516-ball TEPBGA Pin Assignments
Figure 11 shows the 516-ball TEPBGA pin assignments in one figure. The same information is shown split into four quadrants
in Figure 12 through Figure 15.
Figure 11. MPC5674F 516-ball TEPBGA (full diagram)
TCRCLKC
VSS
VSS
MPC5674F 516-ball TEPBGA
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VDD RSTOUT ANA0 ANA15 VDDA_A0 VRH_A AN28 AN29 AN36 VDDA_B0A
VDDEH1 VSS VDD TEST ANA1 ANA5 ANA14 VDDA_A1 REF– AN24 AN27 AN30 AN32 VDDA_B1B
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA22 AN25 AN31 AN34 AN39
C
VSS VDD ANA3 ANA12 ANA18 ANA20 AN26 AN33 AN35 AN38
D
E
F
G
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
H
VSSVDDE2 VSS VSS
J
K
L
M
VSS VDDE2 VDD
AC
VSS FR_A_
AD
VSS FR_A_
AE
VDDE2 D_
AF
ANA8
ANA7
ANA4
(as viewed from top through the package)
VRL_A
VSSA_A1
PCSA1
FR_A_
ANA11ANA9
ETPUA30
ANA16
VDD
PCSA0
ANA10
ANA23
VDDEH4VDDEH3
TCRCLKA
VSTBYVDD33_1
VDD
TMS
VDDE2
VDDENGCLK FR_B_
SINB
SOUTB
D_CS0
FR_B_ PCSB5PCSA4 PCSB1
SCKA
FR_B_ PCSA2VDDEH3 PCSB0PCSB4 D_TA
17 18 19 20 21 22 23 24 25 26
VRL_B VRH_B ANB12 ANB18 ANB21
ANB23
REF– ANB4 ANB10 ANB13 ANB19 ANB22 VSS
ANB0 ANB7 ANB6 ANB11 ANB15 ANB20 VSS
ANB2 ANB14 ANB16 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
VDDEH4 TXDC
A
B
C
D
E
F
G
H
J
K
L
M
ANB1
AN37
ANB9ANB5
ANB8
ANB3
XTAL
VDDEH5
VSSA_B0
ANB17
ETPUC7
VDDEH7
VDD VDDEH6VDDEH5CNRXDCNTXB
SCKCCNTXDCNRXA
PCSC0CNRXCCNTXA
SOUTCCNTXC
CNRXB
PCSC4
VDD
1234567891011121314151617181920212223242526
VDD
N
VDDEH1P
R
T
U
V
W
Y
AA
AB
WKPCFG
PLLCFG1
MSEO1
RXDBPLLCFG2
RESET
JCOMP RDY MSEO0
VDDE2
MCKO
MDO2MDO0EVTOEVTI
MDO10MDO9MDO7
VDD33_1MDO15MDO14MDO13
VDDTDO TCK
VDDEH6
ETPUB12 ETPUB14
ETPUB8 ETPUB10
ETPUB2
ETPUB0
VDDREG
ETPUB26 ETPUB27 ETPUB24
VDD33_3 ETPUB28 VSSSYN
VDD
N
P
R
T
U
V
W
Y
AA
AB
ETPUB4 ETPUB5 ETPUB6
ETPUB16
REGCTL
ETPUB7
ETPUB30 VSSFL EXTAL
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
AC
AD
AE
AF
ETPUA27
ETPUA23
ETPUA19
ETPUA11
ETPUA5
ETPUA1
ETPUA28
ETPUA24
ETPUA20
ETPUA13
ETPUA7
ETPUA2
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA15
ETPUA8
ETPUA9
ETPUA22
ETPUA17
ETPUA3
ETPUA4
EMIOS0
EMIOS2
EMIOS3
EMIOS4
EMIOS7
EMIOS6
EMIOS5
EMIOS13
EMIOS12
EMIOS10
EMIOS9
EMIOS23
EMIOS16
EMIOS15
EMIOS20
EMIOS31
EMIOS18
EMIOS21
EMIOS14
EMIOS28
EMIOS27
EMIOS26
EMIOS25
RX
TX_EN TX_EN
RX
TX TX
BYPCA BYPCB
ETPUC12
ETPUC17
ETPUC23
ETPUC29
ETPUC8
ETPUC13
ETPUC18
ETPUC24
ETPUC30
ETPUC9
ETPUC14
ETPUC20
ETPUC26
ETPUC31
ETPUC10
ETPUC15
ETPUC21
ETPUC27
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
ETPUC2
ETPUC0
TCRCLKB
VDDE8
VDD33_1
D_ADD16
D_ADD17 D_CS3
D_CS2
VSSVDDE8
VDDE9VSS
VDDE8 VDDE10
D_DAT9
VDDE10 D_DAT6
VDDE10 D_OE D_ALE
D_RD_
VSS VDDE10
VDDE9 VSS
VDD33_6
D_DAT15
D_DAT14
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDE8 VSS VSS
VSS
VDDE8 VDDE8
VSS VSS
VDDE10
VSS
VDDE10
D_ADD29
VDD33_4
D_TS
D_CS1 D_ADD21VDDE9 VDDE9VDDE9
VDDE9 VDD33_4
VDDE9
VDDE10
ETPUA26 VSS
VSS
VDD VSSVSS
WR
D_BDIP
ETPUA18 ETPUC11
D_WE0
ETPUA14 ETPUA16 ETPUC16ETPUC19
ETPUA12 ETPUC22
TXDB RXDATXDA ETPUA6 ETPUA10 ETPUC28ETPUC25
BOOT–
CFG1 BOOT–
CFG0 ETPUA0 D_DAT13 D_DAT12 D_DAT11 D_DAT10
VDDE2
VDDE2
VDDE2
VDDE2
PLLCFG0 D_DAT8 D_DAT7 D_DAT5
D_WE2 D_WE3 D_DAT2 D_DAT3 D_DAT4
D_ADD9 D_ADD10 D_ADD11 D_WE1 ETPUB13 D_DAT0 D_DAT1
D_ADD15D_ADD14D_ADD13D_ADD12 ETPUB9 ETPUB15
D_ADD20D_ADD19D_ADD18 ETPUB3ETPUB17 ETPUB11
ETPUB23 ETPUB1
MDO3 ETPUB22ETPUB21
MDO11 MDO12 ETPUB31
PCSA5
EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29
TDI SOUTA SCKB PCSB3 EMIOS8 EMIOS22 EMIOS24
PCSA3 PCSB2 D_ADD22 D_ADD25 D_ADD28
SINA D_ADD26D_ADD23 D_ADD30
D_ADD24 D_ADD27 CLKOUT EMIOS30
ETPUB20 ETPUB19 ETPUB18REGSELETPUB29ETPUB25
VDDE2MDO6MDO5MDO4 MDO8 MDO1
REF–
BYPCA1 REF–
BYPCB1
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 15
Figure 12. MPC5674F 516-ball TEPBGA (1 of 4)
MPC5674F 516-ball TEPBGA
(as viewed from top through t he package)
(1 of 4)
VDD RSTOUT ANA0 ANA15 VDDA_A0 VRH_A AN28
VDDEH1 VSS VDD TEST ANA1 ANA5 ANA14 VDDA_A1 AN24 AN27
VSS VDD ANA2 ANA6 ANA13 ANA17 ANA19 ANA21 ANA22 AN25
VSS VDD ANA3 ANA12 ANA18 ANA20 AN26
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVDDE2 VSS VSS
ANA8
ANA7
ANA4 VRL_A
VSSA_A1
ANA11ANA9
ETPUA30
ANA16
ANA10
ANA23
PLLCFG1 RXDBPLLCFG2
ETPUA27
ETPUA23
ETPUA19
ETPUA11
ETPUA5
ETPUA1
ETPUA28
ETPUA24
ETPUA20
ETPUA13
ETPUA7
ETPUA2
ETPUA31
ETPUA29
ETPUA25
ETPUA21
ETPUA15
ETPUA8
ETPUA9
ETPUA22
ETPUA17
ETPUA3
ETPUA4
VDDE8
VSS VSS VSS VSS VSS VSS
VDDE8 VSS
VSS
VDDE8 VDDE8
ETPUA26 VSS
VSS
VDD
ETPUA18
ETPUA14 ETPUA16
ETPUA12
RXDATXDA ETPUA6
ETPUA0
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A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
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REFBYPCA
BOOTCFG0
TXDB TCRCLKA ETPUA10
BOOTCFG1
VDD RESET VDDE8D_WE0 D_WE2 D_WE3
VSTBYVDD33_1 WKPCFGD_BDIP PLLCFG0
REF-
BYPCA1
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor16
Figure 13. MPC5674F 516-ball TEPBGA (2 of 4)
ANB23
VSS
VSS
MPC5674F 516-ball TEPBGA
(as viewed from top through the package)
(2 of 4)
AN30 AN32 VDDA_B1
AN31 AN34 AN39
AN33 AN35 AN38
ANB4 ANB10 ANB13 ANB19 ANB22 VSS
ANB0 ANB7 ANB6 ANB11 ANB15 ANB20 VSS
ANB2 ANB14 ANB16 VSS VDDEH7
VDDEH7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
ANB1
AN37
ANB8
ANB3
VSSA_B0
ANB17
ETPUC7
VDDEH7
VDDEH6
ETPUC12
ETPUC17
ETPUC23
ETPUC29
ETPUC8
ETPUC13
ETPUC18
ETPUC24
ETPUC30
ETPUC9
ETPUC14
ETPUC20
ETPUC26
ETPUC31
ETPUC10
ETPUC15
ETPUC21
ETPUC27
ETPUC4 ETPUC5 ETPUC6
ETPUC3
ETPUC1
ETPUC2
ETPUC0
VDDE10
D_DAT9
VDDE10 D_DAT6
VDD33_6
D_DAT15
D_DAT14
VSS VSS VSS
VSS
VSS VSS
VDDE10
VSS
VDDE10VDDE10
VSSVSS
TCRCLKC
ETPUC11
ETPUC16ETPUC19
ETPUC22
ETPUC28ETPUC25
D_DAT13 D_DAT12 D_DAT11 D_DAT10
D_DAT8 D_DAT7 D_DAT5
D_DAT2 D_DAT3 D_DAT4
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
E
F
G
H
J
K
L
M
N
C
D
A
B
E
F
G
H
J
K
L
M
N
C
D
REFBYPCB
AN29 AN36 VDDA_B0 VRL_B VRH_B ANB12 ANB18 ANB21ANB9ANB5
REF-
BYPCB1
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 17
Figure 14. MPC5674F 516-ball TEPBGA (3 of 4)
MPC5674F 516-ball TEPBGA
(as viewed from top through the package)
(3 of 4)
VSS FR_A_RXVDD FR_B_RX PCSB5PCSA4 PCSB1 EMIOS3D_TSSINA D_ADD26D_ADD23 D_ADD30
VSS VDDE2 VDD
VSS FR_A_TX
VDDE2
PCSA1
FR_A_
PCSA0
VDDEH4VDDEH3VDDVDDE2
VDDENGCLK FR_B_TX D_CS0
FR_B_ PCSA2VDDEH3 PCSB0PCSB4 D_TA
VDDEH1
MSEO1JCOMP RDY MSEO0
VDDE2
MCKO
MDO2MDO0EVTOEVTI
MDO10MDO9MDO7
VSSVDDE2 VSS
VSSVDDE2 VSS
VSSVDDE2
VSSVDDE2 VDDE2 VDDE2
EMIOS0
EMIOS2
EMIOS4
VDD33_1
D_ADD16
D_ADD17 D_CS3
D_CS2
VDDE2
VDDE2
VDDE2
VDDE2
D_ADD9 D_ADD10 D_ADD11 D_WE1
D_ADD15D_ADD14D_ADD13D_ADD12
D_ADD20D_ADD19D_ADD18
MDO3
MDO11 MDO12
TDI SOUTA SCKB PCSB3
PCSA3 PCSB2 D_ADD22 D_ADD25 D_ADD28
D_ADD24 D_ADD27
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
12345678910111213
12345678910111213
TX_EN TX_EN
D_CLKOUT
VDDE2MDO6MDO5MDO4 MDO8 MDO1
SOUTBVDD33_1MDO15MDO14MDO13 VSSVDDE8 VDD33_4 VDDE9PCSA5
TMS SINBSCKAVDDTDO TCK VDDE9VSS D_ADD29D_CS1 D_ADD21VDDE9 EMIOS1
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Pin Assignments
Freescale Semiconductor18
Figure 15. MPC5674F 516-ball TEPBGA (4 of 4)
MPC5674F 516-ball TEPBGA
(as viewed from top through the package)
(4 of 4)
PCSC1 VSS
RXDC PCSC3 VSS VDD VDDSYN
SINC PCSC2 PCSC5 VSS
XTALVDD VDDEH6VDDEH5CNRXDCNTXB
SCKCCNTXDCNRXA
PCSC0CNRXCCNTXA VDD
ETPUB12 ETPUB14
ETPUB8 ETPUB10
ETPUB2
ETPUB0
ETPUB4 ETPUB5 ETPUB6
ETPUB16
ETPUB7
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
VSSVSS VSS VSS
EMIOS7
EMIOS6
EMIOS13
EMIOS12
EMIOS10
EMIOS16
EMIOS15
EMIOS18
EMIOS21
EMIOS28
EMIOS27
EMIOS26
TCRCLKB
VDDE10 D_OE D_ALE
D_RD_WR
ETPUB13 D_DAT0 D_DAT1
ETPUB9 ETPUB15
ETPUB3ETPUB17 ETPUB11
ETPUB23 ETPUB1
ETPUB22ETPUB21
EMIOS8 EMIOS22 EMIOS24
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
P
R
V
W
Y
AA
AB
AC
AD
AE
AF
T
U
CNRXB VDDREGVDD33_3 ETPUB28 VSSSYNEMIOS23 EMIOS31 VSS VDDE10VDD33_4
VDD ETPUB30 VSSSFL EXTALVDDE9 VSSVDDE9VDDE9VDDE9EMIOS11 EMIOS17 EMIOS19 EMIOS29
ETPUB26 ETPUB27 ETPUB24 REGCTLETPUB31
VDDEH4 TXDC VDDEH5SOUTCCNTXC PCSC4EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30
ETPUB20 ETPUB19 ETPUB18REGSELETPUB29ETPUB25
Pin Assignments
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 19
3.4 Signal Properties and Muxing
See Appendix A, Signal Properties and Muxing, for a listin g and description of the pin functions and properties.
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor20
4 Electrical Characteristics
This section contains detailed inform at ion on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5674F.
The electrical specifications are preliminary and are from previous desi gns, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these
specifications will be met. Finalized specifications will be published after complete characterization and device qualifications
have been completed.
4.1 Maximum Ratings
Table 3. Absolute Maximum Ratings1
Spec Characteristic Symbol Min Max Unit
1 1.2 V Core Supply Voltage VDD –0.3 2.0
2V
2 SRAM Standby Volt age VSTBY –0.3 6.4
3,4 V
3 Clock Synthesizer Voltage VDDSYN –0.3 5.3
4,5 V
4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 –0.3 5.3
4,5 V
5 Analog Supply Voltage (reference to VSSA6)V
DDA7–0.3 6.4 3,4 V
6 I/O Supply Voltage (fast I/O pads) VDDE –0.3 5.3
4,5 V
7 I/O Supply Voltage (medium I/O pads) VDDEH –0.3 6.4
3,4 V
8 Voltage Regulator Input Supply Voltage VDDREG –0.3 6.4
3,4 V
9 Analog Reference High Voltage (reference to VRL8)V
RH9–0.3 6.4 3,4 V
10 VSS to VSSA8 Differential Voltage VSS –V
SSA –0.1 0.1 V
11 VREF Differential Voltage VRH –V
RL –0.3 6.4
3,4 V
12 VRL to VSSA Differential V o ltage VRL –V
SSA –0.3 0.3 V
13 VDD33 to VDDSYN Differential Voltage VDD33 –V
DDSYN –0.1 0.1 V
14 VSSSYN to VSS Differential Voltage VSSSYN –V
SS –0.1 0.1 V
15 Maximum Digital Input Current 10 (per pin, applies to all
digital pins) IMAXD –3 11 3 11 mA
16 Maximum Analog Input Current 12 (per pin, applies to all
analog pins) IMAXA – 3 7 3
7,11 mA
17 Maximum Operating Temperature Range 13 – Die Junction
Temperature TJ–40.0 150.0 oC
18 Storage Temperature Range Tstg –55.0 150.0 oC
19 Maximum Solder Temperature 14
Pb-free package
SnPb package
Tsdr —
—260.0
245.0
oC
20 Moisture Sensitivity Level 15 MSL — 3 —
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 21
4.2 Thermal Characteristics
1Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only ,
and functional operation at the maxima is not guaranteed. S tress beyond the listed maxima may affect device reliabil ity or
cause permanent damage to the device.
22.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
36.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
4Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
55.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
6MPC5674F has two analog power supply pins on the pinout: VDDA_A and VDDA_B.
7MPC5674F has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.
8MPC5674F has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.
9MPC5674F has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.
10 Total injection current for all pins must not exceed 25 mA at maximum operating voltage.
11 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated
time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under
this stress condition.
12 Total injection current for all analog input pins must not exceed 15 mA.
13 Lifetime operation at these specification limits is not guaranteed.
14 Solder profile per CDF-AEC-Q100.
15 Moisture sensitivity per JEDEC test method A112.
Table 4. Thermal Chara cteristics, 416-pin TEPBGA Package1
1Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
Characteristic Symbol Value Unit
Junction to Ambient 2,3 Natural Convection (Single layer board)
2Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
RθJA 24 °C/W
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p)
4Per JEDEC JESD51-6 with the board horizontal.
RθJA 18 °C/W
Junction to Ambient (@200 ft./min., Single layer board) RθJMA 19 °C/W
Junction to Ambient (@200 ft./min., Four layer board 2s2p) RθJMA 14 °C/W
Junction to Board 5
5Thermal resistance between the die and the printed circuit boa rd per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
RθJB 9°C/W
Junction to Case 6
6Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012 .1) with the cold plate temperature used for the case
temperature.
RθJC 6°C/W
Junction to Package Top 7 Natural Convection
7Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
ΨJT 2°C/W
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor22
Table 5. Thermal Chara cteristics, 516-pin TEPBGA Package1
1Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
Characteristic Symbol Value Unit
Junction to Ambient 2,3 Natural Convection (Single layer board)
2Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
RθJA 25 °C/W
Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p)
4Per JEDEC JESD51-6 with the board horizontal.
RθJA 18 °C/W
Junction to Ambient (@200 ft./min., Single layer board) RθJMA 20 °C/W
Junction to Ambient (@200 ft./min., Four layer board 2s2p) RθJMA 15 °C/W
Junction to Board 5
5Thermal resistance between the die and the printed circuit boa rd per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
RθJB 10 °C/W
Junction to Case 6
6Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012 .1) with the cold plate temperature used for the case
temperature.
RθJC 6°C/W
Junction to Package Top 7 Natural Convection
7Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
ΨJT 2°C/W
Table 6. Thermal Characteristics, 324-pin Package1
1Thermal characteristics are targets based on simulation that are subject to change per device
characterization. This data is PRELIMINARY based on similar package used on other devices.
MPC5674F Thermal Characteristic Symbol Value Unit
Junction to ambient 2, 3, natural convection (one-layer board)
2Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance.
3Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
RθJA 29 °C/W
Junction to ambient 1, 4, natural convection (four-layer board 2s2p)
4Per JEDEC JESD51-6 with the board horizontal.
RθJA 19 °C/W
Junction to ambient (@200 ft./min., one-layer board) RθJMA 23 °C/W
Junction to ambient (@200 ft./min., four-layer board 2s2p) RθJMA 16 °C/W
Junction to board 5 (four-layer board 2s2p)
5Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
RθJB 10 °C/W
Junction to case 6RθJC 7°C/W
Junction to package top 7, natural convection ΨJT 2°C/W
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 23
4.2.1 General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ=T
A + (RθJA * PD)Eqn. 1
where:
TA= ambient temperature for the package (oC)
RθJA = junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry stan dard value that provides a quick and easy estimation of th erm a l
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the TEPBGA, these values can be dif ferent by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obt ained on a
single layer boar d i s appr opr iate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to
ambient thermal resistance:
RθJA =R
θJC + RθCA Eqn. 2
where:
RθJA = junction to ambient thermal resistance (oC/W)
RθJC = junction to case thermal resistance (oC/W)
RθCA = case to ambient thermal resistance (oC/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounti ng arrangem e nt on prin ted circuit bo ard, or chan ge the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ=T
T + (ΨJT x PD)Eqn. 3
where:
TT= thermocouple temperature on top of the package ( oC)
ΨJT = thermal characterization parameter (oC/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per J ESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
6Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
7Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor24
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling ef fects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
• C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
• G. Kromann, S. Shido re, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53-58, March 1998.
• B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of Sem iTherm , San Diego, 1999, pp. 212 -220.
4.3 EMI (Electromagnetic Interference) Characteristics
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go
to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the
device's radiated emissions operating behaviors.
Table 7. EMC Radiated Emissions Operating Behaviors: 416 BGA
Symbol Description Conditions fOSC
fSYS
Frequency
band (MHz) Level
(max.) Unit Notes
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
CLK on
FM off
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 26 dBμV1
1Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell
Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM
(GTEM) Cell Method.
50–150 30
150–500 34
500–1000 30
IEC and SAE level I2
2I = 36 dBμV
—1, 3
3S pecified according to Annex D of IEC S tandard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
416 BGA
EBI off
CLK off
FM on4
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 24 dBμV1
50–150 25
150–500 25
500–1000 21
IEC and SAE level K5—1,3
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 25
4.4 ESD Characteristics
4.5 PMC/POR/LVI Electrical Specifications
Note: For ADC internal resource measur ements, see Table 21 in Section 4.9.1, “ADC Internal Resou r ce Measurements.”
4“FM on” = FM depth of ±2%
5K = 30 dBμV
Table 8. EMC Radiated Emissions Operating Behaviors: 516 BGA
Symbol Description Conditions fOSC
fSYS
Frequency
band (MHz) Level
(max.) Unit Notes
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
516 BGA
EBI on
CLK on
FM off
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 40 dBμV1
1Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell
Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM
(GTEM) Cell Method.
50–150 48
150–500 48
500–1000 47
IEC and SAE level G2
2G = 48 dBμV
—1, 3
3S pecified according to Annex D of IEC S tandard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
VRE_TEM Radiated emissions,
electric field and
magnetic field
VDD = 1.2 V
VDDE = 3.3 V
VDDEH = 5 V
TA = 25 °C
516 BGA
EBI on
CLK on
FM on4
4“FM on” = FM depth of ±2%
40 MHz crystal
264 MHz
(fEBI_CAL =66
MHz)
0.15–50 40 dBμV1
50–150 44
150–500 41
500–1000 36
IEC and SAE level G2—1, 3
Table 9. ESD Ratings1,2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Auto motive Grade
Integrated Circuits.
2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified othe rwise in the
device specification.
Spec Characteristic Symbol Value Unit
1 ESD for Human Body Model (HBM) VHBM 2000 V
2 ESD for Charged Device Model (CDM) VCDM 750 (corners)
500 (other) V
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor26
NOTE
In the following table, "untrimmed” means “at reset" and "trimmed” means “after reset".
Table 10. PMC Operating conditions
Name Parameter Condition Min Typ Max Unit Note
VDDREG Supply voltage VDDREG
5V nominal LDO5V / SMPS5V mode 4.5 5 5.5 V 1
1Voltage should be higher than maximum VLVDREG to avoid LVD event
VDDREG Supply voltage VDDREG
3V nominal LDO3V mode 3.0 3.3 3.6 V 1
VDD33 Supply voltage VDDSYN /
VDD33 3.3V nominal LDO3V mode 3.0 3.3 3.6 V 2
2Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. V oltage should be higher than maximum VLVD33
to avoid LVD event
VDD Core supply voltage — 1.14 1.2 1.32 V 3
3Voltage should be higher than maximum VLVD12 to avoid LVD event
Table 11. PMC Electrical Specifications
ID Name Parameter Min Typ Max Unit
1V
BG Nominal bandgap reference voltage 0.608 0.620 0.632 V
1a — Untrimmed bandgap reference voltage VBG – 5% VBG VBG + 5% V
2V
DD12OUT Nominal VRC regulated 1.2V output VDD — 1.27 — V
2a — Untrimmed VRC 1.2V output variation before band
gap trim (unloaded)
Note: Voltage shoul d be higher than maximum
VLVD12 to avoid LVD event
VDD12OUT – 14% VDD12OUT VDD12OUT +10% V
2b — Trimmed VRC 1.2V output variation after band gap
trim (REGCTL load max. 20mA, VDD load max.
1A)1
VDD12OUT – 10% VDD12OUT VDD12OUT + 5% V
2c VSTEPV12 Trimming step VDD12OUT —10—mV
3V
PORC POR rising VDD 1.2V — 0.7 — V
3a — POR VDD 1.2V variation VPORC – 30% VPORC VPORC + 30%
3b — POR 1.2V hysteresis — 75 — mV
4V
LVD12 Nominal rising LV D 1.2V
Note: ~VDD12OUT × 0.87 —1.100— V
4a — Untrimmed L VD 1.2V variation before band gap trim
Note: Rising VDD VLVD12 – 6% VLVD12 VLVD12 + 6% V
4b — Trimmed LVD 1.2V variation after band gap trim
Rising VDD VLVD12 – 3% VLVD12 VLVD12 + 3% V
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 27
4c — LVD 1.2V Hysteresis 15 20 25 mV
4d VLVDSTEP12 Trimmi ng ste p LVD 1.2V — 10 — mV
5I
REGCTL VRC DC current output on REGCTL — — 20 mA
6 — Voltage regulator 1.2V current consumption
VDDREG —3—mA
7V
DD33OUT Nominal VREG 3.3V output — 3.3 — V
7a — Untrimmed VREG 3.3V output variation before band
gap trim (unloaded)
Note: Rising VDDSYN
VDD33OUT – 6% VDD33OUT VDD33OUT + 10% V
7b — T rimmed VREG 3.3V output variation after band gap
trim (max. load 80mA) VDD33OUT – 5% VDD33OUT VDD33OUT + 10% V
7c VSTEPV33 Trimming step VDDSYN — 30 — mV
8V
LVD33 Nominal rising LV D 3.3V
Note: ~VDD33OUT × 0.872 —2.950— V
8a — Untrimmed L VD 3.3V variation before band gap trim
Note: Rising VDDSYN VLVD33 – 5% VLVD33 VLVD33 + 5% V
8b — Trimmed LVD 3.3V variation after bad gap trim
Note: Rising VDDSYN VLVD33 – 3% VLVD33 VLVD33 + 3% V
8c — LVD 3.3V Hysteresis — 30 — mV
8d VLVDSTEP33 Trimmi ng ste p LVD 3.3V — 30 — mV
9I
DD33 VREG = 4.5 V, max DC output current
VREG = 4.25 V, max DC output current, crank
condition
Note: Max current supplied by VDDSYN that does
not cause it to drop below VLVD33
—
——
—80
40 mA
mA
10 — Voltage regulator 3.3V current consumption
VDDREG
Note: Except IDD33
—2—mA
11 VPORREG POR rising on VDDREG — 2.00 — V
11a — POR VDDREG variation VPORREG – 30% VPORREG VPORREG + 30% V
11b — POR VDDREG hysteresis — 250 — mV
12 VLVDREG Nominal rising LVD VDDREG
(LDO3V / LDO5V mode ) —2.950— V
12a — Untrimmed LVD VDDREG variation before band
gap trim
Note: Rising VDDREG
VLVDREG – 5% VLVDREG VLVDREG + 5% V
12b — Trimmed LVD VDDREG variation after band gap
trim
Note: Rising VDDREG
VLVDREG – 3% VLVDREG VLVDREG + 3% V
Table 11. PMC Electrical Specifications (continued)
ID Name Parameter Min Typ Max Unit
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor28
12c — LVD VDDREG Hysteresis
(LDO3V / LDO5V mode ) —30—mV
12d VLVDSTEPREG Trimmi ng ste p LVD VDDREG
(LDO3V / LDO5V mode ) —30—mV
13 VLVDREG Nominal rising LVD VDDREG
(SMPS5V mode) —4.360— V
13a — Untrimmed LVD VDDREG variation before band
gap trim
Note: Rising VDDREG
VLVDREG – 5% VLVDREG VLVDREG + 5% V
13b — Trimmed LVD VDDREG variation after band gap
trim
Note: Rising VDDREG
VLVDREG – 3% VLVDREG VLVDREG + 3% V
13c — LVD VDDREG Hysteresis
(SMPS5V mode) —50—mV
13d VLVDSTEPREG Trimmi ng ste p LVD VDDREG
(SMPS5V mode) —50—mV
14 VLVDA Nominal rising LVD VDDA — 4.60 — V
14a — Untrimmed LVD VDDA variation before band gap
trim VLVDA – 5% VLVDA VLVDA + 5% V
14b — Trimmed LVD VDDA variation after band gap trim VLVDA – 3% VLVDA VLVDA + 3% V
14c — LVD VDDA Hysteresis — 150 — mV
14d VLVDASTEP Trimming ste p LVD VDDA — 20 — mV
15 — SMPS regulator output resistance
Note: Pulup to VDDREG when high, pulldown to
VSSREG when low.
—1525Ohm
16 — SMPS regulator clock frequency (after reset) 1.0 1.5 2.4 MHz
17 — SMPS regulator overshoot at start-up2—1.321.4V
18 — SMPS maximum outpu t current — 1.0 — A
19 — Voltage variation on current step 2 (20% to 80% of
maximum current with 4 usec constant time) ——0.1V
1VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 uA. When using the
recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core
voltage is up to 1A.
2Parameter cannot be tested; this value is based on simulation and characteri zation.
Table 11. PMC Electrical Specifications (continued)
ID Name Parameter Min Typ Max Unit
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 29
4.6 Power Up/Down Sequencing
There is no power sequencing required among pow er sources during power up and power down in order to operate within
specification as long as the following two rules are me t:
• When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.
• When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the
internal 3.3V regulator.
The recommended power supply behavior is as follows: Use 25 V/mil lisecon d or slower rise time for all supplies. Power up
each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH
supplies. There is no limit on the fall time for the power supplies.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to Table 12 and Table 13.
4.6.1 Power-Up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all driver s connected t o VDDE/VDDEH. There is no limit
to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can
be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit
the characteristics described in the next paragraph.
Table 12. Power Sequence Pin States for MH and AE pads
VDD VDD33 VDDE MH Pad MH+LVDS Pads1
1MH+LVDS pads are output-only.
AE/up-down Pads
High High High Normal operation Normal operation Normal operation
— Low High Pin is tri-stated (output buffer,
input buffer, and weak pulls
disabled)
Outputs disabled Pull-ups enabled,
pull-downs disabled
Low High Low Output low,
pin unpowered Outputs disabled Output low,
pin unpowered
Low High High Pin is tri-stated (output buffer ,
input buffer, and weak pulls
disabled)
Outputs disabled Pull-ups enabled,
pull-downs disabled
Table 13. Power Sequence Pin States for F and FS pads
VDD VDD33 VDDE F and FS pads
low low high Outputs Disabled
low high — Outputs Disabled
high low low Outputs Disabled
high low high Outputs Disabled
high high low Normal operation - except no drive current
and input buffer output is unknown.1
1The pad pre-drive circuitry will function normally but since VDDE is unpowered
the outputs will not drive high even though the output pmos can be enabled.
high high high Normal Operation
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor30
If VDD is powered up first, then all pads are loaded through the drain diodes to V DDE/VDDEH. This presents a heavy load that
pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current
injection specification. There is no li mi t to how long after VDD powers up before VDDE/VDDEH must power up.
The rise times on the power supplies are to be no faster than 25 V/millisecond.
4.6.2 Power-Down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down befor e
VDDE/VDDEH must power down.
If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy
load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the
current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down.
There are no limits on the fall times for the power supplies.
4.6.3 Power Sequencing and POR Dependent on VDDA
During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any
forward-bi asing o f de vice di odes that caus es leakage current and/or POR. If the voltage dif ference between VDDA and VDDEH
is more than 1 V, the following will result :
• T riggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created,
when VDDA is sufficiently low, causes suf ficient voltage drop on VDDEH1 node monitored crosses low-voltage detect
level.
•If V
DDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part
out of reset.
• Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH –V
DDA – 1 V(diode drop)/200 KOhms)
up to (VDDEH/2 = VDDA +1V).
• Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor
since VDD = 1.32 V max.
4.7 DC Electrical Specifications
Table 14. DC Electrical Specifications
Spec Characteristic Symbol Min Max Unit
1 Core Supply Voltage (External Regulation) VDD 1.14 1.321,2 V
1a Core Supply Voltage (Internal Regulation)3VDD 1.08 1.32 V
2 I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.61,4 V
3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.251,5 V
4 3.3 V I/O Buffer Voltage VDD33 3.0 3.61,4 V
5 Analo g Supply Voltage VDDA 4.75 5.251,5 V
6a SRAM Standby Voltage
Keep-out Range: 1.2V–2V VSTBY_LOW 0.9561.2 V
6b SRAM Standby Voltage
Keep-out Range: 1.2V–2V VSTBY_HIGH 26V
7 Voltage Regulator Control Input Voltage7VDDREG 2.785.51,5 V
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 31
8 Clock Synthesizer Operating Voltage9VDDSYN 3.0 3.61,4 V
9 Fast I/O Input High Voltage
Hysteresis enabled
Hysteresis disabled
VIH_F 0.65 × VDDE
0.55 × VDDE
VDDE +0.3 V
10 Fast I/O Input Low Voltage
Hysteresis enabled
Hysteresis disabled
VIL_F V
SS –0.3 0.35 × VDDE
0.40 × VDDE
V
11 Medium I/O Input High Voltage
Hysteresis enabled
Hysteresis disabled
VIH_S 0.65 × VDDEH
0.55 × V
DDEH
VDDEH +0.3 V
12 Medium I/O Input Low Volt age
Hysteresis enabled
Hysteresis disabled
VIL_S V
SS –0.3 0.35 × VDDEH
0.40 × VDDEH
V
13 Fast I/O Input Hysteresis VHYS_F 0.1 × VDDE —V
14 Medium I/O Input Hysteresis VHYS_S 0.1 × VDDEH —V
15 Analog Input Voltage VINDC VSSA –0.1 V
DDA +0.1 V
16 Fast I/O Output High Voltage10 V
OH_F 0.8 × VDDE —V
17 Me dium I/O Output High Voltage11 VOH_S 0.8 × VDDEH —V
18 Fast I/O Output Low Voltage10 VOL_F —0.2×V
DDE V
19 Me dium I/O Output Low Voltage11 VOL_S —0.2×V
DDEH V
20 Load Capacitance (Fast I/O)12
DSC(PCR[8:9]) = 0b00
DSC(PCR[8:9]) = 0b01
DSC(PCR[8:9]) = 0b10
DSC(PCR[8:9]) = 0b11
CL—
—
—
—
10
20
30
50
pF
pF
pF
pF
21 Input Capacitance (Digital Pins) CIN —7pF
22 Input Capaci tance (Analog Pins) CIN_A —10pF
24 Operating Current 1.2 V Supplies @ fsys =264MHz
VDD @1.32 V
VSTBY13 @1.2 V and 85oC
VSTBY @6.0 V and 85oC
IDD
IDDSTBY
IDDSTBY6
—
—
—
850
0.10
0.15
mA
mA
mA
25 Operating Current 3.3 V Supplies @ fsys =264MHz
VDD3314
VDDSYN IDD33
IDDSYN
—
— note14
715 mA
mA
26 Operating Current 5.0 V Supplies @ fsys =264MHz
VDDA
Analog Reference Supply Current (Transient)
VDDREG
IDDA
IREF
IREG
—
—
—
5016
1.0
22
mA
mA
mA
Table 14. DC Electrical Specifications (continued)
Spec Characteristic Symbol Min Max Unit
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor32
27 Operating Current VDDE/VDDEH17 Suppl ies
VDDE2
VDDEH1
VDDEH3
VDDEH4
VDDEH5
VDDEH6
VDDEH7
IDD2
IDD1
IDD3
IDD4
IDD5
IDD6
IDD7
—
—
—
—
—
—
—
note17
mA
mA
mA
mA
mA
mA
mA
28 Fast I/O Weak Pull Up/Down Current18
3.0 V–3.6 V IACT_F 42 158 μA
29 Medium I/O Weak Pull Up/Down Current19
3.0 V–3.6 V
4.5 V–5.5 V
IACT_S 15
35 95
200 μA
μA
30 I/O Input Leakage Current 20 IINACT_D –2.5 2.5 μA
31 DC Injection Current (per pin) IIC –1.0 1.0 mA
32 Analog Input Current, Channel Off21, AN[0:7], AN38,
AN39
Analog Input Current, Channel Off, all other analog
inputs AN[x]
IINACT_A –250
–150
250
150
nA
nA
33 VSS Differential Voltage VSS –V
SSA –100 100 mV
34 Analog Reference Low Voltage VRL V
SSA V
SSA +100 mV
35 VRL Differential Voltage VRL –V
SSA –100 100 mV
36 Analog Reference High Voltage VRH V
DDA –100 V
DDA mV
37 VREF Differential Voltage VRH –V
RL 4.75 5.25 V
38 VSSSYN to VSS Differential Voltage VSSSYN –V
SS –100 100 mV
39
Operating Temperature Range—Ambient (Packaged)
TA (TL to TH) –40.0 125.0 οC
40 Slew rate on power supply pins — — 25 V/ms
41 Weak Pull-Up/Down Resistance22, 200 K Opti on RPUPD200K 130 280 kΩ
42 Weak Pull-Up/Down Resistance22, 100 K Option RPUPD100K 65 140 kΩ
43 Weak Pull-Up/Down Resistance22, 5 K Option RPUPD5K 1.4 7.5 kΩ
44 Pull-Up/Down Resistance Matching Ratios23
(100K/200K) RPUPDMTCH –2.5 +2.5 %
1Voltage overshoots duri ng a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
22.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
3Assumed with DC load.
45.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
56.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
6VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode.
7Regulator is functional with derated performance, with supply volt age down to 4.0 V for system with VDDREG =4.5V (min).
82.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage
should be either VDDREG = 3 .0 V (min) or 4.5 V (min) depending on the user regul ation voltage system selected.
9Required to be supplied when 3.3 V regulator is disa bled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”
Table 14. DC Electrical Specifications (continued)
Spec Characteristic Symbol Min Max Unit
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 33
4.7.1 I/O Pad Current Specifications
The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power
consumption is the sum of all outpu t pin curren ts for a particular segmen t. The output pin current can be calculated from
Table 15 based on the voltage, frequency , and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency ,
and load parameters that fall outside the values given in Table 15.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
10 IOH_F = {16,32,47,77} mA and IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V. This spec is for
characterization only.
11 IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE =4.5V;
IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDE = 3.0 V. These specs are for characterization only.
12 Applies to D_CLKOUT, external bus pins, and Nexus pins.
13 VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction
temperature of 150 oC.
14 Power requirements for the VDD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on
the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium
(MH) pads. Also refer to Table 16 for values to calculate power dissipation for specific operation.
15 This value is a target that is subject to change.
16 This value allows a 5 V reference to supply ADC + REF.
17 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad
power. Also refer to Table 15 for values to calculate power dissipation for specific operation. The total power consumption of
an I/O segment is the sum of the individual power consumptions for each pin on the segment.
18 Absolute value of current, measured at VIL and VIH.
19 Absolute value of current, measured at VIL and VIH.
20 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH.
21 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8to12oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down. See Appendix A,
Signal Properties and Muxing.
22 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics
23 Pull-up and pull-down resistances are both enabled and settings are equal.
Table 15. VDDE/VDDEH I/O Pad Average DC Current1
Spec Pad Type Symbol Frequency
(MHz) Load2
(pF) Voltage
(V) Drive/Slew
Rate Select Current (mA)
1Medium I
DRV_MH 50 50 5.25 11 16.0
2 20 505.2501 6.3
3 3.0 50 5.25 00 1.1
4 2.0 200 5.25 00 2.4
5Fast I
DRV_FC 66 10 3.6 00 7.4
666203.60110.5
766303.61012.3
866503.61135.2
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor34
4.7.2 I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption
is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be
calculated from Table 16 dependent on the voltage, frequency , and load on all F type pins. The VDD33 current draw on medium
pads can be calculated from Table 16 dependent on voltage and independent on the frequency and load on all MH type pins.
Use linear scaling to calculate pin currents for volt a ge, frequency, and load parameters that fall outside the values given in
Table 16.
The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
9 Fast w/ Slew
Control IDRV_FSR 66 50 3.6 11 12.7
10 50 50 3.6 10 6.7
11 33.33 50 3.6 01 4.2
12 20 50 3.6 00 2.6
13 20 200 3.6 00 9.1
1These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.
2All loads are lumped.
Table 16. VDD33 Pad Average DC Current1
1These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input
pins only for the medium pads.
Spec Pad Type Symbol Frequency
(MHz) Load2
(pF)
2All loads are lumped.
VDD33
(V) VDDE
(V) Drive/Slew
Rate Select Current (mA)
1MediumI
33_MH — — 3.6 5.5 — 0.0007
2FastI
33_FC 66 10 3.6 3.6 00 0.92
366203.63.6011.14
466303.63.6101.50
566503.63.6112.19
6 Fast w/ Slew
Control I33_FSR 66 50 3.6 3.6 11 0.74
750503.63.6100.52
8 33.33 50 3.6 3.6 00 0.19
920503.63.6000.19
10 20 200 3.6 3.6 00 0.19
Table 15. VDDE/VDDEH I/O Pad Average DC Current1 (continued)
Spec Pad Type Symbol Frequency
(MHz) Load2
(pF) Voltage
(V) Drive/Slew
Rate Select Current (mA)
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 35
4.7.3 LVDS Pad Specifications
LVDS pads are implemented to supp ort the MSC (Micro second Channel) protocol, which is an enhanced feature of the DSPI
module.
4.8 Oscillator and FMPLL Electrical Characteristics
Table 17. DSPI LVDS pad specification
# Characteristic Symbol Condition Min.
Value Typ.
Value Max.
Value Unit
Data Rate
1 Data Frequency fLVDSCLK ——50—MHz
Driver Specs
2 Differential output voltage VOD SRC=0b00 or 0b11 150 — 400 mV
SRC=0b01 90 — 320
SRC=0b10 160 — 480
3 Common mode voltage (LVDS),
VOS VOS — 1.06 1.2 1.39 V
4 Rise/Fall time TR/TF——2—ns
5 Propagation delay (Low to High) TPLH ——4—ns
6 Propagation delay (High to Low) TPHL ——4—ns
7 Delay (H/L), sync Mode tPDSYNC ——4—ns
8 Delay, Z to Normal (High/Low) TDZ ——500—ns
9 Diff Skew Itphla-tplhbI or
Itplhb-tphlaI TSKEW ———0.5ns
Termination
10 Trans. Line (differential Zo) — — 95 100 105 ohms
11 Temperature — — –40 — 150 °C
Table 18. FMPLL Electrical Specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH)
Spec Characteristic Symbol Min Max Unit
1 PLL Reference Frequency Range2 (Normal Mode)
Crystal Reference (PLLCFG2 = 0b0)
Crystal Reference (PLLCFG2 = 0b1)
External Reference (PLLCFG2 = 0b0)
External Reference (PLLCFG2 = 0b1)
fref_crystal
fref_crystal
fref_ext
fref_ext
8
16
8
16
20
403
20
40
MHz
2 Loss of Reference Frequency4fLOR 100 1000 kHz
3 Self Clocked Mode Frequency5fSCM 416MHz
4 PLL Lock Time6tLPLL — < 400 μs
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor36
5 Duty Cycle of Refe rence 7 tDC 40 60 %
6 Frequency un-LOCK Range fUL –4.0 4.0 % fsys
7 Frequency LOCK Range fLCK –2.0 2.0 % fsys
8 D_C LKOUT Period Jitter8, 9 Measured at fSYS Max
Cycle-to-cycle Jitter CJitter –5 5 %fclkout
9
Peak-to-Peak Frequency Modulation Range Limit
10,11
(fsys Max must not be exceeded) Cmod 04%f
sys
10 FM Depth Tolerance12 Cmod_err –0.25 0.25 %fsys
11 VCO Frequency fVCO 192 600 MHz
12 Modulation Rate Limits13 fmod 0.400 1 MHz
13 Predivider output fre quency range14 fprediv 410MHz
1All values given are initial design targets and subject to change.
2Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default
PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency ra nge. Absolute minimum loop frequency is 4 MHz.
3Upper tolerance of less than 1% is allowed on 40MHz crystal.
4“Loss of Reference Frequency” is the reference frequency detected internally , which transitions the PLL into self clocked mode.
5Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR. This
frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and
RFD values have no effect
6This specification applies to the period required for the PLL to re-lock after changing the MFD fre quency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
7 For Flexray operation, duty cycle requirements are higher.
8Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter
percentage for a given interval. D_CLKOUT divider set to divide-by-2.
9Va lues are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter +C
mod.
10 Modulation depth selected must not result in fpll value greater than th e fpll maximum specified value.
11 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in
control register are: 2%, 3%, and 4% peak-to-peak.
12 Depth tolerance is the programmed modulation depth ±0.25% of Fsys. Violating the VCO min/max range may prevent the
system from exiting reset.
13 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz
will result in reduced calibration accuracy.
14 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.
Table 18. FMPLL Electrical Specifications1 (continued)
(VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH)
Spec Characteristic Symbol Min Max Unit
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 37
4.9 eQADC Electrical Characteristics
Table 19. Oscillator Electrical Specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS =V
SSSYN =0V, T
A=T
L to TH)
1All values given are initial design targets and subject to change.
Spec Characteristic Symbol Min Max Unit
1 Crystal Mode Differential Amplitude2
(Min differential voltage between EXTAL and XTAL)
2This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.
In that case, Vextal –V
xtal ≥ 400 mV criterion has to be met for oscillator’s comparator to produce output clock.
V
crystal_diff_amp
| Vextal – Vxtal | > 0.4 V —V
2 Crystal Mode: Internal Differential Amplifier Noise
Rejection Vcrystal_diff_amp_nr —| Vextal – Vxtal | < 0.2 V V
3 EXTAL Input High Voltage
Bypass mode, External Reference VIHEXT
((VDD33/2) + 0.4 V)
—V
4 EXTAL Input Low Voltage
Bypass mode, External Reference VILEXT —
(VDD33/2) – 0.4 V
V
5XTAL Current
3
3Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
IXTAL 13mA
6 Total On-chip stray capacitance on XTAL CS_XTAL —1.5 pF
7 Total On-chip stray capacitance on EXTAL CS_EXTAL —1.5 pF
8 Crystal manufacturer’s recommended capacitive load CL See crystal spec See crystal spec pF
9 Discrete loa d capacitance to be connected to EXTAL CL_EXTAL —
(2 × C
L
–C
S_EXTAL
–C
PCB_EXTAL4)
4CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
pF
10 Discrete load capacitance to be connected to XTAL CL_XTAL —
(2 × C
L
–C
S_XTAL
–C
PCB_XTAL4)
pF
Table 20. eQADC Conver sion Specifications (Operating)
Spec Characteristic Symbol Min Max Unit
1 ADC Clock (ADCLK) Frequency fADCLK 216MHz
2 Conversion Cycles
Single Ended Conversion Cycles 12 bit resolution
Single Ended Conversion Cycles 10 bit resolution
Single Ended Conversion Cycles 8 bit resolution
Note: Differential conversion (min) is one clock
cycle less than the single-ended
conversion valu es l ist ed he re .
CC 2+14
2+12
2+10
128 + 14
128 + 12
128 + 10
ADCLK cycles
3 Stop Mode Recovery Time1TSR 10 — μs
4 Resolution2—1.25 — mV
5 INL: 8 MHz ADC Clock3INL8 –4444LSB5
6 INL: 16 MHz ADC Clock3INL16 –8484LSB
7 DNL: 8 MHz ADC Clock3DNL8 –3434LSB
8 DNL: 16 MHz ADC Clock3DNL16 –3434LSB
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor38
9 Offset Error without Calibration OFFNC 041004LSB
10 Offset Error with Calibration OFFWC –4444LSB
11 Full Scale Gain Error without Calibration GAINNC –120404LSB
12 Full Scale Gain Error with Calibration GAINWC –44,6 44,6 LSB
13 Non-Disruptive Input Injection Current 7, 8, 9, 10 IINJ –3 3 mΑ
14 Incremental Error due to injection current11, 12 EINJ –4444Counts
15 TUE value at 8 MHz 13, 14 (with calibration) TUE8 –44,6 44,6 Counts
16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 –8 8 Counts
17 Maximum differential voltage15
(DANx+ - DANx-) or (DANx- - DANx+)
PREGAIN set to 1X setting
PREGAIN set to 2X setting
PREGAIN set to 4X setting
DIFFmax
DIFFmax2
DIFFmax4
—
—
—
(VRH –V
RL)/2
(VRH –V
RL)/4
(VRH -V
RL)/8
V
V
V
18 Differential input Common mode voltage15
(DANx- + DANx+)/2 DIFFcmv (VRH –V
RL)/2
–5% (VRH –V
RL)/2
+5% V
1Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.
2At VRH –V
RL = 5.12 V, one count = 1.25 mV without using prega in.
3INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy
(12 bit resolution selected).
4New design target. Actual specification will change following characterization. Margi n for manufacturing has not been fully
included.
5At VRH –V
RL = 5.12 V, one LSB = 1.25 mV.
6The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.
7Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than
VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions.
8Exceeding limit may cause conversion error on stressed channels and on unstressed channels. T ransitions within the limit do
not affect device reliability or cause permanent damage.
9Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP =V
DDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pins at injection limits.
11 Performance expected with production silicon.
12 All channels have same 10 kΩ< Rs < 100 kΩ Channel under test has Rs = 10 kΩ, IINJ=IINJMAX,IINJMIN.
13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.
14 TUE does not apply to differential conversions.
15 Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the
differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode
voltage of the differential signal violates the Differential Input common mode voltage specification.
Table 20. eQADC Conversion Specifications (Operating) (continued)
Spec Characteristic Symbol Min Max Unit
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 39
4.9.1 ADC Internal Resource Measurements
Table 21. Power Management Cont rol (PMC) Specification
Spec Characteristic Symbol Min Typical Max Unit
PMC Normal Mode
1Bandgap 0.62 V
ADC0 channel 145 VADC145 — 0.62 — V
2Bandgap 1.2 V
ADC0 channel 146 VADC146 — 1.22 — V
3Vreg1p2 Feedback
ADC0 channel 147 VADC147 — VDD /2.045 — V
4LVD 1.2V
ADC0 channel 180 VADC180 — V
DD /1.774 — V
5 Vreg3p3 Feedback
ADC0 channel 181 VADC181 — Vreg3p3 / 5.460 — V
6LVD 3.3V
ADC0 channel 182 VADC182 — Vreg3p3 / 4.758 —V
7LVD 5.0V
ADC0 channel 183
— LDO mode
— SMPS mode
VADC183 —
VDDREG / 4.758
VDDREG/7.032
— V
Table 22. Standby RAM Regulator Electrical Specifications
Spec Characteristic Symbol Min Typ Max Unit
Normal Mode
1 St andby Regulator Output
ADC1 channel 194 VADC194 —1.2 —V
2 St andby Source Bias
150 mV to 360 mV (30mV Increment @
vref_sel)
ADC1 channel 195
Default Value 150 mV (@vref_sel = 1 1 1)
VADC195 150 —360 mV
3 St andby Brownout Reference
ADC1 channel 195 VADC195 500 —850 mV
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor40
4.10 C90 Flash Memory Electrical Characteristics
Table 23. ADC Band Gap Reference / LVI Electrical Specifications
Spec Characteristic Symbol Min Typ Max Unit
1 4.75 LVD (from VDDA)
ADC1 channel 196 VADC196 —4.75 —V
2 ADC Bandgap
ADC0 channel 45
ADC1 channel 45
VADC45 1.171 1.220 1.269 V
Table 24. Temperature Sensor Electrical Specifications
Spec Characteristic Symbol Min Typ Max Unit
1Slope
–40 °C to 100 °C ±1.0 °C
100 °C to 150 °C ±1.6 °C
ADC0 channel 128
ADC1 channel 128
VSADC1281
1Slope is the measured voltage change per °C.
—5.8 —mV/ °C
2 Accuracy
–40 °C to 150 °C
ADC0 channel 128
ADC1 channel 128
——
±10.0 —°C
Tabl e 25. Flash Program an d Eras e Specificat io n s
Spec Characteristic Symbol Min Typ1
1Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial
Max2
2Initial factory condition: ≤100 program/erase cycles, 25 oC , typ ical supply voltage, 80 MHz minimum system frequency.
Max3
3The maximum erase time occurs after the specified number of program/erase cycles. This ma ximum value is characterized
but not guaranteed.
Unit
1 Double Word (64 bits) Program Time4
4Program times are actual hardware programming times and do not include software overhead.
tdwprogram — 38 — 500 μs
2 Page Program Time4,5
5Page size is 128 bits (4 words).
tpprogram — 45 160 500 μs
3 16 KB Block Pre-program and Erase Time t16kpperase — 270 1000 5000 ms
4 64 KB Block Pre-program and Erase Time t64kpperase — 800 1800 5000 ms
5 128 KB Block Pre-program and Erase Time t128kpperase — 1500 2600 7500 ms
6 256 KB Block Pre-program and Erase Time t256kpperase — 3000 5200 15000 ms
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 41
Table 27 shows the Platform Flash Config uration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the
device reference manual for definitions of these bit fields.
Table 26. Flash EEPROM Module Life
Spec Characteristic Symbol Min Typical1
1Typical endurance is evaluated at 25 °C. Product qualification is pe rformed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance
for Nonvolatile Memory.
Unit
1 Number of program/erase cycles per block for 16 KB and 64
KB blocks over the operating temperature range (TJ)P/E 100,000 — cycles
2 Number of program/erase cycles per block for 128 KB and 256
KB blocks over the operating temperature range (TJ)P/E 1,000 100,000 cycles
3 Minimum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
2Ambient temperature averaged over duration of appli c ation, not to exceed product operating temperature range.
Retention 20
10
5
—
—
—
years
Table 27. PFCPR1 Settings vs. Frequency of Operation1
1Illegal combinations exist. Use entries from the same row in this table.
Spec Clock
Mode
Maximum Frequency2
(MHz)
2This is the nominal maximum frequency of operation: platform runs at fsys/2 i n Enhanced Mode .
APC =
RWSC WWSC DPFEN3
3For maximum flash performance, set to 0b1.
IPFEN3PFLIM4
4For maximum flash performance, set to 0b10.
BFEN5
5For maximum flash performance, set to 0b1.
Core
fsys
Platform
fplatf
1 Enhanced 264 MHz6
6This is the nominal maximum frequency of operation in Enchanced Mode. Max speed is the maximum speed
allowed including frequency modulation (FM). 270 MHz part s allow for 264 MHz system core clock(fsys)+2% FM
and 132 Mhz platform clock (fplatf)+ 2% FM.
132 MHz60b011 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
2 Enhanced/
Full 200 MHz 100 MHz 0b010 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
3 Legacy 132 MHz 132 MHz 0b100 0b01 0b0
0b1 0b0
0b1 0b00
0b01
0b1x
0b0
0b1
Default setting after reset: 0b111 0b11 0b00 0b 00 0b00 0b0
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor42
4.11 AC Specifications
4.11.1 Clocking
The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.
Figure 16. MPC5674F Block Operating Frequency Domain Diagram
Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see
Table 29 and Table 30 for descriptions of bit settings).
Table 28. MPC5674F Operating Frequencies1, 2
1The values in the table are specified at:
VDD = 1.02 V to 1.32 V
VDDE = 3.0 V to 3.6 V
VDDEH = 4.5 V to 5.5 V
VDD33 and VDDSYN = 3.0 V to 3.6 V
TA=T
L to TH.
Mode SIU_ECCR
[EBDF[0:1]]3fsys
(core)
fplatf
(platform and all blocks
except eTPU)
fetpu
(eTPU, eTPU RAM,
and NDEDI) febi_cal4,5 Unit
Enhanced 01
11 264
264 132
132 132
132 66
33 MHz
Full 01
11 200
200 100
100 200
200 50
25 MHz
Legacy 01
11 132
132 132
132 132
132 66
33 MHz
PLL
CORE
PLATFORM /
eTPU /
EBI
CAL BUS
EXTAL
D_CLKOUT
fplatf
Note: tcycsys = 1 / fsys
tcyc =1 / f
platf
÷ 2 = divide-by-2
÷ X = divide-by-X, depending on SIU_SYSDIV[BYPASS]
and SIU_SYSDIV[SYSCLKDIV].
BLOCKS /
(D_CLKOUT is not available
on all packages and cannot
be programmed for faster
than fsys/2.)
÷ 2
PLLCFG[0:1]
SIU_SYSDIV[SYSCLKDIV[0:1]]
IPG DIV SEL
ETPU DIV SEL
SIU_SYSDIV[IPCLKDIV[0:1]]
fetpu
SYSDIV
÷ X
FLASH
NDEDI
DIV febi_cal
SIU_SYSDIV[BYPASS]
X = 2, 4, 8, or 16
X=1
fsys
SIU_ECCR[EBDF[0:1]]
fperiph
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 43
2Up to the maximum frequency rating of the device (refer to Table 1). The fsys speed is the nominal maximum frequency .
270 Mhz part s allow for 264 Mhz system clock + 2% FM.
3See the MPC5674F Reference Manual for full description as not all bit combinations are valid.
4EBI/Calibration bus is not available in all packages.
5The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed
frequency of operation. Normally febi_cal =f
platf /2, but can be limited to < fplatf /2 in Full Mode.
Table 29. IPCLKDIV Settings
SIU_SYSDIV
[IPCLKDIV[0:1]] Mode Description
00 Enhanced CPU frequency is doubled (Max 264Mhz). Platform,
peripheral, and eTPU clocks are 1/2 of CPU frequency
01 Full CPU and eTPU frequency is doubled (Max 200Mhz).
Platform and peripheral clocks are 1/2 of CPU frequency.
10 — Reserved
11 Legacy CPU, eTPU, platform, and peripheral’s clocks all run at
same speed (Max 132Mhz).
Table 30. SYSCLKDIV Settings
SIU_SYSDIV
[SYSCLKDIV[0:1]] Description
00 Divide by 2.
01 Divide by 4.
10 Divide by 8.
11 Divide by 16.
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor44
4.11.2 Pad AC Specifications
Table 31. Pad AC Specifications (V DDEH =5.0V, V
DDE =3.3V)
1
1These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH.
Spec Pad SRC/DSC Out Delay2,4
L
→
H/H
→
L (ns)
2This parameter is supplied for reference and is not guaranteed by design and not tested.
Rise/Fall3,4
(ns)
3This parameter is guaranteed by characterization before qualification rather than 100% tested.
4Delay and rise/fall are measured to 20% or 80% of the respective signal.
Load Drive
(pF)
1Medium
5
5Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
00 152/165 70/74 50
2 205/220 96/96 200
3 01 28/34 12/15 50
4 52/59 28/31 200
5 11 12/12 5.3/5.9 50
6 32/32 22/22 200
7Fast
6
6Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
00
2.5 1.2
10
801 20
910 30
10 11 50
11 Fast with Slew Rate 00 40/40 16/16 50
12 50/50 21/21 200
13 01 13/13 5/5 50
14 19/19 8/8 200
15 10 8/8 2.4/2.4 50
16 12/12 5/5 200
17 11 5/5 1.1/1/1 50
18 8/8 2.6 2.6
19 Pull Up/Down (3.6 V max) — — 7500 50
20 Pull Up/Down (5.2 5 V max) — 6000 5000/5000 50
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 45
Figure 17. Pad Output Delay
4.12 AC Timing
4.12.1 Generic Timing Diagrams
The generic timing diagrams in Figure 18 and Figure 19 apply to all I/O pins with pad types F and MH. See Appendix A, Signal
Properties and Muxing, for the pad type for each pin.
Table 32. Derated Pad AC Specifications (VDDEH =3.3V)
1
1These are worst case value s that are estimated fro m simulation and not tested. The values in the table are simulated at
VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH.
Spec Pad SRC/DSC Out Delay2,3
L
→
H/H
→
L (ns)
2This parameter is supplied for reference and is not guaranteed by design and not tested.
3Delay and rise/fall are measured to 20% or 80% of the respective signal.
Rise/Fall4,3
(ns)
4This parameter is guaranteed by characterization before qualification rather than 100% tested.
Load Drive
(pF)
1 Medium5
5Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
00 200/210 86/86 50
2 270/285 120/120 200
3 01 37/45 15.5/19 50
4 69/82 38/43 200
5 11 18/17 7.6/8.5 50
6 46/49 30/34 200
VDDEn / 2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
VDDEHn / 2
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor46
Figure 18. Generic Output Delay/Hold Timing
Figure 19. Generic Input Setup/Hold Timing
4.12.2 Reset and Configuration Pin Timing
Table 33. Reset and Configuration Pin Ti ming1
1Reset timing specifi ed at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA=T
L to TH.
Spec Characteristic Symbol Min Max Unit
1 RESET Pulse Width tRPW 10 — tcyc2
2 RESET Glitch Detect Pulse Width tGPW 2—t
cyc2
3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2
4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0—t
cyc2
VDDE / 2
D_CLKOUT
A – Maximum Output Delay Time B – Minimum Output Hold Time
VDDEn / 2
A
B
I/O Outputs VDDEHn / 2
VDDE / 2
A
B
D_CLKOUT
VDDEn / 2
I/O Inputs
A – Minimum Input Setup Time B – Minimum Input Hold Time
VDDEHn / 2
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 47
Figure 20. Reset and Configuration Pin Timing
4.12.3 IEEE 1149.1 Interface Timing
2See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1, “Clocking.”
Table 34. JTAG Pin AC Electrical Characteristics1
Spec Characteristic Symbol Min Max Unit
1 TCK Cycle Time tJCYC 100 — ns
2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns
3 TCK Rise and Fall Times (40%–70%) tTCKRISE —3ns
4 TMS, TDI Data Setup Time tTMSS, tTDIS 5—ns
5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid tTDOV —10ns
7 TCK Low to TDO Data Invalid tTDOI 0—ns
8 TCK Low to TDO High Impedance tTDOHZ —20ns
9 JCOMP Assertion T i me tJCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns
11 TCK Falling Edge to Output Valid tBSDV —50ns
12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ —50ns
13 TCK Falling Edge to Output High Impedance tBSDHZ —50ns
14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns
1
2
RESET
RSTOUT
WKPCFG
PLLCFG
3
4
BOOTCFG
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor48
Figure 21. JTAG Test Clock Input Timing
Figure 22. JTAG Test Access Port Timing
1JT AG timing specified at VDD = 1.08 V to 1.32 V , VDDE = 3.0 V to 3.6 V , VDD33 and VDDSYN = 3.0 V to 3.6 V , TA=T
L to TH, and
CL= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 35 for
functional specifications.
TCK
1
2
3
3
2
TCK
4
5
6
78
TMS, TDI
TDO
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 49
Figure 23. JTAG JCOMP Timing
Figure 24. JTAG Boundary Scan Timing
TCK
JCOMP
9
10
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor50
4.12.4 Nexus Timing
Table 35. Nexus Debug Port Timing1
1All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified
at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH, and CL= 30 pF with
DSC = 0b10.
Spec Characteristic Symbol Min Max Unit
1 M CKO Cycle Time tMCYC 22
2The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending
on the system frequency, not to exceed maximum Nexus AUX port frequency.
8t
CYC3
3See Notes on tcyc in Table 28 in Section 4.11.1 Clocking.
2 MCKO Duty Cycle tMDC 40 60 %
3 MCKO Low to MDO Data Valid4
4MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
tMDOV –0.1 0.2 tMCYC
4 MCKO Low to MSEO Data Valid4tMSEOV –0.1 0.2 tMCYC
5 MCKO Low to EVTO Data Valid4tEVTOV –0.1 0.2 tMCYC
6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC3
7 EVTO Pulse Width tEVTOPW 1—t
MCYC
8 TCK Cycle Time tTCYC 45
5Lower frequency is required to be fully compliant to standard.
—t
CYC3
9 TCK Duty Cycle tTDC 40 60 %
10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8— ns
11 TDI, TMS Data Hold Time TNTDIH, tNTMSH 5— ns
12 TCK Low to TDO Data Valid tNTDOV 010 ns
13 RDY Valid to MCKO6
6The RDY pin timing is asynchronous to MC KO. The timing is guaranteed by design to function correctly.
————
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 51
Figure 25. Nexus Timings
4
1
2
3
5
MCKO
MDO
MSEO
EVTO Output Data Valid
7
EVTI 6
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor52
Figure 26. Nexus TCK, TDI, TMS, TDO Timing
TDO
10
11
TMS, TDI
12
TCK
8
9
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 53
4.12.5 External Bus Interface (EBI) Timing
Table 36. Bus Operation Timing 1
Spec Characteristic Symbol 66 MHz (Ext. Bus Freq)2 3
Unit Notes
Min Max
1 D_CLKOUT Period tC15.2 — ns Signals are measured at 50% VDDE.
2 D_CLKOUT Duty Cycle tCDC 45% 55% tC
3 D_CLKOUT Rise T ime tCRT ——
4ns
4 D_CLKOUT Fall Tim e tCFT ——
4ns
5 D_CLKOUT Posedge to Output
Signal Invalid or High Z (Hold T ime)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
tCOH 1.0/1.5 — ns Hold time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 1.0 ns
EBTS = 1: 1.5 ns
6 D_CLKOUT Posedge to Output
Signal Valid (Output Delay)
D_ADD[9:30]
D_BDIP
D_CS[0:3]
D_DAT[0:15]
D_OE
D_RD_WR
D_TA
D_TS
D_WE[0:3]/D_BE[0:3]
tCOV — 7.0/7.5 ns Output valid time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0: 7.0 ns
EBTS = 1: 7.5 ns
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor54
Figure 27. D_CLKOUT Timing
7 Input Signal Valid to D_CLKOUT
Posedge (Setup Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
tCIS 5.0/4.5 — ns Input setu p time selectable via
SIU_ECCR[EBTS] bit:
EBTS = 0; 5.0ns
EBTS = 1; 4.5ns
8 D_CLKOUT Posedge to Input
Signal Invalid (Hold Time)
D_ADD[9:30]
D_DAT[0:15]
D_RD_WR
D_TA
D_TS
tCIH 1.0 — ns
9 D_ALE Pulse Width tAPW 6.5 — ns The timing is for Asynchronous
external memory system.
10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5— ns The timing is for Asynchronous
external memory system.
ALE is measured at 50% of VDDE.
1EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH, and
CL= 30 pF with DSC = 0b10.
2Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
270 MHz parts allow for 264 MHz system clock + 2% FM.
3Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency .
The maximum external bus frequency is 66 MHz.
4Refer to Fast pad timing in Table 31 and Table 32.
5ALE hold time spec is temperature dependant. 1.0 ns spec appli es for temperature range -40 to 0 °C. 2.0 ns spec applies to
temperatu r es > 0 °C. This spec has no dependency on SIU_ECCR[EBTS] bit.
Table 36. Bus Operation Timing 1 (continued)
Spec Characteristic Symbol 66 MHz (Ext. Bus Freq)2 3
Unit Notes
Min Max
1
2
2
3
4
D_CLKOUT
VDDE / 2
VOL_F
VOH_F
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 55
Figure 28. Synchronous Output Timing
65
5
D_CLKOUT
Bus
5
Output
Signal
Output
VDDE / 2
VDDE / 2
VDDE / 2
6
5
Output
Signal VDDE / 2
6
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor56
Figure 29. Synchronous Input Timing
Figure 30. ALE Signal Timing
7
8
D_CLKOUT
Input
Bus
7
8
Input
Signal
VDDE / 2
VDDE / 2
VDDE / 2
ipg_clk
D_CLKOUT
D_ALE
D_TS
ADDR DATA
D_ADD/D_DAT
9
10
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 57
4.12.6 External Interrupt Timing (IRQ Pin)
Figure 31. External Interrupt Timing
4.12.7 eTPU Timing
Table 37. External Interrupt Timing1
1IRQ timing specified at VDD = 1.08 V to 1.32 V , VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V , TA=T
L
to TH.
Spec Characteristic Symbol Min Max Unit
1 IRQ Pulse Width Low tIPWL 3—t
cyc2
2See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1 Clocking.
2 IRQ Pulse Width High tIPWH 3—t
cyc2
3 IRQ Edge to Edge Time3
3Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
tICYC 6—t
cyc2
Table 38. eTPU Timing1
1eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA=T
L to TH,
and CL= 200 pF with SRC = 0b00.
Spec Characteristic Symbol Min Max Unit
1 eTPU Input Channel Pulse Width tICPW 4—t
cyc2
2See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1 Clocking.
2 eTPU Output Channel Pulse Width tOCPW 13
3This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
—t
cyc2
IRQ
12
3
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor58
Figure 32. eTPU Timing
4.12.8 eMIOS T iming
Tabl e 39. eMIOS Timing1
1eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V , VDD33 and VDDSYN = 3.0 V to 3.6 V, T A=T
L to TH,
and CL= 50 pF with SRC = 0b00.
Spec Characteristic Symbol Min Max Unit
1 eMIOS Input Pulse Width tMIPW 4—t
cyc2
2See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1 Clocking.
2 eMIOS Output Pulse Width tMOPW 13
3This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
—t
cyc2
1
2
eTPU
Output
eTPU Input
and TCRCLK
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 59
Figure 33. eMIOS Timing
4.12.9 DSPI Timing
Table 40. DSPI Timing1 2
Spec Characteristic Symbol Peripheral Bus Freq: 132 MHz Unit
Min Max
1 D SPI Cycle Time3, 4
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK tSYS * 2 tSYS*32768*7 ns
2 PCS to SCK Delay5tCSC 12 — ns
3 After SCK Delay6
Master mode
Slave mode
tASC tSYS * 2
tSYS *3 –
constraints 7
—ns
4 SCK Duty Cycle tSDC 0.33 * tSCK 0.66 * tSCK ns
5 Slave Access Time
(SS active to SOUT valid) tA—25 ns
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid) tDIS —25 ns
7PCSx to PCSS time tPCSC tSYS * 2 tSYS * 7 ns
8PCSS
to PCSx time tPASC tSYS * 2 tSYS * 7 ns
1
2
eMIOS
Output
eMIOS Input
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor60
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.
DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high
speed operation.
9 Data Setup T ime for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)8
Master (MTFE = 1, CPHA = 1)
tSUI 20
4
6
20
—
—
—
—
ns
ns
ns
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)8
Master (MTFE = 1, CPHA = 1)
tHI –3
7
12
–3
—
—
—
—
ns
ns
ns
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO —
—
—
—
5
25
13
5
ns
ns
ns
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO –5
2.5
3
–5
—
—
—
—
ns
ns
ns
ns
1DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and T A=T
L to TH
2Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the ma ximum speed allowed including
frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM.
3The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two devices communicating over a DSPI link.
4The actual minimum SCK cycle time is limited by pad performance.
5The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
6The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
7For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS
8This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
Ta bl e 4 1. D SP I LVD S T im ing 1, 2
1These are typical values that are estimated from simulation.
2See DSPI LVDS Pad related data in Table 17.
Characteristic Symbol Min Max Unit
LVDS Clock to Data/Chip Select Outputs tLVDSDATA –0.25 ×
tSCYC
+0.25 ×
tSCYC
ns
Table 40. DSPI Timing1 2 (continued)
Spec Characteristic Symbol Peripheral Bus Freq: 132 MHz Unit
Min Max
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 61
Figure 34. DSPI Classic SPI Timing — Master, CPHA = 0
Figure 35. DSPI Classic SPI Timing — Master, CPHA = 1
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output 4
9
12
1
11
10
4
SCK Output
(CPOL = 0)
(CPOL = 1)
3
2
Data Last Data
First Data
SIN
SOUT
12 11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor62
Figure 36. DSPI Classic SPI Timing — Slave, CPHA = 0
Figure 37. DSPI Classic SPI Timing — Slave, CPHA = 1
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
Electrical Characteristics
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 63
Figure 38. DSPI Modified Transfer Format Timing — Master, CPHA = 0
Figure 39. DSPI Modified Transfer Format Timing — Master, CPHA = 1
PCSx3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL = 0)
(CPOL = 1)
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL = 0)
(CPOL = 1)
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Electrical Characteristics
Freescale Semiconductor64
Figure 40. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
Figure 41. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
Figure 42. DSPI PCS Strobe (PCSS) Timing
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL = 0)
(CPOL = 1)
12
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL = 0)
(CPOL = 1)
PCSx
78
PCSS
Package Information
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 65
5 Package Information
The latest package outline drawings are avail able on the product summary pages on our website:
http://www.freescale.com/powerarchitecture. The following table lists the package case number. Use these numbers in the
webpage’s keyword search engine to find the latest package outline drawings.
Table 42. Package Information
Package Type Case Outline Number
324 TEPBGA 98ASS23840W
416 TEPBGA 98ARE10523D
516 TEPBGA 98ARS10503D
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Package Information
Freescale Semiconductor66
5.1 324-Pin Package
The package drawings of the 324-pin TEPBGA package are shown in Figure 43 and Figure 44.
Figure 43. 324 TEPBGA Package (1 of 2)
Package Information
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 67
Figure 44. 324 TEPBGA Package (2 of 2)
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Package Information
Freescale Semiconductor68
5.2 416-Pin Package
The package drawings of the 416-pin TEPBGA package are shown in Figure 45 and Figure 46.
Figure 45. 416 TEPBGA Package (1 of 2)
Package Information
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 69
Figure 46. 416 TEPBGA Package (2 of 2)
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Package Information
Freescale Semiconductor70
5.3 516-Pin Package
The package drawings of the 516-pin TEPBGA package are shown in Figure 47 and Figure 48.
Figure 47. 516 TEPBGA Package (1 of 2)
Package Information
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 71
Figure 48. 516 TEPBGA Package (2 of 2)
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Product Documentation
Freescale Semiconductor72
6 Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.freescale.com.
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
•MPC5674F Microprocessor Reference Manual (document number MPC5674FRM).
Signal Properties and Muxing
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 73
Appendix A Signal Properties and Muxing
The following table shows the signals properties for each pin on the MPC5674F. For each port pin that has an associated
SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the
programming of the SIU_PCRn[P A] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See
Figure 49.
U
Figure 49. Supported Functions Example
Primary Functions
Secondary Functions
GPIO Functions are
are listed First
are alternate functions
listed Last
GPIO/
PCR1Signal Name2
P/
F/
GFunction
3Function Summary I/O Pad
Type
113 TCRCLKA_IRQ7_GPIO113 PTCRCLKA eTPU A TCR clock I 5V M
A1 IRQ7 External interrupt request I
A2 ———
GGPIO113 GPIO I/O
Function not implemented on th is device
Ta ble 2. Signal Properties Summary
MPC5674F Microcon troller Data Sheet, Rev. 10.1
74 Freescale Semiconductor
Table 43. Signal Properties and Muxing Summary
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
eTPU_A
113 TCRCLKA_IRQ7_
GPIO113 PTCRCLKA eTPU A TCR clock I MH VDDEH1 —/Up —/Up K1 L1 K4
A1 IRQ7 External interrupt request I
A2 —— —
GGPIO113 GPIO I/O
114 ETPUA0_ETPUA12_
GPIO114 PETPUA0 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG K2 L2 L6
A1 ETPUA12 eTPU A channel (output only) O
A2 —— —
GGPIO114 GPIO I/O
115 ETPUA1_ETPUA13_
GPIO115 PETPUA1 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J1 L3 J1
A1 ETPUA13 eTPU A channel (output only) O
A2 —— —
GGPIO115 GPIO I/O
116 ETPUA2_ETPUA14_
GPIO116 PETPUA2 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J2 L4 J2
A1 ETPUA14 eTPU A channel (output only) O
A2 —— —
GGPIO116 GPIO I/O
117 ETPUA3_ETPUA15_
GPIO117 PETPUA3 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J3 K1 H4
A1 ETPUA15 eTPU A channel (output only) O
A2 —— —
GGPIO117 GPIO I/O
118 ETPUA4_ETPUA16_
GPIO118 PETPUA4 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG J4 K2 J4
A1 ETPUA16 eTPU A channel (output only) O
A2 —— —
GGPIO118 GPIO I/O
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 75
119 ETPUA5_ETPUA17_
GPIO119 PETPUA5 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H1 K3 H1
A1 ETPUA17 eTPU A channel (output only) O
A2 —— —
GGPIO119 GPIO I/O
120 ETPUA6_ETPUA18_
GPIO120 PETPUA6 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H2 K4 K5
A1 ETPUA18 eTPU A channel (output only) O
A2 —— —
GGPIO120 GPIO I/O
121 ETPUA7_ETPUA19_
GPIO121 PETPUA7 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — J1 H2
A1 ETPUA19 eTPU A channel (output only) O
A2 —— —
GGPIO121 GPIO I/O
122 ETPUA8_ETPUA20_
GPIO122 PETPUA8 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — J2 H3
A1 ETPUA20 eTPU A channel (output only) O
A2 —— —
GGPIO122 GPIO I/O
123 ETPUA9_ETPUA21_
GPIO123 PETPUA9 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H3 J3 J3
A1 ETPUA21 eTPU A channel (output only) O
A2 —— —
GGPIO123 GPIO I/O
124 ETPUA10_ETPUA22_
GPIO124 PETPUA10 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G1 J4 K6
A1 ETPUA22 eTPU A channel (output only) O
A2 —— —
GGPIO124 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
76 Freescale Semiconductor
125 ETPUA11_ETPUA23_
GPIO125 PETPUA11 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G2 H1 G1
A1 ETPUA23 eTPU A channel (output only) O
A2 —— —
GGPIO125 GPIO I/O
126 ETPUA12_PCSB1_
GPIO126 PETPUA12 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G3 H2 J5
A1 PCSB1 DSPI B peripheral chip select O
A2 —— —
GGPIO126 GPIO I/O
127 ETPUA13_PCSB3_
GPIO127 PETPUA13 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F1 H4 G2
A1 PCSB3 DSPI B peripheral chip select O
A2 —— —
GGPIO127 GPIO I/O
128 ETPUA14_PCSB4_
GPIO128 PETPUA14 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F2 H3 H5
A1 PCSB4 DSPI B peripheral chip select O
A2 —— —
GGPIO128 GPIO I/O
129 ETPUA15_PCSB5_
GPIO129 PETPUA15 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F3 G1 G3
A1 PCSB5 DSPI B peripheral chip select O
A2 —— —
GGPIO129 GPIO I/O
130 ETPUA16_PCSD1_
GPIO130 PETPUA16 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG H4 G2 H6
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO130 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 77
131 ETPUA17_PCSD2_
GPIO131 PETPUA17 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG G4 G3 G4
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO131 GPIO I/O
132 ETPUA18_PCSD3_
GPIO132 PETPUA18 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — G4 G5
A1 PCSD3 DSPI D peripheral chip select O
A2 —— —
GGPIO132 GPIO I/O
133 ETPUA19_PCSD4_
GPIO133 PETPUA19 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — F1 F1
A1 PCSD4 DSPI D peripheral chip select O
A2 —— —
GGPIO133 GPIO I/O
134 ETPUA20_IRQ8_
GPIO134 PETPUA20 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E1 F2 F2
A1 IRQ8 External interrupt request I
A2 —— —
GGPIO134 GPIO I/O
135 ETPUA21_IRQ9_
GPIO135 PETPUA21 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C1 F3 F3
A1 IRQ9 External interrupt request I
A2 —— —
GGPIO135 GPIO I/O
136 ETPUA22_IRQ10_
GPIO136 PETPUA22 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E2 F4 F4
A1 IRQ10 External interrupt request I
A2 —— —
GGPIO136 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
78 Freescale Semiconductor
137 ETPUA23_IRQ11_
GPIO137 PETPUA23 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D1 E1 E1
A1 IRQ11 External interrupt request I
A2 —— —
GGPIO137 GPIO I/O
138 ETPUA24_IRQ12_
GPIO138 PETPUA24 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E3 E2 E2
A1 IRQ12 External interrupt request I
A2 —— —
GGPIO138 GPIO I/O
139 ETPUA25_IRQ13_
GPIO139 PETPUA25 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D2 E3 E3
A1 IRQ13 External interrupt request I
A2 —— —
GGPIO139 GPIO I/O
140 ETPUA26_IRQ14_
GPIO140 PETPUA26 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG C2 E4 E4
A1 IRQ14 External interrupt request I
A2 —— —
GGPIO140 GPIO I/O
141 ETPUA27_IRQ15_
GPIO141 PETPUA27 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG F4 D1 D1
A1 IRQ15 External interrupt request I
A2 —— —
GGPIO141 GPIO I/O
142 ETPUA28_PCSC1_
GPIO142 PETPUA28 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — D2 D2
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO142 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 79
143 ETPUA29_PCSC2_
GPIO143 PETPUA29 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG — D3 D3
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO143 GPIO I/O
144 ETPUA30_PCSC3_
GPIO144 PETPUA30 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG E4 C1 C1
A1 PCSC3 DSPI C peripheral chip select O
A2 —— —
GGPIO144 GPIO I/O
145 ETPUA31_PCSC4_
GPIO145 PETPUA31 eTPU A channel I/O MH VDDEH1 —/WKPCFG —/WKPCFG D3 C2 C2
A1 PCSC4 DSPI C peripheral chip select O
A2 —— —
GGPIO145 GPIO I/O
eTPU_B
146 TCRCLKB_IRQ6_
GPIO146 PTCRCLKB eTPU B TCR clock I MH VDDEH6 —/Up —/Up P19 T23 V25
A1 IRQ6 External interrupt request I
A2 —— —
GGPIO146 GPIO I/O
147 ETPUB0_ETPUB16_
GPIO147 PETPUB0 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N19 T24 V26
A1 ETPUB16 eTPU B channel (output only) O
A2 —— —
GGPIO147 GPIO I/O
148 ETPUB1_ETPUB17_
GPIO148 PETPUB1 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R19 T25 U22
A1 ETPUB17 eTPU B channel (output only) O
A2 —— —
GGPIO148 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
80 Freescale Semiconductor
149 ETPUB2_ETPUB18_
GPIO149 PETPUB2 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R22 T26 U23
A1 ETPUB18 eTPU B channel (output only) O
A2 —— —
GGPIO149 GPIO I/O
150 ETPUB3_ETPUB19_
GPIO150 PETPUB3 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R21 R23 T22
A1 ETPUB19 eTPU B channel (output only) O
A2 —— —
GGPIO150 GPIO I/O
151 ETPUB4_ETPUB20_
GPIO151 PETPUB4 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P22 R24 U24
A1 ETPUB20 eTPU B channel (output only) O
A2 —— —
GGPIO151 GPIO I/O
152 ETPUB5_ETPUB21_
GPIO152 PETPUB5 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P21 R25 U25
A1 ETPUB21 eTPU B channel (output only) O
A2 —— —
GGPIO152 GPIO I/O
153 ETPUB6_ETPUB22_
GPIO153 PETPUB6 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N22 R26 U26
A1 ETPUB22 eTPU B channel (output only) O
A2 —— —
GGPIO153 GPIO I/O
154 ETPUB7_ETPUB23_
GPIO154 PETPUB7 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M19 P23 T23
A1 ETPUB23 eTPU B channel (output only) O
A2 —— —
GGPIO154 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 81
155 ETPUB8_ETPUB24_
GPIO155 PETPUB8 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG N21 P24 T24
A1 ETPUB24 eTPU B channel (output only) O
A2 —— —
GGPIO155 GPIO I/O
156 ETPUB9_ETPUB25_
GPIO156 PETPUB9 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M22 P25 R22
A1 ETPUB25 eTPU B channel (output only) O
A2 —— —
GGPIO156 GPIO I/O
157 ETPUB10_ETPUB26_
GPIO157 PETPUB10 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M20 P26 T25
A1 ETPUB26 eTPU B channel (output only) O
A2 —— —
GGPIO157 GPIO I/O
158 ETPUB11_ETPUB27_
GPIO158 PETPUB11 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG M21 N24 T26
A1 ETPUB27 eTPU B channel (output only) O
A2 —— —
GGPIO158 GPIO I/O
159 ETPUB12_ETPUB28_
GPIO159 PETPUB12 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L19 N25 R23
A1 ETPUB28 eTPU B channel (output only) O
A2 —— —
GGPIO159 GPIO I/O
160 ETPUB13_ETPUB29_
GPIO160 PETPUB13 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L20 N26 P22
A1 ETPUB29 eTPU B channel (output only) O
A2 —— —
GGPIO160 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
82 Freescale Semiconductor
161 ETPUB14_ETPUB30_
GPIO161 PETPUB14 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG L21 M25 R24
A1 ETPUB30 eTPU B channel (output only) O
A2 —— —
GGPIO161 GPIO I/O
162 ETPUB15_ETPUB31_
GPIO162 PETPUB15 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — M24 R25
A1 ETPUB31 eTPU B channel (output only) O
A2 —— —
GGPIO162 GPIO I/O
163 ETPUB16_PCSA1_
GPIO163 PETPUB16 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG P20 U26 V24
A1 PCSA1 DSPI A peripheral chip select O
A2 —— —
GGPIO163 GPIO I/O
164 ETPUB17_PCSA2_
GPIO164 PETPUB17 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG R20 U25 T21
A1 PCSA2 DSPI A peripheral chip select O
A2 —— —
GGPIO164 GPIO I/O
165 ETPUB18_PCSA3_
GPIO165 PETPUB18 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T20 U24 W26
A1 PCSA3 DSPI A peripheral chip select O
A2 —— —
GGPIO165 GPIO I/O
166 ETPUB19_PCSA4_
GPIO166 PETPUB19 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG T19 U23 W25
A1 PCSA4 DSPI A peripheral chip select O
A2 —— —
GGPIO166 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 83
167 ETPUB20_
GPIO167 PETPUB20 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V26 W24
A1 —— —
A2 —— —
GGPIO167 GPIO I/O
168 ETPUB21_
GPIO168 PETPUB21 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V25 V22
A1 —— —
A2 —— —
GGPIO168 GPIO I/O
169 ETPUB22_
GPIO169 PETPUB22 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V24 V23
A1 —— —
A2 —— —
GGPIO169 GPIO I/O
170 ETPUB23_
GPIO170 PETPUB23 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W26 U21
A1 —— —
A2 —— —
GGPIO170 GPIO I/O
171 ETPUB24_
GPIO171 PETPUB24 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W25 Y25
A1 —— —
A2 —— —
GGPIO171 GPIO I/O
172 ETPUB25_
GPIO172 PETPUB25 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — W24 W21
A1 —— —
A2 —— —
GGPIO172 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
84 Freescale Semiconductor
173 ETPUB26_
GPIO173 PETPUB26 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — V23 Y23
A1 —— —
A2 —— —
GGPIO173 GPIO I/O
174 ETPUB27_
GPIO174 PETPUB27 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y25 Y24
A1 —— —
A2 —— —
GGPIO174 GPIO I/O
175 ETPUB28_
GPIO175 PETPUB28 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y24 AA24
A1 —— —
A2 —— —
GGPIO175 GPIO I/O
176 ETPUB29_
GPIO176 PETPUB29 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG — Y23 W22
A1 —— —
A2 —— —
GGPIO176 GPIO I/O
177 ETPUB30_
GPIO177 PETPUB30 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U20 AA24 AB24
A1 —— —
A2 —— —
GGPIO177 GPIO I/O
178 ETPUB31_
GPIO178 PETPUB31 eTPU B channel I/O MH VDDEH6 —/WKPCFG —/WKPCFG U19 AB24 Y22
A1 —— —
A2 —— —
GGPIO178 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 85
GPIO, IRQ, FlexRay
440 TCRCLKC_
GPIO4409P—— —MHV
DDEH7 —/Up —/Up B22 B26 F22
A1 —— —
A2 —— —
GGPIO440 GPIO I/O
441 ETPUC0_
GPIO4419P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG C21 C25 C25
A1 —— —
A2 —— —
GGPIO441 GPIO I/O
442 ETPUC1_
GPIO4429P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG D20 C26 C26
A1 —— —
A2 —— —
GGPIO442 GPIO I/O
443 ETPUC2_
GPIO4439P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG D22 D25 D25
A1 —— —
A2 —— —
GGPIO443 GPIO I/O
444 ETPUC3_
GPIO4449P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG D21 D26 D26
A1 —— —
A2 —— —
GGPIO444 GPIO I/O
445 ETPUC4_
GPIO4459P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG E22 E24 E24
A1 —— —
A2 —— —
GGPIO445 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
86 Freescale Semiconductor
446 ETPUC5_
GPIO4469P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG E19 E25 E25
A1 —— —
A2 —— —
GGPIO446 GPIO I/O
447 ETPUC6_
GPIO4479P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — E26 E26
A1 —— —
A2 —— —
GGPIO447 GPIO I/O
448 ETPUC7_
GPIO4489P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — F23 F23
A1 —— —
A2 —— —
GGPIO448 GPIO I/O
449 ETPUC8_
GPIO4499P— — I/O MH VDDEH7 —/WKPCFG —/WKPCFG — F24 F24
A1 — — —
A2 —— —
GGPIO449 GPIO I/O
450 ETPUC9_IRQ0_
GPIO4509P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F22 F25 F25
A1 IRQ0 External interrupt request I
A2 —— —
GGPIO450 GPIO I/O
451 ETPUC10__IRQ1_
GPIO4519P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG E20 F26 F26
A1 IRQ1 External interrupt request I
A2 —— —
GGPIO451 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 87
452 ETPUC11_IRQ2_
GPIO4529P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG E21 G23 G22
A1 IRQ2 External interrupt request I
A2 —— —
GGPIO452 GPIO I/O
453 ETPUC12_IRQ3_
GPIO4539P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F19 G24 G23
A1 IRQ3 External interrupt request I
A2 —— —
GGPIO453 GPIO I/O
454 ETPUC13_3_IRQ4_
GPIO4549P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F21 G25 G24
A1 IRQ4 External interrupt request I
A2 —— —
GGPIO454 GPIO I/O
455 ETPUC14_4_IRQ5_
GPIO4559P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG F20 G26 G25
A1 IRQ5 External interrupt request I
A2 —— —
GGPIO455 GPIO I/O
456 ETPUC15__
GPIO4569P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG — H23 G26
A1 —— —
A2 —— —
GGPIO456 GPIO I/O
457 ETPUC16_FR_A_TX_
GPIO4579P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG — H24 H22
A1 FR_A_TX FlexRay A transfer O
A2 —— —
GGPIO457 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
88 Freescale Semiconductor
458 ETPUC17_FR_A_RX_
GPIO4589P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G22 H25 H23
A1 FR_A_RX FlexRay A receive I
A2 —— —
GGPIO458 GPIO I/O
459 ETPUC18_
FR_A_TX_EN_
GPIO459
9
P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G20 H26 H24
A1 FR_A_TX_EN FlexRay A transfer enable O
A2 —— —
GGPIO459 GPIO I/O
460 ETPUC19_TXDA_
GPIO4609P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G21 J23 H21
A1 TXDA eSCI A transmit O
A2 —— —
GGPIO460 GPIO I/O
461 ETPUC20_RXDA _
GPIO4619P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG G19 J24 H25
A1 RXDA eSCI A receive I
A2 —— —
GGPIO461 GPIO I/O
462 ETPUC21_TXDB_
GPIO4629P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H22 J25 H26
A1 TXDB eSCI B transmit O
A2 —— —
GGPIO462 GPIO I/O
463 ETPUC22_RXDB_
GPIO4639P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H21 J26 J22
A1 RXDB eSCI B receive I
A2 —— —
GGPIO463 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 89
464 ETPUC23_PCSD5_
GPIO4649P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG H20 K23 J23
A1 PCSD5 DSPI D peripheral chip select O
A2 MAA0 ADC A Mux Address 0 O
A3 MAB0 ADC B Mux Address 0 O
GGPIO464 GPIO I/O
465 ETPUC24_PCSD4_
GPIO4659P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J22 K24 J24
A1 PCSD4 DSPI D peripheral chip select O
A2 MAA1 ADC A Mux Address 1 O
A4 MAB1 ADC B Mux Address 1 O
GGPIO465 GPIO I/O
466 ETPUC25_PCSD3_
GPIO4669P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K22 K25 K21
A1 PCSD3 DSPI D peripheral chip select O
A2 MAA2 ADC A Mux Address 2 O
A3 MAB2 ADC B Mux Address 2 O
GGPIO466 GPIO I/O
467 ETPUC26_PCSD2_
GPIO4679P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J21 K26 J25
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO467 GPIO I/O
468 ETPUC27_PCSD1_
GPIO4689P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J19 L23 J26
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO468 GPIO I/O
469 ETPUC28_PCSD0_
GPIO4699P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG J20 L24 K22
A1 PCSD0 DSPI D peripheral chip select I/O
A2 —— —
GGPIO469 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
90 Freescale Semiconductor
470 ETPUC29_SCKD_
GPIO4709P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K21 L25 K23
A1 SCKD DSPI D clock I/O
A2 —— —
GGPIO470 GPIO I/O
471 ETPUC30_SOUTD_
GPIO4719P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K20 L26 K24
A1 SOUTD DSPI D data output O
A2 —— —
GGPIO471 GPIO I/O
472 ETPUC31_SIND_
GPIO4729P—— —MHV
DDEH7 —/WKPCFG —/WKPCFG K19 M23 K25
A1 SIND DSPI D data input I
A2 —— —
GGPIO472 GPIO I/O
eMIOS
179 EMIOS0_ETPUA0_
GPIO179 PEMIOS0 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA9 AE10 AC13
A1 ETPUA0 eTPU A channel O
A2 —— —
GGPIO179 GPIO I/O
180 EMIOS1_ETPUA1_
GPIO180 PEMIOS1 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB9 AF10 AB13
A1 ETPUA1 eTPU A channel O
A2 —— —
GGPIO180 GPIO I/O
181 EMIOS2_ETPUA2_
GPIO181 PEMIOS2 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y10 AD11 AD13
A1 ETPUA2 eTPU A channel O
A2 —— —
GGPIO181 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 91
182 EMIOS3_ETPUA3_
GPIO182 PEMIOS3 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA10 AE11 AE13
A1 ETPUA3 eTPU A channel O
A2 —— —
GGPIO182 GPIO I/O
183 EMIOS4_ETPUA4_
GPIO183 PEMIOS4 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB10 AF11 AF13
A1 ETPUA4 eTPU A channel O
A2 —— —
GGPIO183 GPIO I/O
184 EMIOS5_ETPUA5_
GPIO184 PEMIOS5 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y11 AD12 AF14
A1 ETPUA5 eTPU A channel O
A2 —— —
GGPIO184 GPIO I/O
185 EMIOS6_ETPUA6_
GPIO185 PEMIOS6 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG — AE12 AE14
A1 ETPUA6 eTPU A channel O
A2 —— —
GGPIO185 GPIO I/O
186 EMIOS7_ETPUA7_
GPIO186 PEMIOS7 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB11 AF12 AD14
A1 ETPUA7 eTPU A channel O
A2 —— —
GGPIO186 GPIO I/O
187 EMIOS8_ETPUA8_
GPIO187 PEMIOS8 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W10 AC13 AC14
A1 ETPUA8 eTPU A channel O
A2 —— —
GGPIO187 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
92 Freescale Semiconductor
188 EMIOS9_ETPUA9_
GPIO188 PEMIOS9 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W11 AD13 AF15
A1 ETPUA9 eTPU A channel O
A2 —— —
GGPIO188 GPIO I/O
189 EMIOS10_SCKD_
GPIO189 PEMIOS10 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA11 AE13 AE15
A1 SCKD DSPI D clock O
A2 —— —
GGPIO189 GPIO I/O
190 EMIOS11_SIND_
GPIO190 PEMIOS11 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB12 AF13 AB14
A1 SIND DSPI D data input I
A2 —— —
GGPIO190 GPIO I/O
191 EMIOS12_SOUTC_
GPIO191 PEMIOS12 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AB13 AF14 AD15
A1 SOUTC DSPI C data output O
A2 —— —
GGPIO191 GPIO I/O
192 EMIOS13_SOUTD_
GPIO192 PEMIOS13 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG AA12 AE14 AC15
A1 SOUTD DSPI D data output O
A2 —— —
GGPIO192 GPIO I/O
193 EMIOS14_IRQ0_
GPIO193 PEMIOS14 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG Y12 AC14 AF17
A1 IRQ0 External interrupt request I
A2 CNTXD FlexCAN D transmit O
GGPIO193 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 93
194 EMIOS15_IRQ1_
GPIO194 PEMIOS15 eMIOS channel O MH VDDEH4 —/WKPCFG —/WKPCFG Y13 AD14 AE16
A1 IRQ1 External interrupt request I
A2 CNRXD FlexCAN D receive I
GGPIO194 GPIO I/O
195 EMIOS16_ETPUB0_
GPIO195 PEMIOS16 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB14 AF15 AD16
A1 ETPUB0 eTPU B channel O
A2 FR_DBG[3] FlexRay debug O
GGPIO195 GPIO I/O
196 EMIOS17_ETPUB1_
GPIO196 PEMIOS17 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA13 AE15 AB15
A1 ETPUB1 eTPU B channel O
A2 FR_DBG[2] FlexRay debug O
GGPIO196 GPIO I/O
197 EMIOS18_ETPUB2_
GPIO197 PEMIOS18 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W12 AC15 AD17
A1 ETPUB2 eTPU B channel O
A2 FR_DBG[1] FlexRay debug O
GGPIO197 GPIO I/O
198 EMIOS19_ETPUB3_
GPIO198 PEMIOS19 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y14 AD15 AB16
A1 ETPUB3 eTPU B channel O
A2 FR_DBG[0] FlexRay debug O
GGPIO198 GPIO I/O
199 EMIOS20_ETPUB4_
GPIO199 PEMIOS20 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB15 AF16 AF16
A1 ETPUB4 eTPU B channel O
A2 —— —
GGPIO199 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
94 Freescale Semiconductor
200 EMIOS21_ETPUB5_
GPIO200 PEMIOS21 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA14 AE16 AE17
A1 ETPUB5 eTPU B channel O
A2 —— —
GGPIO200 GPIO I/O
201 EMIOS22_ETPUB6_
GPIO201 PEMIOS22 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W13 AC16 AC16
A1 ETPUB6 eTPU B channel O
A2 —— —
GGPIO201 GPIO I/O
202 EMIOS23_ETPUB7_
GPIO202 PEMIOS23 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y15 AD16 AA16
A1 ETPUB7 eTPU B channel O
A2 —— —
GGPIO202 GPIO I/O
203 EMIOS24_PCSB0_
GPIO203 PEMIOS24 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AB16 AF17 AC17
A1 PCSB0 DSPI B peripheral chip select I/O
A2 —— —
GGPIO203 GPIO I/O
204 EMIOS25_PCSB1_
GPIO204 PEMIOS25 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA15 AE17 AF18
A1 PCSB1 DSPI B peripheral chip select O
A2 —— —
GGPIO204 GPIO I/O
432 EMIOS26_PCSB2_
GPIO432 PEMIOS26 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y16 AD17 AE18
A1 PCSB2 DSPI B peripheral chip select O
A2 —— —
GGPIO432 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 95
433 EMIOS27_PCSB3_
GPIO433 PEMIOS27 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W14 AC17 AD18
A1 PCSB3 DSPI B peripheral chip select O
A2 —— —
GGPIO433 GPIO I/O
434 EMIOS28_PCSC0_
GPIO434 PEMIOS28 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA16 AF18 AC18
A1 PCSC0 DSPI C peripheral chip select I/O
A2 —— —
GGPIO434 GPIO I/O
435 EMIOS29_PCSC1_
GPIO435 PEMIOS29 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG AA17 AE18 AB17
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO435 GPIO I/O
436 EMIOS30_PCSC2_
GPIO436 PEMIOS30 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG Y17 AD18 AF19
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO436 GPIO I/O
437 EMIOS31_PCSC5_
GPIO437 PEMIOS31 eMIOS channel I/O MH VDDEH4 —/WKPCFG —/WKPCFG W15 AC18 AA17
A1 PCSC5 DSPI C peripheral chip select O
A2 —— —
GGPIO437 GPIO I/O
eQADC
—ANA0 PANA010 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA0 ANA0 A4 A4 A4
—ANA1 PANA110 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA1 ANA1 A5 B5 B5
—ANA2 PANA210 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA2 ANA2 B5 C5 C5
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
96 Freescale Semiconductor
—ANA3 PANA310 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA3 ANA3 B6 D6 D6
—ANA4 PANA410 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA4 ANA4 A6 A5 A5
—ANA5 PANA510 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA5 ANA5 A7 B6 B6
—ANA6 PANA610 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA6 ANA6 B7 C6 C6
—ANA7 PANA710 eQADC A analog input I
AE/up-
down
VDDA_A1 ANA7 ANA7 B8 D7 C7
—ANA8 PANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 C5 A6 D7
—ANA9 PANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7 C7 A6
—ANA10 PANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 C6 B7 B7
—ANA11 PANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 D6 A7 A7
—ANA12 PANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D7 D8 D8
—ANA13 PANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8 C8 C8
—ANA14 PANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 D8 B8 B8
—ANA15 PANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8 A8 A8
—ANA16 PANA16 eQADC A analog input I AE VDDA_A1 ANA16 ANA16 D9 D9 D9
—ANA17 PANA17 eQADC A analog input I AE VDDA_A1 ANA17 ANA17 C9 C9 C9
—ANA18 PANA18 eQADC A analog input I AE VDDA_A1 ANA18 ANA18 D10 D10 D10
—ANA19 PANA19 eQADC A analog input I AE VDDA_A1 ANA19 ANA19 C10 C10 C10
—ANA20 PANA20 eQADC A analog input I AE VDDA_A1 ANA20 ANA20 D11 D11 D11
—ANA21 PANA21 eQADC A analog input I AE VDDA_A1 ANA21 ANA21 C11 C11 C11
—ANA22 PANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12 D12 C12
—ANA23 PANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12 C12 D12
—AN24 PAN24 eQADC A and B shared analog input I AE VDDA_A0 AN24 AN24 — B12 B12
—AN25 PAN25 eQADC A and B shared analog input I AE VDDA_A0 AN25 AN25 — D13 C13
—AN26 PAN26 eQADC A and B shared analog input I AE VDDA_A0 AN26 AN26 — C13 D13
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 97
—AN27 PAN27 eQADC A and B shared analog input I AE VDDA_A0 AN27 AN27 — B13 B13
—AN28 PAN28 eQADC A and B shared analog input I AE VDDA_A0 AN28 AN28 — A13 A13
—AN29 PAN29 eQADC A and B shared analog input I AE VDDA_A0 AN29 AN29 — B14 A14
—AN30 PAN30 eQADC A and B shared analog input I AE VDDA_B1 AN30 AN30 — C14 B14
—AN31 PAN31 eQADC A and B shared analog input I AE VDDA_B1 AN31 AN31 — D14 C14
—AN32 PAN32 eQADC A and B shared analog input I AE VDDA_B1 AN32 AN32 — A14 B15
—AN33 PAN33 eQADC A and B shared analog input I AE VDDA_B0 AN33 AN33 — B15 D14
—AN34 PAN34 eQADC A and B shared analog input I AE VDDA_B0 AN34 AN34 — C15 C15
—AN35 PAN35 eQADC A and B shared analog input I AE VDDA_B0 AN35 AN35 — D15 D15
—AN36 PAN36 eQADC A and B shared analog input I AE VDDA_B1 AN36 AN36 — A15 A15
—AN37 PAN37 eQADC A and B shared analog input I AE VDDA_B0 AN37 AN37 — C16 C17
—AN38 PAN38 eQADC A and B shared analog input I AE VDDA_B0 AN38 AN38 — C17 D16
—AN39 PAN39 eQADC A and B shared analog input I AE VDDA_B0 AN39 AN39 — D16 C16
—ANB0 PANB0 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB0 ANB0 B15 C18 C18
—ANB1 PANB1 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB1 ANB1 B16 D17 D17
—ANB2 PANB2 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB2 ANB2 A17 D18 D18
—ANB3 PANB3 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB3 ANB3 A18 D19 D19
—ANB4 PANB4 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB4 ANB4 B17 C19 B19
—ANB5 PANB5 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB5 ANB5 B18 C20 A20
—ANB6 PANB6 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB6 ANB6 A19 B19 C20
—ANB7 PANB7 eQADC B analog input I
AE/up-
down
VDDA_B0 ANB7 ANB7 A20 A20 C19
—ANB8 PANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 D13 B20 B20
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
98 Freescale Semiconductor
—ANB9 PANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 C14 D20 A21
—ANB10 PANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 C13 B21 B21
—ANB11 PANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 C15 A21 C21
—ANB12 PANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C16 C21 A22
—ANB13 PANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D14 D21 B22
—ANB14 PANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 C17 A22 D20
—ANB15 PANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 D15 B22 C22
—ANB16 PANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C18 C22 D21
—ANB17 PANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 D16 A23 D22
—ANB18 PANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 D17 B23 A23
—ANB19 PANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 B19 C23 B23
—ANB20 PANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 C19 D22 C23
—ANB21 PANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 D18 A24 A24
—ANB22 PANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 A21 B24 B24
—ANB23 PANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 B20 A25 E20
— VRH_A PVRH_A ADC A Voltage reference high I
VDDINT
VRH_A VRH_A VRH_A A10 A12 A12
— VRL_A PVRL_A ADC A Voltage reference low I
VSSINT
VRL_A VRL_A VRL_A A11 A11 A11
— VRH_B PVRH_B ADC B Voltage reference high I
VDDINT
VRH_B VRH_B VRH_B A16 A19 A19
— VRL_B PVRL_B ADC B Voltage reference low I
VSSINT
VRL_B VRL_B VRL_B A15 A18 A18
— REFBYPCB PREFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B12 B18 B18
— REFBYPCA PREFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11 B11 B11
— VDDA_A0 PVDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9 A9 A9
— VDDA_A1 PVDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9 B9 B9
— REFBYPCA1 PREFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A12 A10 A10
— VSSA_A1 PVSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10 B10 B10
— VDDA_B0 PVDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A13 A16 A16
— VDDA_B1 PVDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B13 B16 B16
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 99
— VSSA_B0 PVSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B14 B17 B17
— REFBYPCB1 PREFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A14 A17 A17
FlexRay
248 FR_A_TX_
GPIO248 PFR_A_TX FlexRay A transfer O FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
Y5 AD4 AD4
A1 —— —
A2 —— —
GGPIO248 GPIO I/O
249 FR_A_RX_
GPIO249 PFR_A_RX FlexRay A receive I FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
AA4 AE3 AE3
A1 —— —
A2 —— —
GGPIO249 GPIO I/O
250 FR_A_TX_EN_
GPIO250 PFR_A_TX_EN FlexRay A tr ansfer enable O FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
AB3 AF3 AF3
A1 —— —
A2 —— —
GGPIO250 GPIO I/O
251 FR_B_TX_
GPIO251 PFR_B_TX FlexRay B transfer O FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
Y6 AD5 AD5
A1 —— —
A2 —— —
GGPIO251 GPIO I/O
252 FR_B_RX_
GPIO252 PFR_B_RX FlexRay B receive I FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
AA5 AE4 AE4
A1 —— —
A2 —— —
GGPIO252 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
100 Freescale Semiconductor
253 FR_B_TX_EN_
GPIO253 PFR_B_TX_EN FlexRay B tr ansfer enable O FS VDDE2 —/Up
(–/– for Rev.1 of
the device)
—/Up
(–/– for Rev.1 of
the device)
AB5 AF4 AF4
A1 —— —
A2 —— —
GGPIO253 GPIO I/O
FlexCAN
83 CNTXA_TXDA_
GPIO83 PCNTXA FlexCAN A transmit O MH VDDEH4 —/Up —/Up AB17 AF19 AE19
A1 TXDA eSCI A transmit O
A2 —— —
GGPIO83 GPIO I/O
84 CNRXA_RXDA_
GPIO84 PCNRXA FlexCAN A receive I MH VDDEH4 —/Up —/Up AA18 AE19 AD19
A1 RXDA eSCI A receive I
A2 —— —
GGPIO84 GPIO I/O
85 CNTXB_PCSC3_
GPIO85 PCNTXB FlexCAN B transmit O MH VDDEH4 —/Up —/Up Y18 AD19 AC19
A1 PCSC3 DSPI C peripheral chip select O
A2 —— —
GGPIO85 GPIO I/O
86 CNRXB_PCSC4_
GPIO86 PCNRXB FlexCAN B receive I MH VDDEH4 —/Up —/Up W18 AC19 AA19
A1 PCSC4 DSPI C peripheral chip select O
A2 —— —
GGPIO86 GPIO I/O
87 CNTXC_PCSD3_
GPIO87 PCNTXC FlexCAN C transmit O MH VDDEH4 —/Up —/Up W16 AF20 AF20
A1 PCSD3 DSPI D peripheral chip select O
A2 —— —
GGPIO87 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 101
88 CNRXC_PCSD4_
GPIO88 PCNRXC FlexCAN C receive I MH VDDEH4 —/Up —/Up W17 AE20 AE20
A1 PCSD4 DSPI D peripheral chip select O
A2 —— —
GGPIO88 GPIO I/O
246 CNTXD_
GPIO246 PCNTXD FlexCAN D transmit O MH VDDEH4 —/Up —/Up AB21 AD20 AD20
A1 —— —
A2 —— —
GGPIO246 GPIO I/O
247 CNRXD_
GPIO247 PCNRXD FlexCAN D receive I MH VDDEH4 —/Up —/Up Y19 AC20 AC20
A1 —— —
A2 —— —
GGPIO247 GPIO I/O
eSCI
89 TXDA_
GPIO89 PTXDA eSCI A transmit O MH VDDEH1 —/Up —/Up — M2 K2
A1 —— —
A2 —— —
GGPIO89 GPIO I/O
90 RXDA _
GPIO90 PRXDA eSCI A receive I MH VDDEH1 —/Up —/Up — M3 K3
A1 —— —
A2 —— —
GGPIO90 GPIO I
91 TXDB_PCSD1_
GPIO91 PTXDB eSCI B transmit O MH VDDEH1 —/Up —/Up — P1 K1
A1 PCSD1 DSPI D peripheral chip select O
A2 —— —
GGPIO91 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
102 Freescale Semiconductor
92 RXDB_PCSD5_
GPIO92 PRXDB eSCI B receive I MH VDDEH1 —/Up —/Up — N1 L5
A1 PCSD5 DSPI D peripheral chip select O
A2 —— —
GGPIO92 GPIO I/O
244 TXDC_ETRIG0_
GPIO244 PTXDC eSCI C transmit O MH VDDEH4 —/Up —/Up — AF23 AF23
A1 ETRIG0 eQADC trigger input I
A2 —— —
GGPIO244 GPIO I/O
245 RXDC_
GPIO245 PRXDC eSCI C receive I MH VDDEH5 —/Up —/Up — AD22 AD22
A1 —— —
A2 —— —
GGPIO245 GPIO I/O
DSPI
93 SCKA_PCSC1_
GPIO93 PSCKA DSPI A clock I/O MH VDDEH3 —/Up —/Up Y7 AD8 AB8
A1 PCSC1 DSPI C peripheral chip select O
A2 —— —
GGPIO93 GPIO I/O
94 SINA_PCSC2_
GPIO94 PSINA DSPI A data input I MH VDDEH3 —/Up —/Up AA7 AF7 AE7
A1 PCSC2 DSPI C peripheral chip select O
A2 —— —
GGPIO94 GPIO I/O
95 SOUTA_PCSC5_
GPIO95 PSOUTA DSPI A data output O MH VDDEH3 —/Up —/Up AB7 AD7 AC7
A1 PCSC5 DSPI C peripheral chip select O
A2 —— —
GGPIO95 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 103
96 PCSA0_PCSD2_
GPIO96 PPCSA0 DSPI A peripheral chip select I/O MH VDDEH3 —/Up —/Up AB6 AE6 AD6
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO96 GPIO I/O
97 PCSA1_
GPIO97 PPCSA1 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AC6 AC6
A1 —— —
A2 —— —
GGPIO97 GPIO I/O
98 PCSA2_
GPIO98 PPCSA2 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AC7 AF6
A1 —— —
A2 —— —
GGPIO98 GPIO I/O
99 PCSA3_
GPIO99 PPCSA3 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AE7 AD7
A1 —— —
A2 —— —
GGPIO99 GPIO I/O
100 PCSA4_
GPIO100 PPCSA4 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up — AE5 AE5
A1 —— —
A2 —— —
GGPIO100 GPIO I/O
101 PCSA5_ETRIG1_
GPIO101 PPCSA5 DSPI A peripheral chip select O MH VDDEH3 —/Up —/Up AA6 AD6 AA8
A1 ETRIG1 eQADC trigger input I
A2 —— —
GGPIO101 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
104 Freescale Semiconductor
102 SCKB_
GPIO102 PSCKB DSPI B clock I/O MH VDDEH3 —/Up —/Up Y8 AE8 AC8
A1 —— —
A2 —— —
GGPIO102 GPIO I/O
103 SINB_
GPIO103 PSINB DSPI B data input I MH VDDEH3 —/Up —/Up AA8 AE9 AB9
A1 —— —
A2 —— —
GGPIO103 GPIO I/O
104 SOUTB_
GPIO104 PSOUTB DSPI B data output O MH VDDEH3 —/Up —/Up AB8 AF9 AA10
A1 —— —
A2 —— —
GGPIO104 GPIO I/O
105 PCSB0_PCSD2_
GPIO105 PPCSB0 DSPI B peripheral chip select I/O MH VDDEH3 —/Up —/Up Y9 AD9 AF8
A1 PCSD2 DSPI D peripheral chip select O
A2 —— —
GGPIO105 GPIO I/O
106 PCSB1_PCSD0_
GPIO106 PPCSB1 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AC9 AE8
A1 PCSD0 DSPI D peripheral chip select I/O
A2 —— —
GGPIO106 GPIO I/O
107 PCSB2_SOUTC_
GPIO107 PPCSB2 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up W7 AF8 AD8
A1 SOUTC DSPI C data output O
A2 —— —
GGPIO107 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 105
108 PCSB3_SINC_
GPIO108 PPCSB3 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AD10 AC9
A1 SINC DSPI C data input I
A2 —— —
GGPIO108 GPIO I/O
109 PCSB4_SCKC_
GPIO109 PPCSB4 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AC8 AF7
A1 SCKC DSPI C clock I/O
A2 —— —
GGPIO109 GPIO I/O
110 PCSB5_PCSC0_
GPIO110 PPCSB5 DSPI B peripheral chip select O MH VDDEH3 —/Up —/Up — AF6 AE6
A1 PCSC0 DSPI C peripheral chip select I/O
A2 —— —
GGPIO110 GPIO I/O
235 SCKC_SCK_C_LVDSP_
GPIO235 PSCKC DSPI C clock I/O MH+
LVDS VDDEH4 —/Up —/Up AA19 AD21 AD21
A1 SCK_C_LVDSP LVDS+ downstream signal positive
output clock O
A2 —— —
GGPIO235 GPIO I/O
236 SINC_SCK_C_LVDSM_
GPIO236 PSINC DSPI C data input I MH+
LVDS VDDEH4 —/Up —/Up AA20 AE22 AE22
A1 SCK_C_LVDSM LVDS– downstream signal negative
output clock O
A2 —— —
GGPIO236 GPIO I/O
237 SOUTC_SOUT_C_LVDSP_
GPIO237 PSOUTC DSPI C data output O MH+
LVDS VDDEH4 —/Up —/Up AB18 AF21 AF21
A1 SOUT_C_LVDSP LVDS+ downstream signal positive
output data O
A2 —— —
GGPIO237 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
106 Freescale Semiconductor
238 PCSC0_SOUT_C_LVDSM_
GPIO238 PPCSC0 DSPI C peripheral chip select I/O MH+
LVDS VDDEH4 —/Up —/Up AB19 AE21 AE21
A1 SOUT_C_LVDSM LVDS– downstream signal negative
output data O
A2 —— —
GGPIO238 GPIO I/O
239 PCSC1_
GPIO239 PPCSC1 DSPI C peripheral chip select O MH VDDEH4 —/Up —/Up — AC22 AC22
A1 —— —
A2 —— —
GGPIO239 GPIO I/O
240 PCSC2_GPIO240 PPCSC2 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AE23 AE23
A1 —— —
A2 —— —
GGPIO240 GPIO I/O
241 PCSC3_GPIO241 PPCSC3 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AD23 AD23
A1 —— —
A2 —— —
GGPIO241 GPIO I/O
242 PCSC4_GPIO242 PPCSC4 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AF24 AF24
A1 —— —
A2 —— —
GGPIO242 GPIO I/O
243 PCSC5_GPIO243 PPCSC5 DSPI C peripheral chip select O MH VDDEH5 —/Up —/Up — AE24 AE24
A1 —— —
A2 —— —
GGPIO243 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 107
EBI
256 D_CS0_
GPIO256 PD_CS0 EBI chip select 0 O F VDDE9 —/Up —/Up — — AD9
A1 —— —
A2 —— —
GGPIO256 GPIO I/O
257 D_CS2_D_ADD_DAT31_
GPIO257 PD_CS2 EBI chip select 2 O F VDDE8 —/Up —/Up — — U1
A1 D_ADD_DAT31 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO257 GPIO I/O
258 D_CS3_D_TEA_
GPIO258 PD_CS3 EBI chip select 3 O F VDDE8 —/Up —/Up — — T6
A1 D_TEA EBI transfer error acknowledge I
A2 —— —
GGPIO258 GPIO I/O
259 D_ADD12_
GPIO259 PD_ADD12 EBI address bus I/O F VDDE8 —/Up —/Up — — R1
A1 —— —
A2 —— —
GGPIO259 GPIO I/O
260 D_ADD13_
GPIO260 PD_ADD13 EBI address bus I/O F VDDE8 —/Up —/Up — — R2
A1 —— —
A2 —— —
GGPIO260 GPIO I/O
261 D_ADD14_
GPIO261 PD_ADD14 EBI address bus I/O F VDDE8 —/Up —/Up — — R3
A1 —— —
A2 —— —
GGPIO261 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
108 Freescale Semiconductor
262 D_ADD15_
GPIO262 PD_ADD15 EBI address bus I/O F VDDE8 —/Up —/Up — — R4
A1 —— —
A2 —— —
GGPIO262 GPIO I/O
263 D_ADD16_D_ADD_DAT16_
GPIO263 PD_ADD16 EBI address bus I/O F VDDE8 —/Up —/Up — — R5
A1 D_ADD_DAT16 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO263 GPIO I/O
264 D_ADD17_D_ADD_DAT17_
GPIO264 PD_ADD17 EBI address bus I/O F VDDE8 —/Up —/Up — — T5
A1 D_ADD_DAT17 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO264 GPIO I/O
265 D_ADD18_D_ADD_DAT18_
GPIO265 PD_ADD18 EBI address bus I/O F VDDE8 —/Up —/Up — — T2
A1 D_ADD_DAT18 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO265 GPIO I/O
266 D_ADD19_D_ADD_DAT19_
GPIO266 PD_ADD19 EBI address bus I/O F VDDE8 —/Up —/Up — — T3
A1 D_ADD_DAT19 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO266 GPIO I/O
267 D_ADD20_D_ADD_DAT20_
GPIO267 PD_ADD20 EBI address bus I/O F VDDE8 —/Up —/Up — — T4
A1 D_ADD_DAT20 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO267 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 109
268 D_ADD21_D_ADD_DAT21_
GPIO268 PD_ADD21 EBI address bus I/O F VDDE9 —/Up —/Up — — AB11
A1 D_ADD_DAT21 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO268 GPIO I/O
269 D_ADD22_D_ADD_DAT22_
GPIO269 PD_ADD22 EBI address bus I/O F VDDE9 —/Up —/Up — — AD10
A1 D_ADD_DAT22 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO269 GPIO I/O
270 D_ADD23_D_ADD_DAT23_
GPIO270 PD_ADD23 EBI address bus I/O F VDDE9 —/Up —/Up — — AE10
A1 D_ADD_DAT23 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO270 GPIO I/O
271 D_ADD24_D_ADD_DAT24_
GPIO271 PD_ADD24 EBI address bus I/O F VDDE9 —/Up —/Up — — AF10
A1 D_ADD_DAT24 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO271 GPIO I/O
272 D_ADD25_D_ADD_DAT25_
GPIO272 PD_ADD25 EBI address bus I/O F VDDE9 —/Up —/Up — — AD11
A1 D_ADD_DAT25 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO272 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
110 Freescale Semiconductor
273 D_ADD26_D_ADD_DAT26_
GPIO273 PD_ADD26 EBI address bus I/O F VDDE9 —/Up —/Up — — AE11
A1 D_ADD_DAT26 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO273 GPIO I/O
274 D_ADD27_D_ADD_DAT27_
GPIO274 PD_ADD27 EBI address bus I/O F VDDE9 —/Up —/Up — — AF11
A1 D_ADD_DAT27 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO274 GPIO I/O
275 D_ADD28_D_ADD_DAT28_
GPIO275 PD_ADD28 EBI address bus I/O F VDDE9 —/Up —/Up — — AD12
A1 D_ADD_DAT28 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO275 GPIO I/O
276 D_ADD29_D_ADD_DAT29_
GPIO276 PD_ADD29 EBI address bus I/O F VDDE9 —/Up —/Up — — AB12
A1 D_ADD_DAT29 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO276 GPIO I/O
277 D_ADD30_D_ADD_DAT30_
GPIO277 PD_ADD30 EBI address bus I/O F VDDE9 —/Up —/Up — — AE12
A1 D_ADD_DAT30 EBI data only in non-mux mode.
Address and data in mux mode. I/O
A2 —— —
GGPIO277 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 111
278 D_ADD_DAT0_
GPIO278 PD_ADD_DAT0 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — P25
A1 —— —
A2 —— —
GGPIO278 GPIO I/O
279 D_ADD_DAT1_
GPIO279 PD_ADD_DAT1 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — P26
A1 —— —
A2 —— —
GGPIO279 GPIO I/O
280 D_ADD_DAT2_
GPIO280 PD_ADD_DAT2 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — N24
A1 —— —
A2 —— —
GGPIO280 GPIO I/O
281 D_ADD_DAT3_
GPIO281 PD_ADD_DAT3 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — N25
A1 —— —
A2 —— —
GGPIO281 GPIO I/O
282 D_ADD_DAT4_
GPIO282 PD_ADD_DAT4 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — N26
A1 —— —
A2 —— —
GGPIO282 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
112 Freescale Semiconductor
283 D_ADD_DAT5_
GPIO283 PD_ADD_DAT5 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — M25
A1 —— —
A2 —— —
GGPIO283 GPIO I/O
284 D_ADD_DAT6_
GPIO284 PD_ADD_DAT6 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — N22
A1 —— —
A2 —— —
GGPIO284 GPIO I/O
285 D_ADD_DAT7_
GPIO285 PD_ADD_DAT7 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — M24
A1 —— —
A2 —— —
GGPIO285 GPIO I/O
286 D_ADD_DAT8_
GPIO286 PD_ADD_DAT8 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — M23
A1 —— —
A2 —— —
GGPIO286 GPIO I/O
287 D_ADD_DAT9_
GPIO287 PD_ADD_DAT9 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — M22
A1 —— —
A2 —— —
GGPIO287 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 113
288 D_ADD_DAT10_
GPIO288 PD_ADD_DAT10 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — L26
A1 —— —
A2 —— —
GGPIO288 GPIO I/O
289 D_ADD_DAT11_
GPIO289 PD_ADD_DAT11 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — L25
A1 —— —
A2 —— —
GGPIO289 GPIO I/O
290 D_ADD_DAT12_
GPIO290 PD_ADD_DAT12 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — L24
A1 —— —
A2 —— —
GGPIO290 GPIO I/O
291 D_ADD_DAT13
_GPIO291 PD_ADD_DAT13 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — L23
A1 —— —
A2 —— —
GGPIO291 GPIO I/O
292 D_ADD_DAT14_GPIO292 PD_ADD_DAT14 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — L22
A1 —— —
A2 —— —
GGPIO292 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
114 Freescale Semiconductor
293 D_ADD_DAT15_GPIO293 PD_ADD_DAT15 EBI data only in non-mux mode.
Address and data in mux mode. I/O F VDDE10 —/Up —/Up — — K26
A1 —— —
A2 —— —
GGPIO293 GPIO I/O
294 D_RD_WR_GPIO294 PD_RD_WR EBI read/write O F VDDE10 —/Up —/Up — — R26
A1 —— —
A2 —— —
GGPIO294 GPIO I/O
295 D_WE0_GPIO295 PD_WE0 EBI write enable O F VDDE8 —/Up —/Up — — N1
A1 —— —
A2 —— —
GGPIO295 GPIO I/O
296 D_WE1_GPIO296 PD_WE1 EBI write enable O F VDDE8 —/Up —/Up — — P5
A1 —— —
A2 —— —
GGPIO296 GPIO I/O
297 D_OE_GPIO297 PD_OE EBI output enable O F VDDE10 —/Up —/Up — — P23
A1 —— —
A2 —— —
GGPIO297 GPIO I/O
298 D_TS_GPIO298 PD_TS EBI transfer start O F VDDE9 —/Up —/Up — — AE9
A1 —— —
A2 —— —
GGPIO298 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 115
299 D_ALE_GPIO299 PD_ALE EBI Address Latch Enable O F VDDE10 —/Up —/Up — — P24
A1 —— —
A2 —— —
GGPIO299 GPIO I/O
300 D_TA_GPIO300 PD_TA EBI transfer acknowledge I/O F VDDE9 —/Up —/Up — — AF9
A1 —— —
A2 —— —
GGPIO300 GPIO I/O
301 D_CS1_GPIO301 PD_CS1 EBI chip select O F VDDE9 —/Up —/Up — — AB10
A1 —— —
A2 —— —
GGPIO301 GPIO I/O
302 D_BDIP_GPIO302 PD_BDIP EBI burst data in progress O F VDDE8 —/Up —/Up — — M2
A1 —— —
A2 —— —
GGPIO302 GPIO I/O
303 D_WE2_GPIO303 PD_WE2 EBI write enable O F VDDE8 —/Up —/Up — — N2
A1 —— —
A2 —— —
GGPIO303 GPIO I/O
304 D_WE3_GPIO304 PD_WE3 EBI write enable O F VDDE8 —/Up —/Up — — N3
A1 —— —
A2 —— —
GGPIO304 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
116 Freescale Semiconductor
305 D_ADD9_GPIO305 PD_ADD9 EBI address bus I/O F VDDE8 —/Up —/Up — — P1
A1 —— —
A2 —— —
GGPIO305 GPIO I/O
306 D_ADD10_GPIO306 PD_ADD10 EBI address bus I/O F VDDE8 —/Up —/Up — — P2
A1 —— —
A2 —— —
GGPIO306 GPIO I/O
307 D_ADD11_GPIO307 PD_ADD11 EBI address bus I/O F VDDE8 —/Up —/Up — — P3
A1 —— —
A2 —— —
GGPIO307 GPIO I/O
Reset and Clocks
— RESET PRESET External reset input I MH VDDEH1 RESET/Up RESET/Up M2 R2 N5
230 RSTOUT PRSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/
High A3 A3 A3
211 BOOTCFG0_IRQ2_
GPIO211 PBOOTCFG0 Boot configuration I MH VDDEH1 BOOTCFG/
Down BOOTCFG/
Down ——L4
A1 IRQ2 I
A2 —— —
GGPIO211 GPIO I/O
212 BOOTCFG1_IRQ3_
GPIO212 PBOOTCFG1 Boot configuration I MH VDDEH1 BOOTCFG/
Down Input/Down L1 N2 L3
A1 IRQ3 External interrupt request I
A2 —— —
GGPIO212 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 117
213 WKPCFG_NMI_
GPIO213 PWKPCFG Weak pull configuration input I MH VDDEH1 WKPCFG/Up Input/Up — N3 M5
A1 NMI Critical interrupt to core11 I
A2 —— —
GGPIO213 GPIO I
208 PLLCFG0_IRQ4_
GPIO208 PPLLCFG0 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up M3 R3 M3
A1 IRQ4 External interrupt request I
A2 —— —
GGPIO208 GPIO I/O
209 PLLCFG1_IRQ5_
GPIO209 PPLLCFG1 FMPLL mode configuration input I MH VDDEH1 PLLCFG/Up Input/Up
(for Rev2 of the
device: —/Up)
L2 P2 L1
A1 IRQ5 External interrupt request I
A2 SOUTD DSPI D data output O
GGPIO209 GPIO I/O
— PLLCFG2 PPLLCFG2 FMPLL mode configuration input I MH VDDEH1
PLLCFG/
Down PLLCFG/
Down
L3 P3 L2
—XTAL PXTAL Crystal oscillator output O
AE
VDD33 XTAL XTAL W22 AC26 AC26
—EXTAL PEXTAL Crystal oscillator input I
AE
VDD33 EXTAL EXTAL V22 AB26 AB26
229 D_CLKOUT PD_CLKOUT EBI system clock output O
F
VDDE9 CLKOUT/
Enabled CLKOUT/
Enabled ——AF12
214 ENGCLK PENGCLK EBI engineering clock output
Note: EXTCLK (External clock input)
selected through SIU register)
OFV
DDE2 ENGCLK/
Enabled ENGCLK/
Enabled AA1 AD1 AD1
JTAG and Nexus
(see footnote12 about reset s )
—EVTI –13 EVTI Nexus event in I F VDDE2 —/Up EVTI/Up N4 T4 V1
227 EVTO
(the BAM uses this pin to
select if auto baud rate is on or
off)
–13 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI P1 U1 V2
219 MCKO –13 MCKO Nexus message clo ck out O F VDDE2 O/Low Disabled14 N2 T2 U4
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
118 Freescale Semiconductor
220 MDO0_GPIO220
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO015 Nexus message data out O F VDDE2 O/Low MDO0/Low P3 U3 V3
A1 —— —
A2 —— —
GGPIO220 GPIO I/O
221 MDO1_GPIO221
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO115 Nexus message data out O F VDDE2 O/Low —/Down P4 U4 W6
A1 —— —
A2 —— —
GGPIO221 GPIO I/O
222 MDO2_GPIO222
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO215 Nexus message data out O F VDDE2 O/Low —/Down R1 V1 V4
A1 —— —
A2 —— —
GGPIO222 GPIO I/O
223 MDO3_GPIO223
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO315 Nexus message data out O F VDDE2 O/Low —/Down R2 V2 V5
A1 —— —
A2 —— —
GGPIO223 GPIO I/O
75 MDO4_GPIO75
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO415 Nexus message data out O F VDDE2 O/Low —/Down R3 V3 W1
A1 —— —
A2 —— —
GGPIO75 GPIO I/O
76 MDO5_GPIO76
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO515 Nexus message data out O F VDDE2 O/Low —/Down R4 V4 W2
A1 —— —
A2 —— —
GGPIO76 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 119
77 MDO6_GPIO77
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO615 Nexus message data out O F VDDE2 O/Low —/Down T1 W1 W3
A1 —— —
A2 —— —
GGPIO77 GPIO I/O
78 MDO7_GPIO78
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO715 Nexus message data out O F VDDE2 O/Low —/Down T2 W2 Y1
A1 —— —
A2 —— —
GGPIO78 GPIO I/O
79 MDO8_GPIO79
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO815 Nexus message data out O F VDDE2 O/Low —/Down T3 W3 W5
A1 —— —
A2 —— —
GGPIO79 GPIO I/O
80 MDO9_GPIO80
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO915 Nexus message data out O F VDDE2 O/Low —/Down U1 Y1 Y2
A1 —— —
A2 —— —
GGPIO80 GPIO I/O
81 MDO10_GPIO81
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO1015 Nexus message data out O F VDDE2 O/Low —/Down U2 Y2 Y3
A1 —— —
A2 —— —
GGPIO81 GPIO I/O
82 MDO11_GPIO82
(GPIO function on this pin is
only available on Rev.2 of the
device)
–13 MDO1115 Nexus message data out O F VDDE2 O/Low —/Down U3 Y3 Y4
A1 —— —
A2 —— —
GGPIO82 GPIO I/O
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
120 Freescale Semiconductor
231 MDO12_GPIO231 –13 MDO1215 Nexus message data out O F VDDE2 O/Low —/Down V1 AA1 Y5
A1 —— —
A2 —— —
GGPIO231 GPIO I/O
232 MDO13_GPIO232 –13 MDO1315 Nexus message data out O F VDDE2 O/Low —/Down W2 AA2 AA1
A1 —— —
A2 —— —
GGPIO232 GPIO I/O
233 MDO14_GPIO233 –13 MDO1415 Nexus message data out O F VDDE2 O/Low —/Down V3 AA3 AA2
A1 —— —
A2 —— —
GGPIO233 GPIO I/O
234 MDO15_GPIO234 –13 MDO1515 Nexus message data out O F VDDE2 O/Low —/Down U4 Y4 AA3
A1 —— —
A2 —— —
GGPIO234 GPIO I/O
224 MSEO0 –13 MSEO015 Nexus message start/end out O F VDDE2 O/Low MSEO/HI P2 U2 U6
225 MSEO1 –13 MSEO115 Nexus message start/end out O F VDDE2 O/Low MSEO/HI N3T3U5
226 RDY –13 RDY Nexus ready output O F VDDE2 O/Low RDY/HI M4 R4 U3
—TCK –13 TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down Y1 AB2 AB2
—TDI –13 TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up Y2 AC2 AC2
228 TDO –13 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up W1 AB1 AB1
—TMS –13 TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up W3 AB3 AB3
—JCOMP –13 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down M1 R1 U2
— TEST —TEST Test mode select (not for customer
use) IFV
DDEH1 TEST/Down TEST/Down B4 B4 B4
— VDDSYN —VDDSYN Clock synthesizer power input I VDDE VDDSYN VDDSYN VDDSYN Y22 AD26 AD26
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 121
— VSSSYN —VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN U22 AA26 AA26
—VSTBY —VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY K4 M4 M4
— REGSEL —REGSEL Selects regulator mode (Linear/Switch
mode) IAEV
DDREG REGSEL REGSEL V20 W23 W23
—REGCTL —REGCTL Regulator controller output to
base/gate of power transistor O
AE
VDDREG REGCTL REGCTL T22 Y26 Y26
—VSSFL —VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL V21 AB25 AB25
— VDDREG —VDDREG Source voltage for on-chip regulators
and Low voltage detect circuits I
VDDINT
VDDREG VDDREG VDDREG U21 AA25 AA25
1The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality . For pins that do not have GPIO
functionality, this number is the PCR number.
2The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and
is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.
3P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.
4Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are
designated in the PA field of the SIU_PCRn registers except where explicitly noted.
5MH = High voltage, medium speed
F = Fast speed
FS = Fast speed with slew
AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)
VHV = Very high voltage
6VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%)
power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.
7The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column
is: O – output, I – input, Up – weak pull up enabled, Down – we ak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select
(during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side
of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabl ed.
8The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are
off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
9This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.
10 During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw . The pull resistors are disabled when the system
clock propagates through the device.
11 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1
Signal Name2
P/A/G3
Function4Function Summary
Direction
Pad Type5
Voltage6
St ate during
RESET7State
af ter RESET8
Package Location
324
416
516
MPC5674F Microcon troller Data Sheet, Rev. 10.1
122 Freescale Semiconductor
12 Nexus reset is different than system reset; MDO 1-1 1 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO
are also dependent on trace (RPM or FPM) being enabled.
13 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values
have no effect on the function of these pins once enabled.
14 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_ PCR register).
15 Do not connect pin directly to a power supply or ground.
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 123
Table 45 lists the pin locations of the power and ground signals on the 324 TEPBGA package.
Table 44. 324-pin Power Supply Locations
VDD
A2 B3 C4 D5 K3 V19 W5 W9 W20 Y4 Y21 AA3 AA22 AB2
VDD33
W21 V4
VDDE2
AB4 M9 N1 N10 N9 P10 P9 T4 W6 V2
VDDEH1 VDDEH4 VDDEH6 VDDEH7
B1 L4 AB20 W8 N20 T21 C22 H19 L22
VSS
A1 A22 AA2 AA21 AB1 AB22 B2 B21 C20 C3 D19 D4 J10 J11 J12 J13 J14 J9
K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L9 M10 M11 M12 M13 M14 N11
N12 N13 N14 P11 P12 P13 P14 W19 W4 Y20 Y3
MPC5674F Microcon troller Data Sheet, Rev. 10.1
124 Freescale Semiconductor
Table 45 lists the pin locations of the power and ground signals on the 416 TEPBGA package.
Table 45. 416-pin Power Supply Locations
VDD
A2 B3 C4 D5 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDD33
M1 AA4 AA23
VDDE2
N10 P10 P11 R10 R11 T1 T10 T11 T12 U10 U11 U12 W4 AC1 AC5 AF2
VDDEH1 VDDEH3 VDDEH4 VDDEH5
B1 P4 AC10 AF5 AC11 AF22 AC21 AF25
VDDEH6 VDDEH7
N23 AC25 D24 E23 M26
VSS
A1 A26 B2 B25 C3 C24 D4 D23 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11
L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13 N14
N15 N16 N17 P12 P13 P14 P15 P16 P17 R12 R13 R14 R15 R16 R17 T13 T14 T15
T16 T17 U13 U14 U15 U16 U17 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26
MPC5674F Microcon troller Data Sheet, Rev. 10.1
Freescale Semiconductor 125
Table 46 lists the pin locations of the power and ground signals on the 516 TEPBGA package.
Table 46. 516-pin Power Supply Locations
VDD
A2 B3 C4 D5 E6 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDD33 VDDE10
M1 P6 L21 AA4 AA11 AA14 AA23 F16 F17 F19 F21 N21 P21 AA22
VDDE2
N10 P10 P11 R10 R11 T1 T10 T11 T12 U10 U11 U12 W4 AC1 AC5 AF2
VDDE8 VDDE9
F6 F8 F10 F11 N6 AA5 AA13 AB6 AB7 AB18 AB19 AB20 AB21
VDDEH1 VDDEH3 VDDEH4 VDDEH5
B1 P4 AC10 AF5 AC11 AF22 AC21 AF25
VDDEH6 VDDEH7
N23 AC25 D24 E23 M26
VSS
A25 B2 B25 B26 C3 C24 D4 D23 E5 E7 E8 E9 E10 E11 E12 E13 E14 E15
E16 E17 E18 E19 E21 E22 F5 F13 F14 K10 K11 K12 K13 K14 K15 K16 K17 L10
L11 L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13
N14 N15 N16 N17 P12 P13 P14 P15 P16 P17 R12 R13 R14 R15 R16 R17 T13 T14
T15 T16 T17 U13 U14 U15 U16 U17 AA6 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Revision History
Freescale Semiconductor126
Appendix B Revision History
Table 47 describes the changes made to this document between revi sions.
Table 47. Revision History
Revision
(Date) Description of ch anges
2
(Sept 2008) Initial release, NDA Required.
3
(Nov 2009) Changes betwee n Rev.2 and Rev. 3:
Added 516-pin package figures.
Signals table: Updates throughout entire table.
Updated Section 4.6, “Power Up/Down Sequencing”
Updated featur es li st.
Updated flash PFCPR1 settings table.
Fixed JTAG Test Clock Input Timing figure so the spec #’s in table matched figure.
Updated Orderable Part numbers table.
Moved signals table to be an appendix.
Added 324-pin package thermals.
Updated part numbers in orderable parts table (missing F: MPC5674F).
FMPLL Electrical Spec table:
Spec #1 changed min values of 4 to 8
Removed last sentence of footnote 2
Added note "Upper tolerance of less than 1% is allowed on 40MHz crystal."
Oscillator Electrical Spec table:
Moved predivider op. frequency spec from this table to the FMPLL Electrical Spec table
Removed footnote #3 (since VDDE9 is an external supply and has no relation to the oscillator, PMC, or PLL).
Added maximum solder temperature to Absolute Max Ratings table.
PMC Operating Conditions table:
Removed JTemp row.
Changed VDDR to VDDREG (naming consistency)
Changed VDD12 to VDD (naming consistency)
PMC Electrical Spec table:
Added VDDREG to this parameter “Trimmed bandgap reference voltage / voltage dependence (VDDREG)”
Changed VDDSTEP to LVDSTEP12 (naming consistency)
Added two conditons to the opening statements of Section 4.6, “Power Up/Down Sequencing.”
DC Electrical Specifications table:
spec #9 (Fast I/O Input High Voltage)
spec #10 (Fast I/O Input Low Voltage)
spec #24 (Operating Current 1.2 V Supplies; IDD)
spec #25 (Operating Current 3.3 V Supplies; IDDSYN)
spec #32 (Analog Input Current, Channel Off; IINACT_A)
footnote #12 ("IOH_S = {11.6} mA...")
Revision History
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 127
3
(cont.) eQADC Conversion Specifications table:
Spec #7, 8: both +/-3, no dependency on frequency
Spec #15, 16: added "(with calibration)" to both
Flash Program and Erase Specifications table:
Added footnote 4 to spec #2.
Updated all initial max value times.
Updated entire AC Specifications: Clocki ng section.
Pad AC Specifications table: updated Medium pad specs
Derated Pad AC Specifications table: updated all specs
Updated entire Section 4.6, “Power Up/Down Sequen cing.”
Updated Absolute Maximum Ratings (AMR) specs 1–11, 15, 16.
Changed name of IDDC to IREGCTL since it is the REGCTL max drive current.
Added two EMC Radiated Emissions Operating Behaviors tables and removed “EMI Testing Specifications”
table.
PMC Electrical Sp ecifications table:
1b: Changed 1% to 2%
1c: Changed 150 to 300 ppm/C
2b: added footnote
2c: Changed from "Trimming step VDD" to "Trimming step VDD12OUT"
DC Electrical Specifications table:
6: Updated min value and added keep-out range
Standby RAM Regulator Electrical Specifications table:
Added brownout spec
PMC electrical spec table, added new specs: SMPS regulator output resistance, SPMS regulator clock
frequency, SMPS regulator overshoot at start-up, SMPS max output current, and voltage variation on current
step.
Added LVD VDDA specs to the PMC electrical spec table.
Removed specs for VDDF and VFLASH since those supplies are shorted with others in the package.
4
(Aug 2010) Changes between Rev.3 and Rev.4:
Table “Derated Pad AC Specifications”, Spec #1: Changed 20ns to 200ns.
Added “324-ball TEPBGA Pin Assignments” section and mechanical drawings.
Appendix A (Signals):
Added “(the BAM uses this pin to select if auto baud rate is on or off)” to the EVTO pin description.
Added 324 pinout column.
Changed footnote from “NMI does not have a PCR P A configuration; it is enabled when NMI is enabled through
the SIU DIRER register.“ to “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled
through the SIU_IREER and SIU_IFEER registers.”
Updated eQADC signals to show that eQADC A and B each have dedicated channels (ANx0-23) and shared
channels (AN24-39).
Table 47. Revision Histor y (continued)
Revision
(Date) Description of ch anges
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Revision History
Freescale Semiconductor128
4
(cont) “Temperature Sensor Electrical S pecifications” table: Changed spec #2 to have one temperature range (-40 - 150
C) and changed spec value from ±1.0 to ±10.0 C.
“eQADC Conversion S pecifications (Operating)” table: Changed spec #13 (non-disruptive injection current)
values from ±1 to ±3.
"IPCLKDIV Settings" table, removed footnote "eMIOS and DMA are not considered perip herals here."
5
(Feb-2011) Note 4 in Maximum Ratings updated from 2.0 V to 1.65 V.
Changed I/O Supply Voltage spec in DC Electrical specs, Spec 2, from 1.62 V min to 3.0 V min.
Changed the APC=RWSC value in line 1 of PFCPR1 Settings vs. Frequency of Oper ation table from 0b011 to
0b100
Changed note 1 for Pad AC Specifications table from Vdde = 1.62 V to 1.98 V to read Vdde = 3.0 V to 3.6 V
Changed note 6 for Signal Properties and Muxing Summary table by removing the voltage range 1.8 V - 3.3 V
to have 3.3 V instead of the range.
S pec 2 in Table 9 “ESD Ratings“ the spec for “ESD for Charged Device Model (CDM)” changed to 250 V (other)
from 500 V (other)
Removed voltage ranges 1.62-1.98 V and 2.25-2.75 V from spec 28 in Table 14
6
(Feb-2011) Same content as for Rev. 5
7
(Mar-2011) Adde d entry for Rev. 6 and Rev. 7 to this table to fix a revision -numbering issue.
8
(Jun-2011) Added the following footnotes to the “Signal Properties and Muxing Summary” table:
• Footnote 10, for the ANA[0:7] signals, “During and just after POR negates, internal pull resistors can be
enabled, resulting in as much as 4 mA of current draw . The pull resistors are disabled when the system clock
propagates through the device.”
• Footnote 15, for MDO[0:15] and MSEO[0:1] signals, “Do not connect pin directly to a power supply or ground.”
Changed min and max values of ID 1 “Nominal bandgap reference voltage“ in Table 11 (PMC Electrical
Specifications) to 0.608 V min and 0.632 V max.
Changed min and max values of Spec 2 “ADC Bandgap” in Table 23 (ADC Band Gap Reference/LVI Electrical
Specifications) to 1.171 V min and 1.269 V max.
Changed Spec 3 of Table 26 (Flash EEPROM Module Life) from 'Minimum Data Retention at 25 °C ambient
temperature' to 'Minimum Data Retention at 85 °C ambient temperatu re'
Added Spec 41, 42, 43 and 44 to the “DC Electrical Specifications” t able
Added Note 25 to the “DC Electrical S pecifications” table for Spec 41, 42 and 43
Added Note 26 to the “DC Electrical Specifications” for Spec 44
Added Spec 17 to the “eQADC Conversion Specifications (Operating)” table.
Added Spec 18 to the “eQADC Conversion Specifications (Operating)” table.
Added Note 15 to the “eQADC Conversion Specifications (Operating)” table for Spec 17 and 18.
Table 47. Revision Histor y (continued)
Revision
(Date) Description of ch anges
Revision History
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Freescale Semiconductor 129
8
(Jun-2011) Removed spec 3 from Table 27 “PFCPR1 Settings vs Frequency of Operation”
Updated spec 2a (Untrimmed VRC 1.2V) in Table 11 “P MC Electrical Specifications“ to a max value of
VDD12OUT + 17%.
Updated item 26 (Operating Current VDDA Suppl y) in table 14 “Electrical Specifications” from 30 mA to 40 mA.
Updated Note 11 for Table 14 (Electrical Specifications) to read IOH_F = {16,32,47,77} mA and
IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V.
Updated ID 9 in Table 11 (PMC Electrical Specifications) to
VREG = 4.5 V, max DC output current with a max of 80 mA
VREG = 4.25 V, max DC output current, crank co ndition with a max of 40 mA
Updated Table 17 (DSPI LVDS Pad Specification) with the follo wing:
• Spec 1 typical value updated from 40 MHz to 50 MHz
• Spec 2 added SRC conditions and associated values:
– SRC=0b00 or SRC=0b11 Min 150 mV Max 400 mV
– SRC=0b01 Min 90 mV Max 320 mV
– SRC=0b10 Min 160 mV Max 480 mV
• Spec 3
- Min value from 1.075 V to 1.06 V
- Max value from 1.325 V to 1.39 V
• Added Spec 5, 6 and 7
Updated table 17 "DSPI LVDS pad specification" to include Temperature with a min value of -40 C and max of
150 C
Updated Spec 5 of Table 18, "FMPLL Electrical Specifications" to < 400 us as the Max vaule.
Added the sentence "Violating the VCO min/max range may prevent the system from exiting reset." to the end
of Footnote 16 of Table 18, "FMPLL Electrical Specifications"
Updated Spec 1 of Table 18, "FMPLL Electrical Specific ations", Crystal Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Updated S pec 1 of Table 18, "FMPLL Electrical S pecifications", External Reference (PLLCFG2 = 0b1) minimum
value from 40 MHz to 16 MHz.
Removed Note 9, 'Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1', from Table 18,
"FMPLL Electrical S pecifications".
Updated ID 16 in Table 1 1, “PMC Electrical S pecifications”, SMPS regulator clock frequency (after reset) 2.4MHz
Max
Updated Table 16 “Flash EEPROM Module Life”, spec 3, ‘Blocks with 10,001–100,000 P/E cycles’ to 5 Years.
Added Typ column to Table 25, “Flash Program and Erase Specifications”
Updated Table 3, “Absolute Maximum Ratings” with the following:
- Spec 1, ‘1.2 V Core Supply Voltage’, to a Max of 2.0 V
- Spec 3, ‘Clock Synthesizer Voltage’, to a Max of 5.3 V
- Spec 4, ‘I/O Supply Voltage’ to a Max of 5.3 V
- Spec 5, ‘Analog Supply Voltage’ to a Max of 5.3 V
- Note 2 to read, “2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining.“
- Note 3, “... 5.0 V + 10% ...” to “... 5.25 V + 10 % ...”
- Note 5, “... 3.3 V + 10% ...” to “... 3.60 V + 10 % ...”
Updated Spec 2 (ESD for Charged Device Model (CDM)) of Table 9, “ESD Ratings”, to 500 V
Updated Table 27, “PFCPR1 Settings vs. Frequency of Operation“, Spec 3, APC = RWSC column to 0b100.
Updated Spec 26, “Operating Current 5.0 V Supplies @ fsys = 264 MHz“ for IDDA to 50 mA, in Table 14, “DC
electrical specifications”.
Table 47. Revision Histor y (continued)
Revision
(Date) Description of ch anges
MPC5674F Microcontr oller Data Sheet, Rev. 10.1
Revision History
Freescale Semiconductor130
9 Updated Table 1.,"Orderable Part Numbers" with actual available parts. Added new part number
SPC5673FF3MVY2 ,Package description 516 PBGA, w/EBI, Pb-free.Speed is 200 MHz nom and
max.—Removed note attached to “Orderable Part Numbers” and “Freescale Part Number”.
Updated footnotes of Table 3.,"Absolute Maximum Ratings" to:
• 2.0 V for 10 hours cumulative time, 1.2V +10% for time remaining.
• 6.4 V for 10 hours cumulative time, 5.0V +10% for time remaining.
• 5.3 V for 10 hours cumulative time, 3.3V +10% for time remaining.
Updated Table 6.,"Thermal Characteristics, 324-pin Package" to show MPC5674F thermal characteristics.
In Table 10.,"PMC Operating conditions", updated the parameter “Supply voltage VDD 1.2V nominal" to “Core
supply voltage".
In Table 11.,"PMC Electrical Specifications", updated the following rows:
• Parameter “Nominal VRC regulated 1.2V output VDD” updated column “Typ” to 1.27 V.
• The minimum and maximum value of “Untrimmed VRC 1.2V output variation before band gap trim (unloaded)”
updated to “-14%” and “+10%”, respectively.
• The minimum and maximum value of “Trimmed VRC 1.2V output variation after band gap trim (REGCTL load
max. 20mA, VDD load max 1A)” updated to “-10%” and “+5%”, re spectively.
In Table 12.,"Power Sequence Pin S t ates for MH and AE pads", updated the row (VDD33 = low , VDDE = high),
parameter “MH+LVDS Pads” to “Outputs disabled”.
In Table 13.,"Power Sequence Pin States for F and FS pads", updated the rows (VDD = low, VDD33 = low,
VDDE = high) and (VDD = high, VDD33 = low, VDDE = high), parameter “F and FS pad” to “Outputs Disabled”.
In Table 14.,"DC Electrical Specifications", updated the spec 'Operating Current 1.2 V Supplies @ fSYS = 264
MHz' with 'VDD @ 1.32 V' Max value to 850 mA from 1.0 A, and deleted corresponding footnote stating that the
previous information was preliminary.
Updated current (mA) values in Table 15.,"VDDE/VDDEH I/O Pad Average DC Current" from Spec 5 to 13:
• Spec 5 Current (mA) from 6.5 to 7.4
• Spec 6 Current (mA) from 9.4 to 10.5
• Spec 7 Current (mA) from 10.8 to 12.3
• Spec 8 Current (mA) from 33.3 to 35.2
• Spec 9 Current (mA) from 12.0 to 12.7
• Spec 10 Current (mA) from 6.2 to 6.7
• Spec 11 Current (mA) from 4.0 to 4.2
• Spec 12 Current (mA) from 2.4 to 2.6
• Spec 13 Current (mA) from8.9 to 9.
In Table 35.,"Nexus Debug Port Timing", updated the footnote of parameter “tCYC” to “See Notes on tcyc in
Table27”. Removed references to “Section I/O Pad VDD33 Current Specifications” .
10 Updated Figure 1.,"MPC5674F Orderable Part Number Description" with changes in “Revision of Silicon” and
“Fab Revision ID”.
Updated Table 1.,"Orderable Part Numb ers" with changes in Part numbers and Package Description.
10.1 In Figure 1.,"MPC5674F Orderable Part Number Description", replaced “Revision of Silicon for TSMC is 0 for
now. In future, it will be revision 1” with “0 = Rev 0 (TSMC14)”.
Table 47. Revision Histor y (continued)
Revision
(Date) Description of ch anges
