591
6289D–ATARM–3-Oct-11
AT91SAM9R64/RL64
3. Write the starting destination address in the DMAC_DADDRx register for channel x.
Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory,
although fetched during an LLI fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel
x.
5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are
set as shown in Row 2 of Table 37-1 on page 575, while the LLI.DMAC_CTRLBx regis-
ter of the last Linked List item must be set as described in Row 1 of Table 37-1. Figure
37-4 on page 574 shows a Linked List example with two list items.
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
the last) are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.DMAC_SADDRx register location of all LLIs in memory point to
the start source buffer address proceeding that LLI fetch.
8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
locations of all LLIs in memory is cleared.
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
DMAC_SPIPx register for channel x.
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
the DMAC_DPIPx register for channel x.
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
ing the interrupt status register.
12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according
to Row 2 as shown in Table 37-1 on page 575
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit. The
transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx
registers are fetched. The LLI.DMAC_DADDRx register location of the LLI although fetched is not
used. The DMAC_DADDRx register in the DMAC remains unchanged.
16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys-
tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues and
fetches the next LLI from the memory location pointed to by current DMAC_DSCRx
register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx,
DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register
is left unchanged. The DMAC transfer continues until the DMAC samples the
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer
transfer match that described in Row 1 of Table 37-1 on page 575. The DMAC then
knows that the previous buffer transferred was the last buffer in the DMAC transfer.