1
Data sheet acquired from Harris Semiconductor
SCHS188C
Features
• Buffered Inputs
• Common Three-State Output-Enable Control
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay = 13ns at VCC = 5V,
CL = 15pF, TA = 25oC (Clock to Output)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed
Octal D-Type Flip-Flops manufactured with silicon gate CMOS
technology. They possess the low power consumption of stan-
dard CMOS integrated circuits, as well as the ability to drive
15 LSTTL loads. Due to the large output drive capability and
the three-state feature, these devices are ideally suited for
interfacing with bus lines in a bus organized system. The two
types are functionally identical and differ only in their pinout
arrangements.
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive
edge triggered flip-flops. Data at the D inputs, meeting the
setup and hold time requirements, are inverted and trans-
ferred to the Q outputs on the positive going transition of the
CLOCK input. When a high logic level is applied to the OUT-
PUT ENABLE input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs and
the state of the storage elements.
The HCT logic family is speed, function, and pin compatible
with the standard LS logic family.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC534F3A -55 to 125 20 Ld CERDIP
CD54HC564F3A -55 to 125 20 Ld CERDIP
CD54HCT534F3A -55 to 125 20 Ld CERDIP
CD54HCT564F3A -55 to 125 20 Ld CERDIP
CD74HC534E -55 to 125 20 Ld PDIP
CD74HC564E -55 to 125 20 Ld PDIP
CD74HC564M -55 to 125 20 Ld SOIC
CD74HC564M96 -55 to 125 20 Ld SOIC
CD74HCT534E -55 to 125 20 Ld PDIP
CD74HCT564E -55 to 125 20 Ld PDIP
CD74HCT564M -55 to 125 20 Ld SOIC
January 1998 - Revised April 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
CD54/74HC534, CD54/74HCT534,
CD54/74HC564, CD54/74HCT564
High-Speed CMOS Logic Octal D-Type Flip-Flop,
Three-State Inverting Positive-Edge Triggered
[ /Title
(CD74
HC534
,
CD74
HCT53
4,
CD74
HC564
,
CD74
HCT56
2
Functional Diagram
Pinouts CD54HC534, CD54HCT534
(CERDIP)
CD74HC534, CD74HCT534
(PDIP)
TOP VIEW
CD54HC564, CD54HCT564
(CERDIP)
CD74HC564, CD74HCT564
(PDIP, SOIC)
TOP VIEW
TRUTH TABLE
INPUTS OUTPUT
OE CP Dn Qn
L↑HL
L↑LH
L L X No Change
HXXZ
H = High Level (Steady State)
L = Low Level (Steady State)
X= Don’t Care
↑= Transition from Low to High Level
Z = High Impedance State
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
CP 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
CP
Q0
D0
CP
OE
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
O7
D7
DQDQDQDQDQDQDQDQ
CP CP CP CP CP CP CP CP
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
Three-StateLeakage
Current VIL or VIH VO=VCC
or GND -6--±0.5 - ±5.0 - ±10 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Three-StateLeakage
Current VIL or VIH VO=VCC
or GND - 5.5 - - ±0.5 - ±5.0 - ±10 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
D0 - D7 0.15
CP 0.30
OE 0.55
NOTE: UnitLoadis ∆ICC limitspecificinDC Electrical Specifications
Table, e.g., 360µA max. at 25oC.
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
5
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
Maximum Clock
Frequency fMAX 2 6 - - 5 - - 4 - - MHz
4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
Clock Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
Setup Time
Data to Clock tSU 260--75- -90--ns
4.5 12 - - 15 - - 18 - - ns
610--13- -15--ns
Hold Time
Data to Clock tH25--5--5--ns
4.5 5 - - 5 - - 5 - - ns
65--5--5--ns
HCT TYPES
Maximum Clock
Frequency fMAX 4.5 25 - - 20 - - 16 - - MHz
Clock Pulse Width tW4.5 20 - - 25 - - 30 - - ns
Setup Time
Data to Clock tSU 4.5 20 - - 25 - - 30 - - ns
Hold Time
Data to Clock (534) tH4.5 5 - - 5 - - 5 - - ns
Hold Time
Data to Clock (564) tH4.5 3 - - 3 - - 3 - - ns
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF
Clock to Output 2 - - 165 - 205 - 250 ns
4.5 - - 33 - 41 - 50 ns
CL = 15pF 5 - 13 - - - - - ns
CL = 50pF 6 - - 28 - 35 - 43 ns
Output Disable to Q (534) tPLZ,t
PHZ CL = 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
CL = 50pF 6 - - 26 - 33 - 38 ns
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
6
Output Disable to Q (564) tPLZ,t
PHZ CL = 50pF 2 - - 135 - 170 - 205 ns
4.5 - - 27 - 34 - 41 ns
CL = 15pF 5 - 12 - - - - - ns
CL = 50pF 6 - - 23 - 29 - 35 ns
Output Enable to Q tPZL,t
PZH CL = 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
CL = 50pF 6 - - 26 - 33 - 38 ns
Maximum Clock Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz
Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns
4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns
Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF
Three-State Output
Capacitance CO- - 20 - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD -5-32-----pF
HCT TYPES
Propagation Delay tPHL, tPLH
Clock to Output CL = 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns
Output Disable to Q tPLZ,t
PHZ CL = 50pF 4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
Output Enable to Q tPZL,t
PZH CL = 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns
Maximum Clock Frequency fMAX CL = 15pF 5 - 50 - - - - - MHz
Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns
Input Capacitance CICL = 50pF - 10 - 10 - 10 - 10 pF
Three-State Output
Capacitance CO- - 20 - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD -5-36-----pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD=C
PD VCC2fi+∑CLVCC2fOwhere fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
7
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
8
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
50% 10%
90%
GN
D
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
T
IED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZ
H
OUTPUT
RL = 1kΩ
CL
50pF
CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8681401RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-8681501RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-8984901RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
CD54HC534F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD54HC564F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD54HCT534F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD54HCT564F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD74HC534E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC534EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC564E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC564EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC564M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC564M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC564M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC564M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC564ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC564MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT534E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT534EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT564E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT564EE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT564M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT564ME4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD74HCT564MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC534, CD54HC564, CD54HCT534, CD54HCT564, CD74HC534, CD74HC564, CD74HCT534, CD74HCT564 :
•Catalog: CD74HC534, CD74HC564, CD74HCT534, CD74HCT564
•Military: CD54HC534, CD54HC564, CD54HCT534, CD54HCT564
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC564M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC564M96 SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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