1/42
AN1262
APPLICATION NOTE
May 2001
1 FLYBACK BASICS
Flyback operation will be illustrated with reference to the basic circuit and the waveforms of fig. 1. It is a two-
step proc ess. Durin g the ON-time of the switch, energy is taken from the input and stored in the primary winding
of the flyback transformer (actually, two coupled inductor s). A t the secondary side, the catch diode is reverse-
biased, thus the load is being supplied by the energy stored in the output bulk capacitor.
Figu re 1. Fly ba c k Top ol ogy and ass oc i ate d wave form s.
Q
CLOCK
Ip
Is
Vdrain Vin n•Vout
DCM oper ati on
Q
CLOCK
Ip
Is
Vdrain
∆Ip
CCM operation
Q
CLOCK
Ip
Is
Vdrain
TRANSITION
Vin
ISOLATED
FEEDBACK
Lp Vout
Is
L6590
L6590D
L6590A Clock
+
-
DRAIN
GND
1
1/100
S
RQ
Max. Dut
y
c
y
cle
OSCILLATOR Driver
Rsense
OCP+
-
0.5 V
+
-E/A
2. 5 V
VFB
COMP
FREQUENCY
COMPENSATION
Vcc
LEB
Vac Ls
n:1
Ip
PWM
Clock
by Claudio Adragna
OFFLINE FLYBACK CONVERTERS DESIGN
METHODOLOGY WITH THE L6590 FAMILY
The design of flyback conver ters is quite a demandi ng task that requires SMPS engineers to cope with sev-
eral problem ar eas such as magnetics, control loop analys is, power devices, as well as re gulations concern-
ing safety, EMC and the emerging standby consumption requirements. Lots of variable are involved and
complex tradeoffs are necessary to meet the goal.
In this scenario, the high-voltage monolithic switchers of the L6590 family greatly simplify the task and, at
the same time, allow to build robust and cost-effective low-power systems.
In this application note, after a review of flyback topology, a step-by-step design procedure of an offline sin-
gle-output flyback converter will be outlined. As an example, the design of the test board will be carried out
in details.
AN1262 APP LICATION NO TE
2/42
When the switch turns off, the primary c ircuit is open and the energy stored in the primary is transferred to the
secondary by magnetic coupling. The catch diode is forward-biased, and the stored energy is delivered to the
output capacitor and the load. The output voltage V
out
is reflected back to the primary through the turns ratio n
(V
R
, reflected voltage) and adds up to the input voltage V
in
, giving origin to a much higher voltage on the drain
of the MOSFET.
Flyback is operated in DC M (Discontinuous Conduction Mode) when the input -or primary - current starts from
zero at the beginning of each sw itchi ng cycle. This happens bec ause the secondary of the transform er has dis-
charged all the energy stored in the previous period. If this energy transfer is not complete, the primary current
will start from a value greater than zero at the beginning of each cycle. Then flyback is said to be operated in
CCM ( Continuous C onduction Mode). DCM is char acterized by currents shaped in a tr iangular fashi on, whereas
CCM features trapezoidal currents.
The boundary between these two types of operation depends on several parameters. For a given converter,
that is, as the switching frequency , inductance of the primary winding, transformer turns rati o and regulated out-
put voltage are defined, it depends on the input voltage and the output load.
At design time, whether t he converter will be operated in CCM or in DCM and where the boundary will be located is
u p to the desi gner. Usual ly CCM is sel ected wit h the objective of maximizi ng converter's po wer capability or minimiz-
ing primary RMS curr ent. However, in CCM operation the system's dynamic behavio r is considerabl y worse.
Usually, the converters based on the L6590 family devices are able to deliver the desired output power even
with DCM operation, thus CCM will not be considered.
Table 1. Converter specification data and pre-design ch oices
Converter Electrical Specification
VACmin Minimum mains voltage
VACmax Maximum mains voltage
fLMains frequency (@ min. mains)
NHNumber of holdup cycles
Vout Regulated output voltage
∆Vout% Percent output voltage tolerance (±)
Vr% Percent output voltage ripple
Poutmax Maximum output power
ηExpected converter efficiency
Tamb Maximum ambient temperature
Pre-design Choices
VRReflected voltage
ηTTransformer efficiency
Vspike Leakage inductance overvoltage
Vcc IC supply voltage
VFSecondary diode forward drop
VBF Bridge Rectifier + EMI filter voltage drop
3/42
AN1262 APPLICATION NOTE
2 CONVERTER ELECTRICAL SPECIFICATION
The star ting point of the design p rocedur e is the properties of the c onverter as a bla ck-box, that is the s et of data
listed in the electrical specification table (table 1). Additional requirements, such as efficiency at zero load or
line/load r egulation or max imum junction temp erature, etc., can be added to that list and their i mpact will be con-
sidered where appropriate.
■
Mains Voltag e: Range and Frequency.
There are basically the three possible options listed in table 2,
where a variation of ± 20% is assumed, according to common practice. There are exceptions like some
distribution lines rated at 277 VAC, where a ± 10% spread can be considered, or other special cases for
specific applications. Tab le 2 s hows al so the li ne f requency to be c onsidere d in the stan dard c ases at
the minimum specified mains voltages. An additional specification may require the converter to be shut
down if the mains voltage falls below a "b rownout level". This additional specification will be used for
setting up the brownout protection on the types where it is available.
Table 2. Mains voltage specifications
■
Number of holdup cycles.
The holdup requirement is the ability of the converter to keep the output volt-
age in regulation even in case of mains interruption (missing cycles). This is usually specified in terms
of number of mains cycles NH. This feature is not always demanded (in which case, NH = 0), otherwise
the typical requirement is 1 mains cycle, that is NH = 1. It impacts on the input bulk capacitor selection.
■
Output voltage tolerance.
It can be expressed either in absolute value or as a percentage of the nominal
voltage. Th is requirement, as well as the ones o n lin e and load regulation, if specified, will affect the
choice of the feedback technique (primary or secondary).
■
Output voltage ripple.
The ripple superimposed on top of the DC output voltage is specified as the peak-
to-peak amplitude and includes both low frequency (at 2·fL) and high frequency (fsw) component.
Switch ing noise due to parasitics of the print ed circuit b oard and rando m noise are beyond the s cope
of this procedure. This requirement, if tight, may require the use of an additional filtering cell at the out-
put.
■
Converter Efficiency.
The efficiency is, by definition, the ratio of the output power to the input powe r.
This figure is strongly dependent on the output voltage, because of the losses on the secondary diode.
It should be set based on experience, us ing numbers of similar convert ers as a reference. As a rule of
thumb, 75% (η = 0.75) can be used for a low voltage output (3.3 V or 5 V) and 80% (η = 0.8) for higher
output voltages (12 V and above).
3 PRE-DESIGN CHOICES
Before starting the design calculati ons of the various parts of the converter, some parameters not defined at the
"black-box level" need to be fixed. There is some degree of freedom in the selection of these parameters, pro-
vided some constraints are taken into account.
■
Reflected Voltage.
In principle, the reflected voltage should be as high as possible. In fact this leads to
a greater duty cycle, which minimizes the RMS current through the IC's MOSFET for a given power
throughput. There are two pos sibl e limitat ions to the maxim um reflected vol tage . One is th e maxi mum
duty cycle Dmax allowed by the devices (67% m in.); some margin shou ld be considered for load tr an-
sients, thus the reflected voltage should be such that the maximum duty cycle (at minimum input voltage
Input (VAC)V
ACmin (VAC)V
ACmax (VAC)f
L
(Hz)
110 88 132 60
220 176 264 50
WRM (Wide Range Mains) 88 264 60
AN1262 APP LICATION NO TE
4/42
and maximum output power) does not exceed 62-64%. The other limitation is that the sum of the max-
imum input voltage, reflected voltag e and overvo ltage spike - du e to the leakage induc tance - must be
below the breakdown of the internal MOSFET (700 V min.). Some margin needs also to be considered:
at least 50V is recommended to take the forward recovery of the diode of the clamp circuit and param-
eter spread into account. Fi gure 2 il lustra tes sche matically how the drain v oltage is ap portioned. T he
suggested value of VR is 130 V: i t leads to a maximum drain voltage slightly exceeding 500 V in 220VAC
or WRM applications, and about 320 V in 110 VAC application, thus leaving enough room for an efficient
leakage inductance demagnetization (see below). The maximum duty cycle will be about 60% in
110VAC and WRM applica tions , and close to 36% in 220 VAC applications.
Figure 2. Drain voltage compo sition.
■
Leakage inductance overvoltage.
The energy stored in the mutual inductance of the transformer at the
primary side is not completely transferred to the secondary, after MOSFET turn-off, until the leakage
inductance is demagnetized. This delays and makes inefficient the energy transfer from primary to sec-
ondary. To minimize this noxious effect the voltage across the leakage inductance (the leakage induct-
ance spike) that resets the inductance itself should be as high as possible. Obviously, this is limited by
the maximum allowable drain voltage. With the reflected voltage selected as previously discussed, it is
possible to allow about 140 V extra voltage in 220 VAC or WRM applications and much more in 110 VAC
applications (see fig. 2). This will affect the design of the clamp circuit.
■
Transformer ef f iciency.
B y definition, it is t he ratio of the power del ivered by the s econdary windin g to
the power entering the primary. The secondary power includes the converter output power and the one
dissipated in the secondary rectifier. Besides the secondary one, the prim ary power in cludes the one
dissipated insid e t he transf orme r and t hat not tr ansf erred t o the s econdary si de and dissipat ed o n t he
leakage inductance. For typical transformers used in converters based on the L6590 family IC's, typical
values of efficiency ranges between 88% and 95%, depending on the power level and on the construc-
tion technique. Efficiency increases with the power level and by using winding interleaving construction
technique. For consistency, check that the input power of the transformer be less than the converter
input power.
■
Device sup ply voltage.
The supply v ol tag e range of the IC spans from 7 to 16.5 V . Such a wide range
is envisaged to accommoda te the variation th at the voltage generated by the s elf-supply winding may
Vin
VR
Vspike
Clamp Diode
forward recover
y
700 V
374 V
187 V
504 V
317 V
≤ 650 V mar
g
in
ON OFF
Leak. Inductance
dema
g
netization
Current flows at t he
secondar
y
side
Prim. Inductance resonates
with drain capacitance
Leak. Inductance resonates
with drain capacitance
Transformer
dema
g
netised
5/42
AN1262 APPLICATION NOTE
experience in converters with opto-isolated feedback. This variation is a result of the poor magnetic cou-
pling with the secondary winding. It is then recommended to design the turns ratio of the self-supply
winding so as to get a voltage approximately in the middle of this range (e.g. 11-12 V). This will give
allowance for increasing at heavy load and dropping at zero load.
■
Secondary diode forward drop
. The type of secondary diode will be selected basically depending on the
output voltage. In fact this determines the maximum reverse voltage applied to the diode while the MOS-
FET is switched on. For low output volt ages ≤15 V) a Schottky diode can be used and a typical forward
drop of 0.5V can be considered; for higher output voltages an ultrafast PN diode will be used, with a
typical forward drop of 0. 8 V.
■
Bridge Rectifier + EMI filter voltage drop.
This drop is subtracted to the peak of the input AC voltage and
affects the peak v oltage o f the rip ple superi mpo se d on top of t he DC voltage ac ross the i nput bulk ca-
pacitor. A typical value can be 3 V .
4 PRELIMINARY CALCULATIONS (ST E P 1)
There are a few quantities that need to be calculated before starting the individual design of each functional
block of the converter. They are summarized in table 3.
Table 3. Preliminary cal culations (step 1).
5 BRIDGE RECTIFIER SELECTION
Due to the lim ited power range that the device is able to handle, no special considerati ons are needed to select the
di odes of the bridge rectifier. Any 1A rated standard diodes with 400/600 V reverse voltage are suitable. Some man-
u facturers ma ke int egrated bri dge rectifiers housed in smal l packages. See t able 4 for so me suggested part s.
Table 4. 1A standard silicon rec tifier and bridge selecti on
Symbol Parameter Definition
Pin Converter Input Power
Iout DC Output Current
VPKmin Minimum Peak Input Voltage VPKmin = VACmin ·
VPKmax Ma ximum Peak Input Voltage
Type Part Number Rated Voltage Package Manufacturer(s)
Diode 1N4004 400 DO41 GI, GS, FAGOR, HTA, ON, TSC
Diode 1N4005 600 DO41 GI, GS, FAGOR, HTA, ON, TSC
Bridge DF04M 400 DIL4 GI,TSC
Bridge DF06M 600 DIL4 GI,TSC
Bridge KBP104G 400 SIL4 TSC
Bridge KBP105G 600 SIL4 TSC
Bridge DFS04M 400 DIL4 (SMD) HTA
Bridge DFS06M 600 DIL4 (SMD) HTA
Pin Poutmax
η
---------------------=
Iout Poutmax
Vout
---------------------=
2V
BF
–
VPKmax VACmax 2
⋅
=
AN1262 APP LICATION NO TE
6/42
6 INPUT BULK CAPACITOR SELECTION
The input bulk capacitor C
in
, along with the bridge rectifier, converts the AC mains voltage to an unregulated
DC bus, V
in
, which is the input voltage for the downstr eam flyback converter. C
in
mu st be large enough to have
a rel ativel y low r ipple s uperimposed on top of the DC level, as s hown in fig. 3. At mi nimum s pecified mains volt-
age, the value of C
in
determines the absolute minimum, V
inmin
, of the DC input voltage of the converter. The
maximum duty cycle and the maximum peak current allowed by the IC must not be exceeded at this voltage.
However, as to thermal consideration, the bus DC voltage (V
DCmin
@ V
ACmin
) should be considered.
Figure 3. Input voltage waveforms:
a) without hol dup c apa b il i ty ;
b) wit h hol du p c apabi lit y.
Large v alues of C
in
resul t in higher V
DCmin
and V
inmin
, lower peak an d RMS current through the power MOSFET
(i.e. less power dissi pation in th e device) and less duty cycle range to achieve regulation but, on the other hand,
also in bigger capacitor size, higher peak and RMS current drawn from the mains ( i.e. more power dissipation
in the bridge rectifier). Small values of C
in
give origin to the opposite situation.
Experience shows that a good compromise between these contrasting requirements is a C
in
value that causes
the peak-to-peak r ipple amplitude to be 25-30% of the peak mains voltage (@ V
ACmin
), which means that V
inmin
will be 70-75% of the peak value. Anyway, if holdup capabil ity is required, a much larger capacitance values wil l
be needed: the voltage ripple across C
in
is expected to be 25-30% of the peak value, after 1 mains cycle miss-
ing, which means that in normal operation the ripple will be much less.
Table 5 summariz es the required capacitance per watt of input power for a given value of V
inmin
, with and with-
out holdup requirement, and shows the resulting values of V
DCmin
. Th is al lows to c alculate the mi nimum c apac-
itance needed, by multiplying the value taken from the table times P
in
. Then a standard value will be selected,
taking also the tolerance into account.
a)
Vin VPKmin
Vinmin VDCmin
TC
1
fL
Vin VPKmin
Vinmin
after fail
VDCmin
TC
after fail
1 missin
g
c
y
cle
b)
Vinmin
TC
7/42
AN1262 APPLICATION NOTE
Table 5. Cin values for 1W input power
The actual values of V
inmin
and V
DCmin
need to be re calculated with the actual capacitance value. Since th e evaluation
of V
inmin
i nvolves an equation having no closed form solution, an iterat ive cycle needs to be established:
; (1)
where T
C
is the recharging time of C
in
, that is the time w hile the bridge diodes are conducting, which can be
initially assumed equal to zero. After few iterations both V
inmin
and T
C
will converge to their respective values.
In case of holdup requirement the cycle should be executed twice. The first time w i th N
H
= 1 to find V
inmin
after
one mains cycle missing (which will be used to check for maximum duty cycle and maximum peak current) the
second one wi th N
H
= 0 to find V
inmin
in nor mal operati on ( to be used for steady state and thermal c alculat ions).
V
DCmin
will be simply the average of V
inmin
(calculated with N
H
= 0 anyway) and V
PKmin
:
(2)
The volt age rating of C
in
is selected dependi ng on V
PKmax
: it is usually 200 V for 110 V
AC
applications and 400V
for 220 V
AC
or WRM applications.
7 PRELIMINARY CALCULATIONS (ST E P 2)
The next step is to check for not exceeding the limits imposed by the IC. Prior to this, the power processed by
the transformer (P
inT
) and the average voltage drop across the ON-resistance of the internal MOSFET
(V
DS(on)x
) will be evaluated. V
DS(on)x
is s ubtracted t o V
inmin
and the resul ting value is the v oltage actually applied
to the primary winding of the transformer. The R
DS(on)
used must take temperature into account. Use the max-
imum value defined at 125°C.
The fir st li mit to be checked is the maximum dut y cy cle D
X
. If it exceeds 62- 64%, either the reflected v oltage V
R
should be lowered or the minimum input DC voltage V
inmin
should be increased by selecting a lar ger input ca-
pacitance.
The second limit to be checked is the maximum drain voltage during the OFF-state of the MOS FET. A t least
50V margin s hould be ensu red. The over voltage s pike can be reduced to allow more reflected voltage if n eces-
sary, keeping in mi nd that it cannot be much lower than V
R
not to hurt the primary- to-secondary energy tr ansfer.
The last check concerns the peak primary current that must not exceed the minimum guaranteed OCP threshold
(0.55A). If this is exceeded, a higher maximum duty cycle D
X
should be used, if possible. Also a higher V
inmin
is beneficial. Some iterations, involving a recheck of the first two points, may be necessary to find the optimum
compromise. If no solution can be found, either C CM operation should be considered or the power handled by
the converter should be derated.
110 VAC or WRM 220 VAC
NH=0 2.0 µF/W 3.0 µF/W 0.55 µF/W 0.8 µF/W
Vinmin = 90V
VDCmin = 105V Vinmin = 100V
VDCmin = 110V Vinmin = 180V
VDCmin = 210V Vinmin = 200V
VDCmin =220V
NH=1 7.2 µF/W 10.4 µF/W 1.8 µF/W 2.8 µF/W
Vinmin = 90V
VDCmin = 116V Vinmin = 100V
VDCmin = 117V Vinmin = 180V
VDCmin = 236V Vinmin = 200V
VDCmin =239V
Vinmin VPKmin
2Pin
Cin
--------–12N
H
⋅+
f
L
------------------------- 2–Tc
⋅
⋅=
T
c
arccos V
inmin
V
PKmin
-------------------
2
π
f
L
⋅⋅
---------------------------------------------=
V
DCmin 1
2
--- VPKmin Vinmin
+()⋅=
AN1262 APP LICATION NO TE
8/42
All of the above mentioned calculation steps are summarized in table 6.
Table 6. Preliminary Calculations (step 2)
8 OPERATING CONDITIONS @ VIN = VDCMIN
From the thermal point of view the heaviest operating conditions for the IC, and for most of the other parts of
the converter as well, are usually encountered at minimum input voltage.
That is why the operating cond itions @ V
in
= V
DCmin
need being evaluated. This will be done with the aid of the
relationships in table 7.
Table 7. Relationship useful for calculating converter's operating conditions @ Vin = VDCmin
Symbol Parameter Definition
PinT Transfor mer Input Powe r
VDS(on)x Max. average drop on RDS(on) in ON-state
DxMaximum Duty Cycle
VDSmax Maximum drain Voltage in OFF-state VDSmax = VPKmax + VR + Vspike
Ippkx Max. Peak Primary Current
Symbol Description Definition
D Duty Cycle (switch ON-time to switching period ratio)
Ippk Peak Primary Current Ippk = Ippkx
IpDC DC Primary Current
IpRMS Total RMS Primary Current
IpAC RMS Primary Current (AC component only)
D ‘ Seconda ry diode condu ction time to switching per iod ratio
Ispk Peak Secondary Current
IsDC DC Secondary Current IsDC = Iout
PinT Vout VF
+
()
Iout
⋅
ηT
-------------------------------------------=
VDS on
() Vinmin VR
+
1Vinmin VR
⋅
Pin RDS on
()
⋅
----------------------------------+
--------------------------------------------
≈
DXVR
Vinmin VDS on
()
x
–()V
R
+
-----------------------------------------------------------------=
Ippkx PinT
Vinmin VDS on
()
x
–
---------------------------------------------- 2
DX
-------
⋅=
DVinmin VDS on
()
x
–
VDCmin VDS on
()
x
–
-------------------------------------------------= DX
⋅
IpDC DIp
pk
⋅2
-------------------=
IpRMS Ippk D
3
----
⋅
=
IpAC IpRMS
2IpDC
2
–=
D'VDCmin VDS on
()
x
–
VR
------------------------------------------------- D
⋅
=
Ispk 2I
out
⋅D'
-----------------=
9/42
AN1262 APPLICATION NOTE
Once this information has been found, it is possible to evaluate the power dissipation of the IC and check for
thermal limitations. Table 8 summarizes the relationships that can be u sed for thi s evaluation. In those formulae:
- T
c
is the crossover time of the voltage and current waveforms at MOSFET's turn off;
- C
drain
is the total capacitance of the drai n, composed of the C
oss
of the MOSFET, the parasitic capacitance of
the primary winding and, in case, some external capacitance.
As previously said, the worst-case operating conditions for the IC usually occur at V
in
= V
DCmin
, however it is
worthwhile checking the losses also at maximum input voltage, that is at V
in
= V
PKmax
, especially if an external
capacitor is added on the drain.
With the w orst-case total losses in the IC it is possible to find the maximum junction-to-ambient thermal resis-
tance allowed for safe operation at maximum ambient temperature.
The operating temperature range of the devices extends to 150 °C, however designing for such high tempera-
ture is not recommended. A reasonable target can be to design for 125 °C maximum die temperature:
(3)
Table 8. IC's power losses estim ate
With the aid of the diagrams shown in fig. 20 it is possible to estimate whether the required thermal resistance
is feasible or not and, in the posit ive case, how large the on-board copper area is supposed to be. Consider that
copper areas larger than 4 cm
2
do not give sign ificant reducti on of thermal resis tance and may cause PCB lay-
outing to become a serious issue.
If the thermal chec k does not give positi ve results, a different heatsinking s trategy may be consid ered, otherwi se
a higher maximum duty cycle D
X
should be used, if possible, to reduce the RMS current. Also a higher V
inmin
Symbol Description Definition
IsRMS Total RMS Secondary Current
IsAC RMS Secondary Current (AC component only)
Symbol Description Definition
Pcond Conduction losses
Psw Switching losses
PCAP Capacitive losses
PQQuiescent losses PQ = VCC · Iop
Assume:RDS(on) max = 28 Ω (@ Tj = 125 °C)
Tc = 50ns
fsw = 65kHz
Cdrain = 100pF
Iop = 7mA
IsRMS Ispk D'
3
-----
⋅
=
IsAC IsRMS
2IsDC
2
–=
Rthmax 125 Tamb
–
PQPcond Psw Pcap
+++
-----------------------------------------------------------------=
Pcond IpRMS
2RDS on
()
max
⋅
=
Psw 1
3
--- Vin VR
+()Ippk Tc
⋅⋅⋅≈ f
sw
⋅
PCAP 1
2
--- Cdrain Vin VR
+()
2
⋅⋅≈ f
sw
⋅
Table 7. (continued)
AN1262 APP LICATION NO TE
10/42
(that is a larger input capacitor) is of help. Some iterations, involving a recheck of the points mentioned in "Pre-
liminary Calculations - step 2", may be necessary.
If no solution can be found, either some specification should be relaxed or the power handled by the converter
should be derated.
9 FLYBACK TRANSFORMER DESIGN
To comp lete the set of data needed to design the flybac k transformer, the primary inductanc e value (L
p
) and the
primary-to-secondary turns ratio (n) are still to be defined.
The primary inductance will be chosen so that the converter is operated on the boundary between DCM and
CCM at V
in
= V
inmin
:
(4)
while the pr imary-to-secondary turns ratio is defined so as to get the desired reflected voltage V
R
:
(5)
With the complete set of specification, the transformer design can start with the selection of the magnetic core
material and geometry.
Table 9. Ferrite Materials selection
As to the magnetic material, a standard soft ferrite for pow er applications (gapped core-set with bobbin) is the
usual choice: the switching frequency is not so high thus special grades for high frequency oper ation are not
required. Table 9 shows some suitable materials.
The geometry will be usually a popular E or E-derived type. Other configurations, such as RM or PQ cores, are not
recommended because they are inherently high leakage geometries, since they result in narrower and t hicker wind-
ings. Conside r that minimizing leakage induc tance is one of the major task s in the desi gn of a fly back transformer .
Among the various shapes and styles offered by manuf acturers the most suitable one wil l be selected with technical
and econom ic considerations. Table 10 shows some possible choices with the relevant data useful for the design.
The next quantity to be defined is the peak flux density B
max
which the transform er will be operated at. Being
this a DCM design, B
max
will also equal the maximum flux density swing
∆
B
max
.
Grade Saturation flux density
[T] Specific Power Losses @100 °C [W/cm3]Manufacturer
B2 0.36 THOMSON
3C85 0.33 PHILIPS
N67 0.38 EPCOS (ex S+M)
PC30 0.39 TDK
F44 0.4 MMG
Lp Vinmin VDS on)x
()
–()D
X
⋅[]
2
2f
sw PinT
⋅⋅
-------------------------------------------------------------------------=
nVR
Vout VF
+
-------------------------=
PFe 1.15 10 5
–B2.26
∆fsw
1.11
⋅⋅ ⋅=
P
Fe 1.54 10 7
–B2.62
∆fsw
1.54
⋅⋅ ⋅=
P
Fe 8.53 10 7
–B2.54
∆fsw
1.36
⋅⋅ ⋅=
P
Fe 1.59 10 6
–B2.58
∆fsw
1.32
⋅⋅ ⋅=
P
Fe 2.39 10 6
–B2.23
∆fsw
1.26
⋅⋅ ⋅=
11/42
AN1262 APPLICATION NOTE
Due to the moderate switching frequency, B
max
will be limited by core saturation and not by core losses. This
means that transformer's power loss es will be located mostly in the windings.
As shown in table 9, ferrites sat urate above 0.3 T thus a value of B
max
e qual to 0.28-0.30 T may be selected to
maximize core utilization, or B
max
= 0.25 T can be chosen for a more conservative design.
This maximum peak flux density will occur when the peak primary current is maximum. However, it is not suffi-
cient to consider the peak current Ip
pkx
resulting from table 6. To guarantee that the transformer does not sat-
urate even under short circuit conditions, the maximum peak primary current to be considered is the maximum
value of the OCP threshold (I
lim
= 0.7A, from the datasheet).
Now a step-by-step procedure for the design of the transformer will be given.
Table 10. Core list and significant design data
1)
Choose core size.
Transformer's core must be able to handle the power throughput P
inT
without saturating
and with acceptable pow er losses, with the minimum size. Determining its optimum size is a trial-and-error
process and a proper starting point may reduce considerably the number of iterations needed.
A most common w ay of describing core s ize is the so -called Area Product (AP), which is the product of the
effective cross-sectional area of the core times the window area available to accommodate the windings. It
is possible to define the minimum AP required by a specific application.
The following equation can be useful to estimate the minimum AP (in cm
4
) required:
Core Ve
[cm3]Ae
[cm2]Aw
[cm2]AP
[cm4]K1 K2 Lt
[cm] WB
[cm] Rth
[°C/W]
THOMSON (B2)
EF1505A 0.51 0.15 0.15 0.022 29.7 -0.68 2.63 0.92 75
EF2007A 1.46 0.31 0.26 0.081 61.1 -0.7 3.65 1.32 45
EF2509A 3.3 0.58 0.4 0.232 103 -0.73 4.64 1.64 30
E2006A 1.5 0.32 0.35 0.112 62.2 -0.7 3.9 1.18 46
E2507A 3.2 0.55 0.6 0.33 90 -0.73 5.2 1.54 40
PHILIPS (3C85)
E16/8/5 0.75 0.201 0.216 0.043 42.2 -0.7 3.3 0.94 65
E20/10/6 1.49 0.32 0.35 0.112 62.2 -0.69 3.9 1.18 46
E25/13/7 2.99 0.52 0.56 0.291 90 -0.73 4.9 1.56 40
EPCOS (ex S+M) (N67)
E16/8/5 0.76 0.2 0.22 0.044 42.2 -0.7 3.4 1 65
E20/10/6 1.49 0.32 0.34 0.109 62.2 -0.69 4.12 1.25 46
E25/13/7 3.02 0.52 0.61 0.317 90 -0.73 5 1.56 40
TDK (PC30)
EI16-Z 0.67 0.198 0.267 0.053 66 -0.57 3.31 0.86 44
EI22-Z 1.63 0.42 0.2 0.084 85.4 -0.71 3.86 0.845 33
EI25-Z 1.93 0.41 0.425 0.174 119 -0.57 4.94 0.98 31
MMG - NEOSID (F44)
EF16 0.754 0.225 0.216 0.049 42.2 -0.7 3.3 1 65
EF20 1.5 0.314 0.348 0.109 62.2 -0.69 3.9 1.2 46
EF25 3.02 0.515 0.564 0.29 90 -0.73 4.8 1.6 40
AN1262 APP LICATION NO TE
12/42
(6)
In this equation
∆
T is the hot-spot temperature rise (located in the core center leg, where heat can be re-
moved more difficultly), defined as
∆
T = T
max
- T
amb
. For reliability reasons T
max
is usually limited at 100°C
where, by the way, ferri tes usual ly feature minimum losses . K
u
is the w indow utili zation fac tor , that is the por-
tion of the total core window area occupied by the windings, whic h can be estimated equal to 0.4 for margin
wound construction and to 0.7 for triple insulated wire construction.
The smallest core with an AP greater then AP
min
will be chosen from the catalog data (the core list of table
10 ca n be used as a r eference) . If there is a core wi th an AP < AP
min
but very close to, it might be worthwhi le
trying to design with this smaller core before trying the larger one.
2)
Calculate the required minimum number of primary turns of the primary winding.
It will be given by:
3)
Define primary and secondary windings' turns number.
In the case of single-output under consideration, the
secondary winding turns number Ns will be simply:
,
that is, the res ult of the division will be rounded up to the next lar ger integer. The actual pri mary turns will then
be calculated, rounding the result to the closest integer.
Np = [Ns · n + 0.5].
It can be convenient to round to the next even number when interleaved winding technique is to be used for
transformer construction, so as to split the primary in two equal halves.
4)
Calculate the air gap length.
The gap length (l
g
) needed to get the desired inductance Lp will be calculated
with the follow ing empirical formula:
(7)
If the calculated value is not availabl e as a standard part, if possible, the primary turns number can be adjust-
ed a little bit to get an off-the-shelf part.
The air gap should be located on the core center leg only, to minimize radiated fields. In prototyping, center
leg grindi ng to get nonstandard gap values can be avoided by keepi ng the two half-cores apar t by about half
the calculated value with spacers.
5)
Calculate transformer total losses.
The allowed total transform er losses (P
tot
) can be calculated by dividing
the hot-spot temperature rise
∆
T by the thermal resistance of the wound core R
th(core)
:
If the manu facturer does not provi de thermal data, R
th(core)
can be estimated. It has been shown [1] that there
is a good correlation between core's area product and thermal resistance, regardless of its shape:
R
th(core)
≈
23 · AP
-0.37
[°C/W];
Apmin 103LpIpRMS
⋅
T1
2
---
∆KuBmax
⋅⋅
----------------------------------------
1.316
cm4
[]⋅
=
Npmin Lp 0.7⋅
Bmax Ae
⋅
------------------------- 104
⋅
=
NsNp
n
-------- 1
+=
IgLp
Np2
---------- 109
k1
---------
⋅
1
k2
------
mm[]
=
P
tot T∆
Rth core
()
----------------------- W[]
=
13/42
AN1262 APPLICATION NOTE
this best-fit equation refers to natural convection cooling.
6)
Calculate the actual flux swing,
the actual core losses and the allowed copper losses. The flux swing will be
given by:
(8)
and the corresponding core losses can be calculated with the form ulae in table 9:
(9)
The allowed copper losses will obviously be:
P
Cu
= P
tot
- P
Fe
[W] (10)
7)
Design windings.
The goal is to find the right wire size so that copper losses are within the limit stated by
(10). At this mo ment, loss es due to s kin and prox imity effect will not be accounted for. The constr ucti on tech-
nique of the transformer will be such that these effects will be minimized.
Copper losses will be equally apportioned to the primary and the secondary winding (the power handled by
the auxi liary one is negligible ). Therefore the maxim um primar y and secondary winding resi stance w ill be re-
spectively:
; (11)
The primar y and secondary conductor copper cross-section ar ea will be obtained considering the resistivity
of copper at 100°C (
ρ
100
= 2.303·10
-6
Ω
·cm) and the average length-per-tur n (4) of the bobbin associated to
the selected core:
(12)
(13)
A wire table (like the sample one shown in table 11) will be looked up and a wire with a copper area (A p
Cu
,
As
Cu
) equal or greater than the minimum above calculated will be selected. Anyway, to minimize skin effect,
the selected wire diameter should not exceed 2·
δ
, where
δ
is the skin depth of copper (about 0.3 mm at 65
kHz and 100°C). In practice, the maximum wire size for minimum skin effect is AWG23 (
∅
0.57 mm, A
Cu
=
0.2573 mm
2
). If Ap
Cu
is larger, a number (Nwp, Nws) of such (or smaller) wires will be paralleled so as to
achieve the desired total area:
where the results will be rounded up to the next larger integer.
B∆Lp lppk
⋅
Np Ae
⋅
---------------------- 104T[]⋅=
P
Fe VekB
p
∆f
sw
q[W]⋅⋅ ⋅=
Rp PCu
2Ip
RMS
2
⋅
------------------------ [Ω]=Rs PCu
2Is
RMS
2
⋅
------------------------ [Ω]=
ApCumin ρ100 Np Lt
⋅⋅
Rp
--------------------------------- [cm2]=
AsCumin ρ100 Ns Lt
⋅⋅
Rs
--------------------------------- cm2
[]=
Nwp ApCumin
ApCu
-----------------------=
Nws AsCumin
AsCu
----------------------=
AN1262 APP LICATION NO TE
14/42
Table 11. Wire Table (RS-214). Copper wire. Heavy insulati on.
Finally the total winding area must be checked to make sure they fit the bobbin window Aw:
Api · Nwp · Np + As
i
· Nws · Ns
≤
K
u
· Aw (14)
where Api and Asi are the individ ual wire cross- secti on, primary and secondary respectiv e ly, inclu ding isola-
tion. If the above inequality is not verified there are the following options:
a) if Np is quite larger than Np
min
, try decreasing Np and go back to step 3;
b) choose a smaller wire, recalculate Nwp and Nws and recheck window fitting;
c) use few er wires in a strand accepting a likely larger temperature rise;
d) use the next size core and restart from step 2.
Finally, the auxi liar y winding w ill be d efined. It has not been c onsidered before bec ause it handles a very low
power, thus it will be made with a single thin wire (e.g. AWG32 or AWG33) which gives a negligib le contr ibu-
tion to winding build and losses. Just the turns number needs to be defined:
(15)
where 0.7 V is the typical forward drop on the auxiliary (small signal) diode.
8)
Calculate actual power dissipation and hot-spot temperature rise.
The actual resistance of the primary and
secondary windings has to be calculated first:
; ,
AWG Diameter
Copper
[cm]
Diameter
Insulated
[cm]
Area
Copper
[cm2]
Area
Insulated
[cm2]
22 0.064 0.071 0.003255 0.004013
23 0.057 0.064 0.002582 0.003221
24 0.051 0.057 0.002047 0.002586
25 0.045 0.051 0.001624 0.002078
26 0.040 0.046 0.001287 0.001671
27 0.036 0.041 0.001021 0.001344
28 0.032 0.037 0.000810 0.001083
29 0.029 0.033 0.000642 0.000872
30 0.025 0.030 0.000509 0.000704
31 0.023 0.027 0.000404 0.000568
32 0.020 0.024 0.000320 0.000459
33 0.018 0.022 0.000254 0.000371
Naux Ns VCC 0.7+
Vout VF
+
--------------------------
⋅=
Rp ρ100 Np Lt
⋅
Nwp ApCu
⋅
-------------------------------
⋅=Rs ρ100 Ns Lt
⋅
Nws AsCu
⋅
-------------------------------
⋅=
15/42
AN1262 APPLICATION NOTE
then the total power dissipation and the hot spot temperature rise will be respectively:
Finally, some suggestions on the transformer construction techniques. When building a transformer, the general
rule is to minimize parasitics, basically leakage inductance and winding capacitance.
In order for a transformer to meet isolation and safety norms, primary and secondary windings must be sepa-
rated by isolation layers, thus their coupling cannot be intimate. Moreover, in a margin w ound construction the
entire window breadth cannot be used (2.5 to 3 mm margin on each side must be considered to achieve suffi-
cient cr eepage distance) thus the win ding becomes shorter and thicker, whi ch hurts coupling. This is w hy triple
insulation construction is recommended.
Figure 4. Interleaved winding technique
As a result, it is not possible to reduce leak age inductanc e below a certain extent. Practic ally, for a well assem-
bled transformer, leakage inductance will be about 1 to 3% of the primary inductance.
Interleaved windings technique (putting on half the primary turns first, then the secondary and finally the other
half of the primary, see fig. 4) may considerably reduce leakage inductance (theoretically almost four times).
The two primary halves must be series connected, never paralleled. Other tricks, such as spacing windings
evenly acr oss a layer (when they do not completely fill it), or using multiple strands of wire, or keeping isolation
between windings to a minimum are also effective. Besides, the use of split bobbins is not recommended.
Primary w inding ca pacitance i s the major componen t of the C
drain
capacitance ear lier mentioned. B esi des con-
tributing to internal MOSFET power loss es, it causes ringing and noise problems that may force the use of ad-
ditional damping networks to comply with EMC requirements.
To achieve a low capacitance, always wind first the primary winding and, in particular, the half whose end is to
be connected to the drain of the MOSFET. In this way the second half primary has a shielding effect that reduces
the capacitive coupling. In case of multiple layer windings, which exhibit higher capacitance, it is useful to embed
one layer of isolation between two adjacent winding layers. This, however, tends to increase leakage inductance
and therefore should be done with care.
Ptot PFe Rp IpRMS
2Rs IsRMS
2
⋅+⋅+=
T∆Ptot Rth
⋅=
1/2 primar
y
turns
1/2 primar
y
turns
secondar
y
turns
air
g
ap on
centre le
g
AN1262 APP LICATION NO TE
16/42
10 CLAMP CIRCUIT DE SIGN
The dr ain pin of the IC needs to be properly c lamped to pr event the spik e due to the transfor mer leakage i nduc-
tance from exceeding the breakdown voltage (700V minimum). An RCD clamp (s ee fig. 5a) is a popular cheap
solution, however it dissipates power even under no-load conditions: there is at least the reflected voltage V
R
across the clamp resistor at all times. If minimizing the light load losses is a must, the use of a zener or transil
clamp (s ee fig. 5b) is recommended whenever possible. Such circuit gives also a better defined clamping level
but dissipates more power at full load.
Figure 5. Suggested clamp circuit topologies
The clamp may not be necessar y in a 110V
AC
operated c onverter but, before giv ing up this circui t, it is important
to check carefully the spike under overload and start-up conditions to make sure that the voltage rating of the
MOSFET is never exceeded.
RCD
clamp
. The clamp capacitor is charged by the energy stored in the leakage inductance and must ensure
that the maximum allowed overvoltage V
spike
is never exceeded, even under short circuit conditions (when the
peak primary current is I
lim
= 0.7 A). Its minimum value will be then:
The capacitor must be l ow-loss type ( with polypr opy lene or polys tyrene film di electr ic) to r educe power dis sipa-
tion and prevent overheating due to the high peak currents it experiences.
The minimum value of the clamp resistance is:
,
a
)
RC
D
RCD CLAMP
L6590
L6590D
L6590A
Drain
GND
b
)
D
ZENER
CLAMP
DZ
Drain
GND
L6590
L6590D
L6590A
Cmin LLK Ilim
2
⋅
VRVspike
+()
2
V
R
2
–
----------------------------------------------------=
Rmin 1
fsw Cmin 1Vspike
VR
----------------+
ln⋅⋅
-------------------------------------------------------------------=
17/42
AN1262 APPLICATION NOTE
and its power rating has to be:
Usuall y the resistor value w ill be selected much higher than the minimum to reduce losses. The clamp cap acitor
will then be quite larger than the minimum as well.
The blocking diode must be not only very fast-recov ery but also very fast-turn-on type to avoid additional drain
overvoltage. A 1A rated diode with a breakdown voltage at least V
PKmax
+ V
R
is needed. Table 12 shows the
suggested ST parts.
Table 12. Recommen ded ST parts for blockin g diode.
Zener clamp.
The Transil (or zener) clamp voltage should be equal to:
V
CL
= V
R
+ V
spike
(16)
Usually Transils are rated by their stand-off Voltage V
RM
at 25°C temperature, which is defined at low current,
whereas the desired clamp voltage is to be considered at operating junction temperature and I
lim
current.
To take this into consideration, as a rule of thumb the stand-off voltage can be selected as high as 70% of the
desired clamp level. Please refer to [2] and [3] to see how these problems are handled.
The Transil or zener must have an adequate power handling capability in steady state operation:
.
Table 13 lists some recommended devices available from ST .
The same recommendation s as in the RCD c lamp c ase a pply to the blocking diode in series to the Transil . Onl y
the breakdown voltage could be derated to V
PKmax
.
Table 13. Recommen ded ST parts for clamping .
110 VAC 220 VAC or WRM
Diode VRRM Package Diode VRRM Package
BYT01-400 400 F126 STTA106 600 F126
SMBYT01-400 400 SMB STTA106U 600 SMB
VRPz ≤ 0.75 W Pz = 1W Pz = 1.5W
≤100 V BZW04-154
BZW06-154
SMAJ154A-TR
BZW04-154
BZW06-154
SMBJ154A-TR
P6KE180A
1.5KE180A
SMCJ154A-TR
130 V BZW04-188
BZW06-188
SMAJ188A-TR
BZW04-188
BZW06-188
SMBJ188A-TR
P6KE200A
1.5KE200A
SMCJ188A-TR
PRVR
2
Rmin
------------ 1
2
--- LLK Ilim
2fsw
⋅⋅⋅+=
P
Z1
2
--- VCL
VCL VR
–
------------------------ LLK Ilim
2fsw
⋅⋅⋅⋅=
AN1262 APP LICATION NO TE
18/42
11 SECONDARY RECTIFIER SELECT ION
Although the converter is operated in DCM, it is recommended to use an ultrafast p-n diode or, whenever al-
lowed by the reverse voltage, a Schottky type. The latter, besides optimizing the reverse recovery , minimizes
conduction losses as well.
The voltage rating will be higher than the maximum reverse voltage it experiences:
, (17)
with a suitable safety margin (us ually 20-25%). As to its current rating, it is a common design practice to choose
a diode r ated for 2- 3 tim es the DC output c urrent I
out
. Table 14 lists some r ecomm ended devi ces a vailabl e fr om
ST assuming V
R
= 130 V. In each cell of the table there are two recommended devices, the first one is an axial
or through-ho le diode and the second one is in SMD pack age. The sal e types in italic are p-n diodes, the others
are Schottky type.
Table 14. Recommen ded ST parts for second ary recti fication.
12 OUTPUT CAPACITOR SELEC TION AND PO ST FILTER
Large, low-E SR electrolytic capacitors usually do the filtering work. The parameters to be considered for their
selection ar e the wor king volt age, RMS ripple rating and ESR, the actual cap acitance v alue is of sec ondar y im-
portanc e.
Obviousl y, the D C working vol tage must be greater than V
out
. A margin of 25% is recommended for the s ake of
reli ability .
The AC current the output capacitor undergoes causes power dissipation on its ESR and a resulting tempera-
ture rise. This is the major res ponsible for capacitor degr ading. Thus it is important not to operate the capacitor
beyond its AC current rippl e rating, otherwise its lifeti me will be consider ably shortened. This parameter is usu-
ally specified at 85°C or 105°C ambient temperature, depending on capacitor's quality. The value could be de-
rated considering the actual maximum ambient temperature (T
amb
) and the capacitor's target lifetime. For a
conservative design no derating will be applied. The AC current capability must then be larger than Is
AC
and
110 VAC 220 VAC or WRM
Vout
(V) Pout≤5W Pout=7.5W Pout=10W Pout≤5W Pout=7.5W Pout=10W
3.3 1N5820
STPS5L25B STPS5L25B-1
STPS5L25B STPS10L25D
STPS10L25G 1N58210
STPS3L25S STPS5L25B-1
STPS5L25B STPS10L25D
STPS10L25G
5 1N5820
STPS5L25B 1N5820
STPS5L25B STPS10L25D
STPS10L25G 1N5821
STPS340C 1N5822
STPS340B STPS640CT
STPS640CB
9 1N5821
STPS2L30A 1N5821
STPS340B 1N5822
STPS340B –
STPS160U –
STPS3L60S STPS5H100-1
STPS3L60S
12 1N5819
STPS1L40A 1N5822
STPS3L60S –
STPS3L60S –
STPS1H100U –
STPS2H100U STPS5H100B-1
STPS2H100U
15 BYV10-60
STPS160A BYV10-60
STPS160A –
STPS3L60S –
STPS1H100U –
STPS2H100U STPS5H100B-1
STPS2H100U
18 BYV10-60
STPS160A BYV10-60
STPS1H100U
BYW98-100
STPS2H100U –
STPS1H100U –
STPS2H100U STPS5H100B-1
STPS2H100U
24 BAT49
STPS1H100A –
STPS1H100U –
STPS1H100U
BYW100-200
STPR120A BYW100-200
STPR120A BYW100-200
SMBYW02-200
VREV Vout 1VPKmax
VR
--------------------+
⋅=
19/42
AN1262 APPLICATION NOTE
may be achieved by using paralleled capacitors.
ESR, b esides being res ponsible for capacitor heating, is what basical ly det ermines the switching frequency volt-
age ripple superimposed on top of the DC value. T his is true as long as the capacitive contribution to the ripple
is negligible, that is if:
(18)
The specification on the maximum allowed output ripple is then translated into a requirement on the maximum
ESR of the capacitor:
(19)
Anyway, once the specification on either the AC ripple current or the ESR is fulfilled, the resulting capacitance
value definitely meets condition (18).
If the requirement on ESR is very tight, there is an alternative to using a large number of output capacitors: it is
possible to toler ate a higher ripple on C
out
(provi ded the AC ripple requi rement is met) and add an LC post filter,
like the one shown in fig. 6, that attenuates the ripple to the desired level.
Figure 6. Output post filter for ripple reduction
The attenuation factor of such filter is approximately given by:
which is the same for complementary duty cycles and minimum for D=0.5. Thus, to get the desired attenuation
factor the following design equations can be applied:
It is conveni ent t o choose an off-the-shelf ch oke and then selec t a capacitor with an ESR low enough to get the
desired attenuation level. For low output current (less than 1 A) ferrite beads may be used. At any rate, the DC
current rating of the choke should be oversized to minimize DC voltage drop. In fact, the feedback should be
connected upstream the post filter to avoid stability problems (s ee "Control loop compensation" section).
Cout >>100 Iout Dx
⋅
Vr% Vout fsw
⋅⋅
--------------------------------------⋅
ESRx Vr%
100
---------- Vout
Ispk
-----------
⋅=
L
Cout C'
ESR ESR'
∆Vo ∆Vout
Post filter
Ka Voutpp
–
∆
∆V
Op p
–
----------------------- D1D–()
ESR'
fsw L⋅
---------------⋅⋅≈=
Ka ESR'
4f
sw L⋅⋅
----------------------- for Dx > 0.5=Ka Dx 1 Dx–()
ESR'
fsw L⋅
--------------- for Dx < 0.5⋅⋅=
AN1262 APP LICATION NO TE
20/42
13 SELF-SUPPLY CIRCUIT DESIGN
To define the self-supply circuit it is necessary to select the bias rectifier and the supply capacitor (see fig. 7)
since the turns number of the auxiliary winding has been defined already.
The bias rectifier has to withstand a reverse voltage equal to:
with an appropriate safety margin of 20-25%. The current rating is of little concern since the diode has to carry
few mA. A popular 1N 4148 (75V rating) or an UF4003 (200V rating) may be suitable choices.
The supply capacitor has to be l arge enough to k eep the device r unning during the tim e needed for the auxil iary
winding to develop its correct voltage at start-up. A minimum value of 10 µF is recommended and any low cost
electr olyti c ca pacitor w ill do the job. The r esis tor Rs in series to D filters the voltage spik e appearing on the pos-
it ive-going edge of the voltage gener ated by the self- supply winding that causes the v oltage Vcc to inc rease with
the conver ter's output load. The optimum value depends on the transformer's stray para meters (mainly the cou-
pling between the aux iliary and th e sec ondar y winding) and c an be found em piricall y onc e the tr ansformer s pec
and construction have been frozen. A small and inexpensive axial inductor in the range of 1 to 10
µ
H may be
used instead of R
S
, with even better results.
Figure 7. Self-supply circuit
14 BROWNOUT PROTECTION DESIGN (L6590A AND L6590D ONL Y)
With reference to the schematic of fig. 8, the following relationships can be established for the ON (V
inON
) and
OFF (V
inOFF
) thresholds of the input voltage:
.
Solving for R 1 and R2:
For a proper operation of this function, V
inON
must be less than V
PKmin
and V
inOFF
less than V
inmin
(see the
timing diagram of figure 8).
VREV VCC 1VPKmax
VR
--------------------+
⋅=
L6590
L6590D
L6590A
Vcc D
CNaux
Rs
VinON R2
R1 R2+
----------------------
⋅2.5,=
VinOFF 2.5–
R1
--------------------------------- 50 10 6
–
⋅+2.5
R2
--------=
R1 VinON VinOFF
–
50 10 6
–
⋅
----------------------------------------=
R2 R1 2.5
VinON 2.5–
------------------------------⋅=
21/42
AN1262 APPLICATION NOTE
Figu re 8. Brownout prot ect io n ci rcui t and t i m in g dia gram
15 CONTROL LOOP DESIGN
The control loop can be summarized as show n in figure 9, where each block is described by it s transfer function
in the complex frequency domain represented by means of a Bode plot.
Figu re 9 . Control loop Block Diagram
The set PWM modulator + Power stage is w hat, in control theory terminology, is called the "plant", while the
compensated error amplifier is the "controller".
+
-
L6590A
L6590D
2.5 V
VinOK
50
µ
A
Vin
6.4 V
R1
R2
Vcc
Vin VPKmin
Vinmin
VinOFF
VinON
VinOK
Vcc
PWM
Vout
OUTPUT
DIVIDER
+
-
Vref Vo
COMPENSATED
ERROR AMPLI FIER VCOMP PWM MODULATOR POWER STAGE
G2
(j
ω
)
Vin
D
G1
(j
ω
)
AN1262 APP LICATION NO TE
22/42
The transfer function G2(j
ω
) of the plant is defined by the control method (voltage mode), the topology of the
conver ter (flyback) and its operati ng mode (DCM in the specifi c case). The task of the control l oop design is then
to determine the transfer function G 1(j
ω
) of the error amplifier and define the relevant frequency compens ation
network. T he objective of the design is to ensure that the resulting closed-loop system will be stable and well
performing in terms of dynamic response, line and load regulation.
The chara cteristic s of the cl osed-loop sy stem can be i nfer red from it s open-loop proper ties . Provided the open-
loop gain crosses the 0 dB axis only once at f= f
c
(crossover frequency), stability will be ensured if the gain phase
shift (besides the 180° due to negative feedback) is less than 180° at f = f
c
. This is the well-know n Nyquist's
stability criterion.
Anyway, adequate margin to this boundary condition must be provided to prevent instability due to parameter
variations and to optimize the dynamic response that would be severely underdamped otherwise. Under worst
case condition this "phase margin"
Φ
m
should never go below 20 or 30°. Typically,
Φ
m
= 45° in nominal condi-
tions is used as a design guideline: this ensures fast transient response with very little ringing. Sometimes a
higher margin (up to 60° or 75°) is required to account for very large spreads in line, load and temperature
changes as well as manufacturing tolerances.
Although Nyquist's criterion allows the phase shift to be over 180° at a frequency below f
c
, this is not recom-
men ded because it would result in a conditionally stabl e sy stem. A reduction of th e gain ( which may tempor aril y
happen during large load transients) would cause the system to oscillate, therefore the phase shift should not
get close to 180° at any frequency below f
c
.
Optimum dynam ic performance require s a large gain bandwi dth, that is the crossover fr equency f
c
to be pushed
as high as possible (
≤
f
sw
/4). When optimum dynamic performance is not a concern, f
c
will be typically chosen
equal to f
sw
/10.
Good load and line regulation implies a high DC gain, thus the open loop gain should have a pole at the origin.
In this way the theoretical DC gain would tend to infinity, whereas the real-world one will be limited by the low-
frequency gain of the Error Amplifier. Since voltage mode control has poor open-loop line regulation, the overall
gain should be still high also at frequenc ies around 100-120 Hz to maximize rejection of the input voltage ripple.
This is related to phase margin: a higher phase margin leads to a lower low-frequency gain.
Once the goal of the design has been established in terms of crossover frequency and phase margin, the next
step is to determine the transfer function of the plant G2(j
ω
) in order to sel ect an appropriate structure for G1(j
ω
).
The transfer function G 2(j
ω
) of the plant is descr ibed in Tab. 15, while its asymptotic Bode plot is illustrated in
Fig.10.
In G2
0
definition the r ati o D
max
/Vs i s the PWM modulator gain, while D
max
= 0 .7 is the maximum duty cycl e and
V
s
= (3.5-1.5) = 2 V is the oscillator peak-t o-val ley sw ing (see the relevant section). R
out
= V
out
/I
out
is the equiv-
alent load resistor.
This kind of plant will be stabilized in closed-loop operation by what is commonly known as a Type 2 amplifier.
Its transfer function G1(j
ω
), which comprises a pole at the origin and a zero-pole pair, is defined as:
Its asymptotic Bode plot is illustrated in Fig. 11.
The main task of this correction is to boost the phase of the overall loop (actually, to reduce the phase lag of
G2(j
ω
)) in the neighborhood of the crossover frequency.
G1 jω() G10
jω
----------- 1jω
ωZ
-------+
1jω
ωP
-------+
-----------------
⋅=
23/42
AN1262 APPLICATION NOTE
Figure 10. Plant transfer function G2(jω) of DCM Flyback (Bode Plots)
Table 15. Plant Transfer Func tion and its Main Quantities
Figu re 11. Cont rol l er Transf er Func ti on G1( jω) (Bode Plots)
Symbol Definition
G2(jω)
G20
fESR
fout
Gain
[dB] Phase
[°]
Gain
Phase 0
-90
0fout
G20
fESR
G2 jω() G20
1jω
ωESR
--------------+
1jω
ωout
-----------+
------------------------
⋅=
G20Dmax
Vs
-------------- Vin Rout
2Lpf
sw
⋅⋅
---------------------------⋅⋅=
f
ESR ωESR
2π⋅
--------------= 1
2πESR Cout
⋅⋅ ⋅
---------------------------------------------=
fout ωout
2π⋅
----------- 1
πRout Cout
⋅⋅
------------------------------------==
Gain
[dB] Phase
[°]
Gain
Phase
0
-90
0f
fZfP
AN1262 APP LICATION NO TE
24/42
The synthesis of G1 (j
ω
) can be done by following the following step-by-step procedure:
a) Calculate gain and phase of G2(j
ω
) at the desired crossover frequency (f
c
). That is :
;
G2(j
ω
) will be calculated at maximum input voltage and maximum load, w here the gain-bandwidth product is
maximum.
b) Calculate gain and phase of G1(j
ω
) at f = f
c
in order for the overall open-loop gain to cross the 0 dB axis at
f = f
c
with the phase margin
Φ
m
:
;
,
c) Cancel the pole of G2(j
ω
) by placing the zero of G1(j
ω
) in the neighborhood:
(
α
= 1 to 5)
d) Place the pole of G1(j
ω
) so as to get the desired phase margin:
,
e) Calculate the unity gain frequency G1
0
:
The synth esis of G1(j
ω
) is compl eted. The following step will concern the practical impl ementation of such func-
tion, that is the re alizati on of a Type 2 a mplifier. This will be done considering two cases , the s econdary and the
primary sensing feedback.
16 SECONDAR Y FEEDBACK IMPLEMENTAT ION
This ki nd of feedbac k, shown in fig. 12 , uses a popular arrangement wi th a TL431 as sec ondary refer ence/err or
amplifier and an optocoupler to transfer the control signal to the primary side. The error amplifier of the IC is
then used as a current source whose characteristic is shown in fig. 12 as well: the voltage V
COMP
is changed
(and the duty cycle is controlled) by modulatin g the current Ic s unk from the pin. A change of Ic c auses a change
of V
COMP
corresponding to a resistance R
COMP
= 9 k
Ω
. The resulting transfer function is:
and table 16 shows how its quantities are defined
G2cG2 2 πfc
⋅⋅()=
Φ2
c
180
π
---------- G2 2 πfc
⋅⋅()[]arg⋅=
G1cG1 2 πfc
⋅⋅()
1
G2c
-----------==
Φ1
c
180
π
---------- G1 2 πfc
⋅⋅()[]arg⋅180–ΦmΦ2c
–+==
f
Z
ω
Z
2π⋅
----------- αωout
2π⋅
-----------
⋅==
f
P
ω
P
2π⋅
-----------= fC
π
180
---------- Φ1c
⋅
tan
-------------------------------------------
≈
G102πG1cfcfZ
⋅
fP
-------------⋅⋅ ⋅≈
G1 jω() V
COMP
∆Vout
∆
----------------------- VCOMP
∆IC
∆
----------------------- IC
∆IF
∆
-------- IF
∆VK
∆
----------- VK
∆Vout
∆
---------------⋅⋅ ⋅ CTRmax RCOMP
⋅
RBRHCF
⋅⋅
----------------------------------------------- 1
jω
----- 1jωR
HR
F
+()C
F
⋅⋅+
1jωR
COMP CCOMP
⋅⋅+
----------------------------------------------------------------⋅⋅== =
25/42
AN1262 APPLICATION NOTE
Figure 12. Secondary feedback: TL431 + optocoupler circuit (I)
Table 16. G1(jω) I mp lemen tation: seco ndary feedb ack (I)
This technique provides very good regulation of the output voltage and galvanic isolation from the primary side
at the same time.
In Table 16 it is possible to find the design relationships useful to derive the part values. Icmax is specified in
the Datasheet (2.5mA).
The following condition should be met:
, (20)
otherwise t wi ll not be possible to find a positive val ue for R
F
. If the condition (20) is not met, an optocoupl er with
a narrower CTR
min
- CTR
max
spread should be selected. If that is not possible, either a higher f
c
or a lower
Φ
m
should be selected and the calculations from step a) to step e) redone.
Symbol Definition
RLRL ≈ 0.27 to 2.7 [kΩ]
RH
RB
CF
RF
CCOMP
Vout
RBRH
RL
TL431
CF
L6590
L6590D
L6590A
COMP
VK
IF
IC
CCOMP
IC
VCOMP
1.5
3.5
RCOMP = ∆VCOMP
∆IC
1 mA
VFB
Not needed
in the L6590A
RF
RHVout 2.5–
2.5
------------------------- RL
⋅=
RBCTRmin Vout 3.5–
ICmax
-------------------------⋅<
CFCTRmax RCOMP
⋅
RBRHG10
⋅⋅
-----------------------------------------------=
RF1
2πfZCF
⋅⋅ ⋅
-------------------------------- RH
–=
CCOMP 1
2πfPRCOMP
⋅⋅ ⋅
---------------------------------------------=
CTRmax
CTRmin
----------------------- G1c
π
180
---------- Φ1c
⋅
tan
RCOMP
------------------------------------------- Vout 3.5–
ICmax
-------------------------⋅⋅≤
AN1262 APP LICATION NO TE
26/42
Figure 13. PWM gain reduction by RC (seconda ry feedb ack II).
A resisto r R
C
in parallel to C
COMP
, as shown in fig. 13, is useful to reduce the PW M gain
∆
V
COMP
/
∆
I
C
. In fact,
the resistor come s dynami cally in par allel to R
COMP
, t hus reducing the equival ent value appeari ng at the numer-
ator of the gain. Moreover, since it diverts part of the current sourced by the pin COMP, the opto's transistor
carries less current and a slightly higher bias resistor R
B
can be used, thus giving some extra gain reduction.
An additional resistor, R
B1
, of some k
Ω
could be needed to guarantee sufficient bias to the TL431.
To be able to exploit the full dynamics of the error amplifier under worst case conditions, R
C
must not be lower
than 7 k
Ω
, which reduces the gain by a 1/0.35
≅
2.86 factor. R
C
values low er than 7 k
Ω
will reduce the gain
further on but will reduce also the maximum duty cycle allowed (worst case). Depending on the maximum duty
cycle specified for a given application, this can be acceptable.
Table 17 summarizes the situation for different values of R
C
.
Table 17. PW M gain reduction for different RC values
In this case the design procedure outlined in table 16 should be slightly modified as shown in table 18.
RC (kΩ)R
C
// RCOMP (kΩ)Dmax PWM Gain
Reduction KB
(RB multiplier) Total Gain
Reduction
7.5 4.09 0.7 2.2 1.24 2.73
7 3.94 0.7 2.29 1.25 2.86
6.8 3.87 0.68 2.32 1.25 2.91
6.2 3.67 0.62 2.45 1.27 3.11
5.6 3.45 0.55 2.61 1.28 3.34
5.1 3.26 0.49 2.76 1.29 3.58
4.7 3.09 0.44 2.91 1.31 3.8
4.3 2.91 0.38 3.09 1.32 4.07
3.9 2.72 0.32 3.31 1.33 4.4
3.6 2.57 0.28 3.5 1.34 4.69
Vout
RBRH
RL
TL431
CF
L6590
L6590D
L6590A
COMP
VK
IF
IC
CCOMP
VFB
No t needed
in th e L6590A
RF
RC
RB1
27/42
AN1262 APPLICATION NOTE
Table 18. G1(jω) I mp lemen tation: seco ndary feedb ack (II)
More flex ibility is giv en by the network illustr ated in figure 14, applicable with the L6590 and L6590D which have
the error amplifier on board.
For this circuit, to be able to find a positive value for R
F
, the condition is:
,
which is less stringent than (20). The resulting function is:
,
and Table 19 shows how its quantities are defined.
Figure 14. Secondary feedback: TL431 + optocoupler circuit (III)
Symbol Definition
RLRL ≈ 0.27 to 2.7 [kΩ]
RH
RC, KBSelect from table 17
RB
CF
RF
CCOMP
RHVout 2.5–
2.5
------------------------- RL
⋅=
RBCTRmin Vout 3.5–
ICmax
------------------------- KB
⋅⋅<
C
F
CTRmax RCOMP// RC
()⋅
R
B
R
H
G10
⋅⋅
-----------------------------------------------------------------=
RF1
2πfZCF
⋅⋅ ⋅
-------------------------------- RH
–=
CCOMP 1
2πfPRCOMP// RC
()⋅⋅ ⋅
---------------------------------------------------------------=
CTRmax
CTRmin
----------------------- G1c
π
180
---------- Φ1c
⋅
tan
RF2
------------------------------------------- 1RC
RE
-------+
V
out 3.5–
ICmax
-------------------------⋅⋅⋅≤
G1 jω() V
COMP
∆Vout
∆
----------------------- VCOMP
∆VE
∆
----------------------- VE
∆IC
∆
-----------
⋅=IC
∆IF
∆
-------- IF
∆VK
∆
----------- VK
∆Vout
∆
---------------
⋅⋅ ⋅ CTRmax RERF2
⋅⋅
R
E
R
C
+() · RBRHCF1
⋅⋅
-------------------------------------------------------------------- 1
jω
----- 1jωR
HR
F1
+()C
F1
⋅⋅+
1jωR
F2 CF2
⋅⋅+
----------------------------------------------------------------
⋅⋅==
Vout
RB
RH
RL
TL431
CF1
L6590
L6590D
Vcc
VK
COMP
VFB
RE
RC
RF2
CF2
IF
IC
VE
RF1
AN1262 APP LICATION NO TE
28/42
Table 19. G1(jω) I mp lemen tation: seco ndary feedb ack (III)
Figu re 15 shows a special c onfiguration, with the optocou pler connected in ser ies to the supply pin of the IC that
provides the following benefits:
a) a large range of the voltage generated by the auxiliary winding can be allowed since the changes are
"damped" by the phototransistor and V cc is stabilized by the error amplifier; this is useful with a poor quality
transformer or when the output voltage (tracke d by the auxiliary voltage ) may decrease because of constant
current regulation (e.g. battery chargers, see fig.40 on L6590’s datasheet).
b) during overload and short ci rcuit the power throughput is automati cally reduced because the operation of the
device becomes intermittent. In fact, the phototransistor carries the quiescent current I
Q
of the IC and, if the
output voltage is too low, there will not be enough current through the photodiode at the secondary side to
maintain I
Q
. The device will be switched off as it goes into UVLO.
c) despite the IC's OVP protection is bypassed by such configuration, the system is still protected against op-
tocoupler's failures: if that happens, the phototransistor will no longer be able to supply the IC, which will go
into UVLO just like in case of overload or short circuit.
The transfer function of the schematic of Fig. 15 is:
The V
CC
capacitor has a significant effect on the frequency characteristic of this circuit: in particular, it introduces
a low-frequenc y pole that c auses a phase l ag noxious for the phase mar gin. This pole needs to be compe nsated
by a zero, which requires an additional resistor (R
C
) in series to the capacitor.
The zero (R
H1
+ R
F1
) · C
F1
will be plac ed clo se to t he pole due to the V
CC
capacitor , (R
H2
+R
C
)·C
S
so as t o com-
pensate it. The pole at the origin and the other zero-pole pair r ealize a type 2 amplifier (see Table 20 to see how
Symbol Definition
RF2; RC ;
RERE > 1kΩ
RLRL ≈ 0.27 to 2.7 [kΩ]
RH
RB
CF1
RF1
CF2
RF2 2kΩ> RC2.5 RF2
⋅<
RHVout 2.5–
2.5
------------------------- RL
⋅=
RBCTRmin Vout 3.5–
2.5
------------------------- RE
⋅⋅<
C
F1 CTRmax RERF2
⋅⋅
R
E
R
C
+() · RBRHG10
⋅⋅
--------------------------------------------------------------------=
RF1 1
2πfZCF1
⋅⋅ ⋅
----------------------------------- RH
–=
CF2 1
2πfPRF2
⋅⋅ ⋅
-----------------------------------=
G1 jω() V
COMP
∆Vout
∆
----------------------- VCOMP
∆VCC
∆
----------------------- VCC
∆IC
∆
--------------- IC
∆IF
∆
-------- IF
∆VK
∆
----------- VK
∆Vout
∆
--------------- =⋅⋅⋅⋅==
= CTRmax RF2
RB
---------- 1
jωRH1 CF1
⋅⋅
------------------------------------ 1jωR
cC
s
⋅⋅+()1j+ωR
H1 RF1
+()C
F1
⋅⋅[]⋅
1j+ωR
H2 Rc
+()C
s
⋅⋅[]1j+ωR
F2 CF2
⋅⋅()⋅
------------------------------------------------------------------------------------------------------------------------ .⋅⋅ ⋅
29/42
AN1262 APPLICATION NOTE
Figure 15. Secondary feedback: TL431 + optocoupler circuit (IV)
Table 20. G1(jω) I mp lemen tation: seco ndary feedb ack (IV)
this netw ork can be designed). The bias resist or of the photodiode will be selected s o as to sus tain the quies cent
current of the L6590 and the cur rent through the div ider R
H2
+R
L2
. Pl ease note that the steady state s upply volt-
age Vcc (us ed in table 20 to c hoose R
L2
and R
H2
) has to be sufficiently higher than the UVLO threshold ( say 3-
4 V, depending on C
S
). In fact, the PWM starts only when the Vcc vol tage has decayed from the start-up thresh-
old to the neighborhood of the steady state value. During this time the PWM is inhibited by the error amplifier,
saturated low because the voltage at the pin V
FB
is higher than 2.5V.
The turn number of the auxiliary winding will be such that the V
CE
across the phototransistor never falls below
1-2 V, to let it work in its active region. In case of constant current regulation, the variation of the output voltage
Symbol Definition
RL2; RH2 ;
RF2 RF2 > 0.4 · RH2
RL1 RL1 ≈ 0.27 to 2.7 [kΩ];
RB
RC
CF1
RF1
CF2
L6590
L6590D
Vcc
Naux
RH2
RL2
RF2
VFB
COMP
CF2
Rc
IC
470 nF
Cs
TL431
Vout
RB
RH1
RL1
CF1
VK
IF
RF1
RL2 15V
VCC
----------- kΩ[]> R
H2 VCC 2.5–
2.5
------------------------- RL2
⋅=
RH1 Vout 2.5–
2.5
------------------------- RL1
⋅=
RBCTRmin Vout 3.5–
IQ2.5
RL2
----------+
-------------------------
⋅<
RC1
2πfZCS
⋅⋅ ⋅
--------------------------------=
CF1 CTRmax R⋅F2
RBRH1 G10
⋅⋅
--------------------------------------=
RF1 RH2 RC
+()C
S
⋅
C
F1
------------------------------------------ RH1
–=
CF2 1
2πRF2 fP
⋅⋅ ⋅
-----------------------------------=
AN1262 APP LICATION NO TE
30/42
must be a ccounted for as w ell (t he mini mum spec ified value w ill be c onsidered) and the turn num ber may result
quite high.
17 PRIMARY FEEDBACK IMPLEMENTATION
In this approach, which will be considered with regards to the L6590 and the L6590D only, the voltage generated
by the self-supply winding is sensed and regulated. This solution, shown in fig. 16, is cheap because no opto-
coupler is needed, but provides poor regulation, especially as a result of load changes.
Ideally, the voltage generated by the self supply winding and the output voltage should be related by the N
aux
/
Ns turn ratio only. Actually, numerous non-idealities, mainly transformer's parasitics, cause the actual ratio to
deviate fr om the ideal one . Line regulation is quite good, in the range of ± 2%, whereas load r egulation i s about
±5%. Output voltage tolerance is instead in the range of ±10%. The resulting transfer function is:
Table 21 shows how its quantities are defined. As to the selection of Vcc, the same considerations concerning
the circuit of fig. 15 apply to the circ uit in fig. 16a. Such limitation is not in the circuit of fig. 16b.
Figure 16. Primary fe edback: cir cuits
Table 21. G1(jω) Implementation: Primary Feedback
The value of the resistor Rs (R’s for the circuit of fig. 16b) in series to the bias diode will be selected to achieve
minimum load regulation and its value may range from few units to some hundred ohm.
Symbol Definition
RL
RH
CFp
CFs
RF
G1 jω() V
COMP
∆Vout
∆
----------------------- Naux
NS
------------ VCOMP
∆VCC
∆
-----------------------⋅=Naux
NS
------------ 1
RHCFs CFp
+()⋅
-------------------------------------------- 1
jω
----- 1j+ωR
FC
Fs
⋅⋅
1j+ωR
FC
Fs CFp
⋅
CFs CFp
+
---------------------------
⋅⋅
----------------------------------------------------------- .⋅⋅⋅==
a
)
b
)
L6590
L6590D
Vcc
Naux
RH
RL
RF
CFs
Rs
VFB
COMP
CFp
22 µF L6590
L6590D
Vcc
Naux
RH
RL
RF
CFs
R's
VFB
COMP
CFp
Rs
22 µF220 nF
RL15V
VCC
----------- kΩ[]>
R
HV
CC 2.5–
2.5
------------------------- RL
⋅=
CFp Naux
NS
------------ fZ
fP
----- 1
G10RH
⋅
-----------------------
⋅⋅=
C
Fs CFp fP
fZ
----- 1–
⋅=
R
F1
2πf
Z
C
Fs
⋅⋅ ⋅
-----------------------------------=
31/42
AN1262 APPLICATION NOTE
The optimum value w ill be found empirically once the transformer construc tion has been frozen. Also the di vider
R
H
, R
L
that sets the V
CC
voltage (and as a consequence, the output voltage) is likely to need adjustment after
bench verification. Some improvement in terms of load regulation can be achieved by using an inductor (typi-
cally, betw een 1 and 10
µ
H) instead of a re sistor. A ny inexpens ive axial inductor able to carr y few mA will serve
the purpose.
Figure 17. Leading Edge Blanking (LEB) circuit for leakage inductance spikes filtering
However , the most effective way to improve regulati on is to use the circuit shown in figure 17, which blanks the
spike appear ing at the leadi ng edges of the voltage gener ated by the sel f-supply winding. This spik e, due to the
transformer's leakage inductance, is the major responsible for the poor load regulation.
18 LAYOUT RECOMMEN DATIONS
A proper printed circuit board (PCB) layout is essential for correct operation of any switch-mode converter and
this i s tr ue for the devices of the L6590 family as wel l. Car eful c omponent pl acing, corr ect t races r outi ng, appro-
priate traces widths and compliance with isolation distances are the major issues.
Figure 18. Suggested gro und rou ting for converters wi th second ary feedb ack.
Vcc
GND
L6590
L6590D
L6590A
1N4148
BC327
10 kΩ
100 pF 22 µF
Iout [A]
Vout [V]
0.01 0.1 1
11
12
13
14
15
16
17
18 Rs
LEB
Vin Vout
L6590
L6590D
L6590A
DRAIN
GND
COMP
Vcc
Vac
VFB
Primar
y
Power GND
Secondar
y
Si
g
nal GND
Primar
y
Si
g
nal GND One-point GND
BOK
Secondar
y
Power GND
L6590A and
L6590D onl
y
L6590 and
L6590D onl
y
C
Y1
AN1262 APP LICATION NO TE
32/42
Some fundamental rules will be given to enable the designer to successfully produce a good layout.
All of traces carrying high currents, especially if pulsed (the bold ones in figures 18 and 19), should be as short
and fat as possible. This w ill keep both resistive and inducti ve effects to a minimum, in favor of effici ency as well
as radiated RFI. If a two layer PCB is used, some of these traces could be routed parallel on both sides.
Noise coupl ing and radiation will also be reduced by minimizing t he area circumscr ibed by curr ent loops where
high pulsed currents flow, that is the bolded ones in figures 18 and 19. The most critical loop is that including
the input bulk capac itor , the transformer and the L6590, thus these components should be next to one other. In
figure 20 an example of possible component placement is given.
Figure 19. Suggested ground routing for converters with primary feedback
Current returns (or ground) routing is also very important. All of them (signal ground, power ground, shielding,
etc.) should be routed separately and should be c onnected only at a single ground point, as suggest ed in f igures
18 and 19.
Generally, traces carrying signal currents should run far from others carrying pulsed currents or with quickly
swingi ng voltages lik e the bolded ones of figures 18 and 19. Fr om this viewpoint, par ticular care s hould be taken
of the feedback path. In case of two layer PCB, it is a good practice to r oute signal traces on one PCB side and
power traces on the other side.
Some cruci al points of the cir cuit need or may need filte ring, such as the V
CC
pin or the BOK pin. In case, high-
frequency filter capacitors (with plastic film or ceramic dielectric) should be placed between these pins and the
"signal ground" route, as close to the IC as possible.
Reduction of common mode emissions requires a Y1 class capacitor (or two series connected Y2 class ones)
connected between the primary and secondary ground. This decoupling capacitor should be connected as close
to the transformer as possible.
Another i mportant poi nt is r elated to creepage distance: thi s must be observed between primar y and sec ondary
ground (8mm), between the phases of the input voltage (4 mm) and the opposite ends of the primary winding
of the transformer (4mm). Concerning the primary-to-secondary ground separation, no component or traces
Vin Vout
L6590
L6590D
DRAIN
GND
Vcc
Vac
VFB
Primary Powe r GND
Primary Signal GN D One-point GND
BOK
Secondary GND
L6590D only
C
Y1
33/42
AN1262 APPLICATION NOTE
must be placed in this region, except the above mentioned common mode suppression capacitor and any op-
tocoupler for secondary feedback.
Filling any unused space in the PCB with a ground plane helps reduce noise emission, but does not exempt
from using the above mentioned care in component placing and traces routing. For instance, if a signal ground
is connected to a ground plane along a pulsed current path between two components, (it is usually the most
direct one) noise will be injected into the signal circuitry.
Figure 20. Possib le compon ent placem e nt.
19 TEST BOARD: DESIGN AND EVALUATION
In order to show how to proceed with the desi gn of an application bas ed on the L6590 family, the design of the
test boar d, used to evaluate the devi ce's performance, will be illus trated in details. Finall y, the resulting electric al
schematic and a bench evaluation of the test board will be presented. The electrical specifications of the test
board and some preliminary choices are listed in table 22. Table 23a) shows the results of some preliminary
calculations needed to go further with the design steps.
Table 22. Test board's electri cal specification and pre-design choices
Electrical Specification
VACmin 88 V Minimum mains voltage
VACmax 264 V Maximum mains voltage
fL60 Hz Mains frequency (@ min. mains)
NH0 Number of holdup cycles
Vout 5 V Regulated output voltage
∆Vout% 2 % Percent output voltage tolerance (±)
Vr% 1 % Percent output voltage ripple
Poutmax 10 W Maximum output power
η0,75 Expected converter efficiency
Tamb 40 ° Maximum ambient temperature
+
to input
brid
g
e
si
g
nal
g
round
+jumper
Transformer
Cin
CY
L6590
L6590D
Csuppl
y
Zener
clamp
AN1262 APP LICATION NO TE
34/42
Bridge rectifier selection.
An integrated bridge (DF06M, 4x1A/600V, GI) has been selected.
Input Bulk Capacitor.
From table 5, in order for the valley vol tage on the input cap to be around 90 V, a minimum capac itance of about
27 µF should be used. A standard 22 µF/400V electrolytic capacitor will be chosen. After few iterations, the (1)
cycle converges at V
inmin
= 84.9V, T
c
= 2.11 ms. From eqn. 2, V
DCmin
= 103.2 V.
Table 23b) shows the results of a second step of calculations, aimed at checking that no limit of the device is
violated. The result is OK.
Operating conditions @ V
in
= V
DCmin
and thermal check.
The results are listed in table 23c). With these data the power dissipated by the L6590 is calculated and the
result is shown in table 23d).
From eqn. 3, the maximum junction-to-ambient thermal resistance needed for reaching thermal balance at Tj =
125 °C is 51.2 °C/W. From the diagrams of fig. 21 it is possi ble to see that this can be obtained with about 1 cm
2
copper area on the P CB.
Figure 21. L6590 Fami ly Packa ges Junctio n-to-A m bient Therm al Resistance
Pre-design Choices
VR120 V Reflected voltage
ηT0,9 Transformer efficiency
Vspike 80 V Leakage inductance overvoltage
VCC 12 V L6590 supply voltage
VF0.6 V Secondary diode forward drop
VBF 3 V
Bridge Rectifier + EMI filter voltage drop
SO16W
Rthja vs. PCB c opper area
Pdiss = 1.4 W
0.511.522.533.544.5
46
48
50
52
54
56
[cm^2]
[°C/W]
1 Oz 2 Oz
MINIDIP
Rthja vs. PCB copper area
Pdi ss = 1.4 W
0.511.522.533.544.5
46
47
48
49
50
51
52
[cm^2]
[°C/W]
1 Oz 2 Oz
Table 22.
(continued)
35/42
AN1262 APPLICATION NOTE
Table 23. Test Board design calculations results.
a) Preliminary Calculations results (step 1)
Symbol Parameter Value
Pin Converter Input Power 13.33 W
Iout DC Output Current 2 A
VPKmin Minimum Peak Input Voltage 121.5 V
VPKmax Maximum Peak Input Voltage 373.4 V
b) Preliminary Calculations results (step 2)
Vinmin Absolute minimum Input DC Voltage 84.9 V
VDCmin Minimum Input DC bus Voltage 103.2 V
PinT Transformer Input Power 12.44 W
VDS(on)x Max. average drop on RDS(on) in ON-
state 7.24 V
DxMaximum Duty Cycle 0.607
VDSmax Maximum drain Voltage in OFF-state 573.4 V
Ippkx Max. Peak Primary Current 0.528 A
c) Operating Conditions @ Vin = VDCmin
VDS(on) Average drop on R DS(on) in ON-state 7.24 V
D Duty Cycle (switch ON-time to switch-
ing period ratio) 0.496
Ippk Peak Primary Current 0.528 A
IpDC DC Primary Current 0.131 A
IpRMS Total RMS Primary Current 0.215 A
IpAC RMS Primary Current (AC component
only) 0 .170 A
D’ Secondary diode conduction time to
switching per iod ratio 0.397
Ispk Peak Secondary Current 10.08 A
IsDC DC Secondary Current 2 A
IsRMS Total RMS Secondary Current 3.67 A
IsAC RMS Secondary Current (AC compo-
nent only) 3.08 A
d) Device power dissipation @ Vin = VDCmin
Pcond Conduction losses 1.29 W
Psw Switching losses 0.13 W
Pcap Capacitive losses 0.16 W
PqQuiescent losses 0.08 W
Ptot Total losses 1.66 W
Rthj-amb Maximum junction-ambient thermal
resistance 51.2 °C/W
AN1262 APP LICATION NO TE
36/42
Flyback transformer design
Eqn. 4 giv es the primary induc tance ( Lp = 1.37 mH, rounded up to 1.4 mH), while eqn. (5) giv es the primary- to-
secondary turns ratio (n = 21.4) . The design will be done considering Philip's E-cor es in 3C85 ferrite and as-
suming a maximum peak flux of 0.25T, a temperature rise of 40 °C and 40% window utilization factor. Going
step-by-step:
1) Eqn. 6 provides a minimum AP of 0.042 cm
4
. Table 10 shows that an E20/10/6 core could fit the design.
2) The primary turns number will be Np
min
= 122.5.
3) The resulting secondary turn number will be 122.5/21.4=5.7 which will rounded up to 6. The primary turns
number will then become 6·21.4=128.4. Finally, the choice will be Np=128 turns and Ns=6 turns, which
yields an actual turns ratio of 128/6 = 21.33, very close to the target.
4) From eqn. 7, the air gap needed to get the desired value of Lp will be 0.63 mm.
5) Table 10 shows that the thermal resistance of the finished core is 46 °C/W, thus the maximum power dissi-
pation inside the transformer shall not exceed 40/46 = 0.87 W.
6) Equations 8, 9 and 10 will pr ovide the actual fl ux swing (which will be lower than 0.25 T becau se Np>Npmin),
the actual core losses and the allow ed copper losses respectively. The resulting flux swing is
∆
B=180 mT:
the relevant core losses amount at 66 mW, thus it is possible to dissipate up to 0.8 W in the windings.
7) The required primary and secondary winding resistance will be 8.65
Ω
and 30 m
Ω
respectively (resulting
from eqns. 11 ). The resul ting pr imary resis tance is quite high and the dr op across it r educes signifi cantly the
actual voltage applied at the primary inductance. The target primary resistance is then reduced at 4
Ω
and
the secondary will be increased at 46m
Ω
to maintain the same total copper losses.
The required primary and secondary copper area will be 2.87·10
-4
cm
2
and 1.2·10
-3
cm
2
respectively (eqns.
12, 13). Table 11 shows that this can be done with one AWG32 wire at th e primar y and four paralleled (twist-
ed) AWG32 wires at the secondary. This will both minimize high frequency effe cts and simplify the BOM. The
total occupied area will be 7 mm
2
(eqn. 14), 20% of the total available area, thus the windings will fit.
On top of the primary and secondary winding, 14 turns of AWG32 wire will be wound to make the auxiliary
winding (eqn. 15).
8) The actual resistance of the primar y and secondary wi ndings will be 3.6
Ω
and 42 m
Ω
respectively, for total
copper losses of 0.73 W. The total losses will be about 0.8 W and the resulting temperature rise 36.8 °C.
Zener clamp
To optimize losses at light load a zener clamp will be used. The clamp voltage should be around 200 V (eqn.
16), thus a BZW06-154 is first selected.
Assuming a leakage inductance of 30 µH (about 2% of the primary inductance), pow er dissipa tion wil l be about
0.6 W in normal operation and about 1.1 W in overcurrent limitation. The relevant clamping voltages would be
196 V and 209 V respectively. The initial choice will then be confirmed.
An STTA106 (1A / 600V turboswitch diode) will be used as the blocking diode.
Secondary rectifier
Accordi ng to e qn. 17, and consi der ing 25% marg in, the blocki ng vol tage of the diode should exceed 2 8 V, whi le
its current rating should be in excess of 4 A. Although table 14 suggests a bigger device, an 1N5822 (3A/40V)
Schottky diode is selected for this test board.
37/42
AN1262 APPLICATION NOTE
Output Capacitor
Capacitor's ripple current rating should exceed 3 A. The minimum capacitance value should be 373 µF (eqn.
18) and the maximum ESR should be less than 5 m
Ω
. For long-time reliability the capacitor(s) should also be
able to withstand at least 3.08 A current ripple. Three R ubycon's ZL series 470 µF/16V paralleled capacitors
were se lected, for a tota l rippl e capability of nearly 3 A and a total ESR of ab out 20 m
Ω
. To meet the requirement
on the output voltage ripple an LC post filter is needed that attenuates ripple at least four times. Choosing a
standard value of L = 4.7 µH, the maximum ESR of the additional capacitor should not exceed 300m
Ω
.
An additional 220 µF/10V ZL capacitor has been added.
Self-supply circuit
The self supply cir cui t will include an 1N4148 di ode and a 22 µF supply capacitor. A 10
Ω
resis tor will be added
in series to the diode to r educe Vcc voltage variations with the load current. This value is likely to be adjusted
after bench verification.
Control loop design
The crossover frequency will be selected as high as 10 kHz, worst case. The objective will be to get 70° phase
margin.
The plant transfer function is:
with G2o = 11.5, f
ESR
= 5464 Hz, f
out
= 90.3 Hz (@ max. load and max. V
in
). A type 2 amplifier will be used for
G1(j
ω
).
Going step-by-step:
a) The gain and phase of G2 at f=10 kHz are 0.281 and -29° respectively;
b) In order for the overal l open- loop gain to c ross the 0 dB axis at f=10 kHz w ith 70° phase m argin, the gai n and
phase of G 1(j
ω
) will be 3.56 and -81° respectively;
c) the compensating zero will be placed at 360 Hz (
α
= 4, to maximize 100H z gain);
d) the compensating pole will be placed at 2270 Hz;
e) the unity gain factor is 35.4·10
4
s/rad.
Since a tight tolerance on the output voltage is required, an optoisolated feedback will be used and G1(j
ω
) will
be r ealized with the schematic of figure 13. The TL431 and an optocoupler PC817A from Sharp will be used.
The CTR is specified between 0.8 and 1.6.
Using a 6.8k
Ω
resistor as R
C
, the resulting part values are:
R
L
= R
H
= 2.43 k
Ω
; R
B
= 560
Ω
; R
F
= 2k
Ω
; C
F
= 100 nF; C
COMP
= 22 nF.
Electrical Schematic, BOM and evaluation results
In fig. 22 the electrical schematic of the test board is illustrated and table 24 lists the relevant BOM. The dia-
grams of figure 23 show the evaluation r esults of the board, figure 24 show s s ome typi cal wavefo rms and figure
25 the effect of the frequency change on the output voltage transient.
G2 jω() G20
1jω
ωESR
--------------+
1jω
ωout
-----------+
------------------------⋅=
AN1262 APP LICATION NO TE
38/42
Figure 22. Test board electrical schematic
Table 24. Test board Bill Of Material
Symbol Value Notes
R1 10 Ω¼ W, 5%
R2 6.8kΩ¼ W, 1%
R3 560Ω ¼ W, 1%
R4, R6 2.43kΩ¼ W, 1%
R5 2kΩ¼ W, 1%
C1 22 µF 400 V, electrolytic, ELNA RE3 or equivalent
C2 22 µF 25 V, elec trolyti c
C3 22 nF plastic film
C4 2.2 nF 250V Y class
C5, C6, C7 470 µF 16 V, electrolytic, RUBYCON ZL or equivalent
C8 220 µF 10 V, electrolytic, RUBYCON ZL or equivalent
C9 100 nF 10V electrolytic
L1 4.7 µH UK ltd., ELC8D4R7E
D1 BZW06-154 154V / 600W peak Transil, ST
31
5
4
6, 7, 8
5 Vdc / 2 A
C2
C4
C8
R3
R4
D1
D3
D4
OP1
L6590
IC1
4
3
1
2
3
C5
R1
C3
R6
L1
T1
D2
C6
BDG
Vinac
88 to 264 V
C9
2
1
IC2
C7
R5
R2
C1
F1
39/42
AN1262 APPLICATION NOTE
Figure 23. Test board evaluation results
Symbol Value Notes
D2 STTA106 1A / 600V Turboswitch, ST
D3 1N4148
D4 1N5822 3A / 40V Schottky, ST
IC1 L6590 Monolithic HV Switcher, ST
OP1 PC817A Optocoupler, Sharp
BD1 DF06M GI, or equivalent 1A, 600 V
T1 ---
Core E20/10/6, 3C85 ferrite, Philips or equivalent
≈ 0.6 mm air gap for a primary inductance of 1.4 mH (LLK <30 µH)
Pri: 64T+64T, series conneceted, AWG32 (∅ 0.22 mm)
Sec: 6T, 4xAWG32 (∅ 0.22 mm)
Aux: 14T, AWG32 (∅ 0.22 mm)
F1 T2A250V 2A, 250V ELU
Test board Load & Line regulation
0.003 0.01 0.03 0.1 0.3 1 3
4.9
4.92
4.94
4.96
4.98
5
Load Current [A]
Output Voltage [V]
264 VAC
88 V AC
110 VAC
220 VAC
T est Board Eff ici ency
0.003 0.01 0.03 0.1 0.3 1 3
20
30
40
50
60
70
80
Load Current [A]
Effici e ncy [% ]
88 VAC
264 VAC
220 VAC
110 VAC
Test Board Li ght- load Consumption
50 100 150 200 250 300 350 400 450
0
200
400
600
800
1,000
DC Input Vol t age [V ]
Input Power [ mW]
Pout
0.5 W
0.25 W
0.1 W
0.05 W
0 W
Device Pow er Dissipation
Rth
j
-am b= 58 °C/ W @ 1.5W
0.003 0.01 0.03 0.1 0.3 1 3
0.05
0.1
0.2
0.5
1
2
5
Load Current [A]
Devi ce Dissi pati o n [W]
88 VAC
110 VAC
264 VAC
220 VAC
Table 24. (continued)
AN1262 APP LICATION NO TE
40/42
Figure 24. Test board main waveforms under different operating conditions
Figure 25. Test board load transient response; effect of frequency change (left).
20 REFERENCES
[1] Lloyd H. Dixon, Jr. "Filter Inductor and Flyback Transformer Design for Switching Power Supplies", UNI-
TRODE Power Supply Design Seminar Manual, 1994 (SEM-1000)
[2]"Calculation of Transil Apparent Dynamic Resistence" (AN575)
[3]"Transistor Protection by Transil" (AN587)
[4]"Getting Familiar with the L6590 Family High-voltage Fully Integrated Power Supply" (AN1261)
A1: Id rai n
Ch1: Vdrain
Vin = 100 V
I out = 2 A
Vin = 100 V
Iout = 50 mA
A1: Id rai n
Ch1: Vdrain
Vin = 400 V
Iout = 2 A
Vin = 400 V
Iout = 50 mA
A1: Idrain
Ch1: Vdrain
A1: Id rai n
Ch1: Vdrain
Vin = 200 V
Iout = 0.2 ↔0.4 A
Vout
Iout
Vin = 200 V
Iout = 0.1 ↔0.3 A
Vout
Iout
transition
22 ⇒65 kHz
transition
65 ⇒22 kHz
41/42
AN1262 APPLICATION NOTE
SUMMARY
1
Flyback Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2
Converter Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3
Pre-design Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4
Preliminary Calculations (step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
5
Bridge rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
6
Input Bulk Capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
7
Preliminary Calculations (step 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
8
Operating Conditions @ V
in
= V
DCmin
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
9
Flyback Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
10
Clamp Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
11
Secondary rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
12
Output Capacitor selection and post filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
13
Self-supply Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
14
Brownout Protection design (L6590A and L6590D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
15
Control loop design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
16
Secondary feedback implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
17
Primary feedback implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
18
Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
19
Test Board: Design and Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
20
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
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by i m pl i cat i on or oth erwi se under any pat ent or pat ent r i ghts of S T M i croelectroni cs. Spec i ficat i ons m ent i oned i n this public at ion are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
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42/42
AN1262 APP LICATION NO TE
