CY7C1380D-167AXCT - Cypress Semiconductor

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

CY7C1380D

CY7C1382D

PRELIMINARY

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05543 Rev. *A Revised October 28, 2004

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Provide high-performance 3-1-1-1 access rate

•User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard lead-free 100-pin TQFP,

119-ball BGA and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36

and 1,048,576 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE1), depth-expansion Chip

Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP

and ADV), Write Enables (BWX, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 2 of 29

Logic Block Diagram – CY7C1380D (512K x 36)

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

0, A1, A

MEMORY

ARRAY

DQs

DQPA

DQPB

DQPC

DQPD

SLEEP

CONTROL

[1:0]

A ,

DQP

BYTE

WRITE REGISTER

B ,

DQP

BYTE

WRITE REGISTER

C ,

DQP

BYTE

WRITE REGISTER

D ,

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE DRIVER

B ,

DQP

BYTE

WRITE DRIVER

C ,

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

0, A1, A ADDRESS

ADV

CLK BURST

COUNTER AND

LOGIC

CLR

ADSC

BWB

BWA

CE1

DQB,DQPB

WRITE REGISTER

DQA,DQPA

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQA,DQPA

WRITE DRIVER

OUTPUT

BUFFERS

DQB,DQPB

WRITE DRIVER

A[1:0]

ZZ SLEEP

CONTROL

Logic Block Diagram – CY7C1382D (1 M x 18)

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 3 of 29

Pin Configurations

NC / 72M

NC / 36M

DQP

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

DQc

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1380D

(512K X 36)

NC / 72M

NC / 36M

DDQ

SSQ

DQP

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DQP

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1382D

(1 Mbit x 18)

100-pin TQFP Pinout

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 4 of 29

Pin Configurations (continued)

2345671

VDDQ

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS

NC / 36MNC / 72M

VDDQ

AAA

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

2345671

VDDQ

NCDQB

DQB

AA AA

ADSP VDDQ

VDDQ

NC / 72M

VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS

VDDQ

A NC / 36M A

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPB

DQPA

BWB

NC VDD NC

BWA

BWE

CY7C1382D (512K x 18)

CY7C1380D (512K x 36)

119-ball BGA (1 Chip Enable with JTAG)

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 5 of 29

Pin Configurations (continued)

165-ball fBGA

CY7C1380D (512K x 36)

234 5671

TDO

NC / 288M

DQP

CE3

BWE

ACE2

MODE

NC / 36M

NC / 72M

DDQ

CLK GW

DDQ

TCK

TDI

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

DQP

DDQ

CY7C1382D (1M x 18)

234 5671

TDO

NC / 288M

DQP

ACE

BWE

ACE2

MODE

NC / 36M

NC / 72M

DDQ

NC BW

CLK GW

DDQ

TCKA0

TDI

NC V

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

NCV

DDQ

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 6 of 29

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active.

A1: A0 are fed to the two-bit counter..

BWA,BWB

BWC,BWD

Input-

Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).

BWE Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

be asserted LOW to conduct a byte write.

CLK Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

the burst counter when ADV is asserted LOW, during a burst operation.

CE1

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.

CE2[2] Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3 to select/deselect the device.

CE3[2] Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select/deselect the device.Not available for AJ package version.Not connected

for BGA. Where referenced, CE3 is assumed active throughout this document for BGA.

OE Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

ADV Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,

it automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1:

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only

ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1:

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only

ADSP is recognized.

ZZ Input-

Asynchronous

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW

or left floating. ZZ pin has an internal pull-down.

DQs, DQPXI/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as

outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

VSSQ I/O Ground Ground for the I/O circuitry.

VDDQ I/O Power Supply Power supply for the I/O circuitry.

MODE Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation. Mode Pin has an internal pull-up.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP

packages.

TDI JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available

on TQFP packages.

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 7 of 29

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (tCO) is 2.6 ns

(250-MHz device).

The CY7C1380D/CY7C1382D supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE1, CE2, CE3 are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always tri-stated during the first cycle of the access. After the

first cycle of the access, the outputs are controlled by the OE

signal. Consecutive single Read cycles are supported. Once

the SRAM is deselected at clock rise by the chip select and

either ADSP or ADSC signals, its output will tri-state immedi-

ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3 are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BWX) and

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BWX

signals. The CY7C1380D/CY7C1382D provides Byte Write

capability that is described in the Write Cycle Descriptions

table. Asserting the Byte Write Enable input (BWE) with the

selected Byte Write (BWX) input, will selectively write to only

the desired bytes. Bytes not selected during a Byte Write

operation will remain unaltered. A synchronous self-timed

Write mechanism has been provided to simplify the Write

operations.

Because the CY7C1380D/CY7C1382D is a common I/O

device, the Output Enable (OE) must be deserted HIGH before

presenting data to the DQs inputs. Doing so will tri-state the

output drivers. As a safety precaution, DQs are automatically

tri-stated whenever a Write cycle is detected, regardless of the

state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and

(4) the appropriate combination of the Write inputs (GW, BWE,

and BWX) are asserted active to conduct a Write to the desired

byte(s). ADSC-triggered Write accesses require a single clock

cycle to complete. The address presented to A is loaded into

the address register and the address advancement logic while

being delivered to the memory array. The ADV input is ignored

during this cycle. If a global Write is conducted, the data

presented to the DQs is written into the corresponding address

location in the memory core. If a Byte Write is conducted, only

the selected bytes are written. Bytes not selected during a

Byte Write operation will remain unaltered. A synchronous

self-timed Write mechanism has been provided to simplify the

Write operations.

Because the CY7C1380D/CY7C1382D is a common I/O

device, the Output Enable (OE) must be deserted HIGH before

presenting data to the DQs inputs. Doing so will tri-state the

output drivers. As a safety precaution, DQs are automatically

tri-stated whenever a Write cycle is detected, regardless of the

state of OE.

TMS JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available

on TQFP packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be

connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die

Pin Definitions (continued)

Name I/O Description

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 8 of 29

Burst Sequences

The CY7C1380D/CY7C1382D provides a two-bit wraparound

counter, fed by A1: A0, that implements either an interleaved

or linear burst sequence. The interleaved burst sequence is

designed specifically to support Intel Pentium applications.

The linear burst sequence is designed to support processors

that follow a linear burst sequence. The burst sequence is user

selectable through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported. Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 80 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

Truth Table [ 3, 4, 5, 6, 7, 8]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

READ Cycle, Begin Burst External L H L L L X X X L L-H Q

READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

WRITE Cycle, Begin Burst External L H L L H L X L X L-H D

READ Cycle, Begin Burst External L H L L H L X H L L-H Q

READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Notes:

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.

5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2.

7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

don't care for the remainder of the write cycle.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

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CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 9 of 29

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Truth Table for Read/Write[5,9]

Function (CY7C1380D) GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HLHHHH

Write Byte A – (DQA and DQPA) HLHHHL

Write Byte B – (DQB and DQPB)HLHHLH

Write Bytes B, A H L H H L L

Write Byte C – (DQC and DQPC) HLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQD and DQPD) HL LHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Truth Table for Read/Write[5,9]

Function (CY7C1382D) GW BWE BWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA)HLHL

Write Byte B – (DQB and DQPB)HLLH

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

Truth Table (continued)[ 3, 4, 5, 6, 7, 8]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 10 of 29

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1380D/CY7C1382D incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. . The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1380D/CY7C1382D contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to VDD through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TEST-LOGIC

RESET

RUN-TEST/

IDLE SELECT

DR-SCAN SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

Bypass Register

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

Selection

Circuitry

TCK

MS TAP CONTROLLER

TDI TD

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CY7C1382D

Document #: 38-05543 Rev. *A Page 11 of 29

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the I/O

ring when these instructions are executed.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in this SRAM TAP controller,

and therefore this device is not compliant with 1149.1. The

TAP controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between

the two instructions. Unlike the SAMPLE/PRELOAD

instruction, EXTEST places the SRAM outputs in a High-Z

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

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PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required - that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

TAP AC Switching Characteristics Over the Operating Range[10, 11]

Parameter Description Min. Max. Unit

Clock

tTCYC TCK Clock Cycle Time 50 ns

tTF TCK Clock Frequency 20 MHz

tTH TCK Clock HIGH time 25 ns

tTL TCK Clock LOW time 25 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 5 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

Set-up Times

tTMSS TMS Set-up to TCK Clock Rise 5 ns

tTDIS TDI Set-up to TCK Clock Rise 5 ns

tCS Capture Set-up to TCK Rise 5

Hold Times

tTMSH TMS hold after TCK Clock Rise 5 ns

tTDIH TDI Hold after Clock Rise 5 ns

tCH Capture Hold after Clock Rise 5 ns

Notes:

10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns.

tTL

Test Clock

(TCK)

123456

est Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

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3.3V TAP AC Test Conditions

Input pulse levels ................................................ VSS to 3.3V

Input rise and fall times..................... ..............................1 ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse levels ......................................... VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels................... ......................1.25V

Output reference levels .................. ..............................1.25V

Test load termination supply voltage .................... ........1.25V

2.5V TAP AC Output Load Equivalent

1.5V

20p

Z = 50Ω

50Ω

1.25V

20p

Z = 50Ω

50Ω

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[12]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = –4.0 mA, VDDQ = 3.3V 2.4 V

IOH = –1.0 mA, VDDQ = 2.5V 2.0 V

VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V

VDDQ = 2.5V 2.1 V

VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V

VDDQ = 2.5V 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 V

VDDQ = 2.5V 0.2 V

VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3 V

VDDQ = 2.5V 1.7 VDD + 0.3 V

VIL Input LOW Voltage VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current GND < VIN < VDDQ –5 5 µA

Identification Register Definitions

Instruction Field

CY7C1380D

(512K x 36)

CY7C1382D

(1 Mbit x 18) Description

Revision Number (31:29) 000 000 Describes the version number.

Device Depth (28:24)[13] 01011 01011 Reserved for Internal Use

Device Width (23:18) 000000 000000 Defines memory type and architecture

Cypress Device ID (17:12) 100101 010101 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence Indicator (0) 11

Indicates the presence of an ID register.

Notes:

12. All voltages referenced to VSS (GND).

13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.

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Scan Register Sizes

Instruction 33

Bypass 11

ID 32 32

Boundary Scan Order

(119-ball BGA package)

85 85

Boundary Scan Order

(165-ball fBGA package)

89 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.

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119-Ball BGA Boundary Scan Order [14, 15]

CY7C1380D (256K x 36) CY7C1382D (512K x 18)

Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID

1H4 44 E4 1 H4 44 E4

2T445 G4 2 T4 45 G4

3T546 A4 3 T5 46 A4

4T647 G3 4 T6 47 G3

5 R5 48 C3 5 R5 48 C3

6 L5 49 B2 6 L5 49 B2

7R650 B3 7 R6 50 B3

8U651 A3 8 U6 51 A3

9 R7 52 C2 9 R7 52 C2

10 T7 53 A2 10 T7 53 A2

11 P6 54 B1 11 P6 54 B1

12 N7 55 C1 12 N7 55 C1

13 M6 56 D2 13 M6 56 D2

14 L7 57 E1 14 L7 57 E1

15 K6 58 F2 15 K6 58 F2

16 P7 59 G1 16 P7 59 G1

17 N6 60 H2 17 N6 60 H2

18 L6 61 D1 18 L6 61 D1

19 K7 62 E2 19 K7 62 E2

20 J5 63 G2 20 J5 63 G2

21 H6 64 H1 21 H6 64 H1

22 G7 65 J3 22 G7 65 J3

23 F6 66 K2 23 F6 66 K2

24 E7 67 L1 24 E7 67 L1

25 D7 68 M2 25 D7 68 M2

26 H7 69 N1 26 H7 69 N1

27 G6 70 P1 27 G6 70 P1

28 E6 71 K1 28 E6 71 K1

29 D6 72 L2 29 D6 72 L2

30 C7 73 N2 30 C7 73 N2

31 B7 74 P2 31 B7 74 P2

32 C6 75 R3 32 C6 75 R3

33 A6 76 T1 33 A6 76 T1

34 C5 77 R1 34 C5 77 R1

35 B5 78 T2 35 B5 78 T2

36 G5 79 L3 36 G5 79 L3

37 B6 80 R2 37 B6 80 R2

38 D4 81 T3 38 D4 81 T3

39 B4 82 L4 39 B4 82 L4

40 F4 83 N4 40 F4 83 N4

41 M4 84 P4 41 M4 84 P4

42 A5 85 Internal 42 A5 85 Internal

43 K4 43 K4

Notes:

14. Balls that are NC (No Connect) are preset LOW.

15. Bit# 85 is preset HIGH.

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165-Ball BGA Boundary Scan Order [14, 16]

CY7C1380D (256K x 36) CY7C1380D (256K x 36)

Bit# Ball ID Bit# Ball ID Bit# Ball ID

1N637 A9 73 K2

2N738 B9 74 L2

310N39 C10 75 M2

4P1140 A8 76 N1

5P841 B8 77 N2

6R842 A7 78 P1

7R943 B7 79 R1

8P944 B6 80 R2

9 P10 45 A6 81 P3

10 R10 46 B5 82 R3

11 R11 47 A5 83 P2

12 H11 48 A4 84 R4

13 N11 49 B4 85 P4

14 M11 50 B3 86 N5

15 L11 51 A3 87 P6

16 K11 52 A2 88 R6

17 J11 53 B2 89 Internal

18 M10 54 C2

19 L10 55 B1

20 K10 56 A1

21 J10 57 C1

22 H9 58 D1

23 H10 59 E1

24 G11 60 F1

25 F11 61 G1

26 E11 62 D2

27 D11 63 E2

28 G10 64 F2

29 F10 65 G2

30 E10 66 H1

31 D10 67 H3

32 C11 68 J1

33 A11 69 K1

34 B11 70 L1

35 A10 71 M1

36 B10 72 J2

Note:

16. Bit# 89 is preset HIGH.

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Document #: 38-05543 Rev. *A Page 17 of 29

165-Ball BGA Boundary Scan Order [14, 16]

CY7C1382D (512K x 18) CY7C1382D (512Kx18)

Bit# Ball ID Bit# Ball ID Bit# Ball ID

1N637 A9 73 K2

2N738 B9 74 L2

3 10N 39 C10 75 M2

4P1140 A8 76 N1

5P841 B8 77 N2

6R842 A7 78 P1

7R943 B7 79 R1

8P944 B6 80 R2

9 P10 45 A6 81 P3

10 R10 46 B5 82 R3

11 R11 47 A5 83 P2

12 H11 48 A4 84 R4

13 N11 49 B4 85 P4

14 M11 50 B3 86 N5

15 L11 51 A3 87 P6

16 K11 52 A2 88 R6

17 J11 53 B2 89 Internal

18 M10 54 C2

19 L10 55 B1

20 K10 56 A1

21 J10 57 C1

22 H9 58 D1

23 H10 59 E1

24 G11 60 F1

25 F11 61 G1

26 E11 62 D2

27 D11 63 E2

28 G10 64 F2

29 F10 65 G2

30 E10 66 H1

31 D10 67 H3

32 C11 68 J1

33 A11 69 K1

34 B11 70 L1

35 A10 71 M1

36 B10 72 J2

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Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to VDDQ + 0.5V

DC Input Voltage....................................–0.5V to VDD + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range [17, 18]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage VDDQ = 3.3V 3.135 VDD V

VDDQ = 2.5V 2.375 2.625 V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[17] VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[17] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current

except ZZ and MODE

GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –5 µA

Input = VDD 30 µA

Input Current of ZZ Input = VSS –30 µA

Input = VDD 5µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply

Current

VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4.0-ns cycle, 250 MHz 350 mA

5.0-ns cycle, 200 MHz 300 mA

6.0-ns cycle, 167 MHz 275 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

4.0-ns cycle, 250 MHz 160 mA

5.0-ns cycle, 200 MHz 150 mA

6.0-ns cycle, 167 MHz 140 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f= 0

All speeds 70 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

4.0-ns cycle, 250 MHz 135 mA

5.0-ns cycle, 200 MHz 130 mA

6.0-ns cycle, 167 MHz 125 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All speeds 80 mA

Shaded areas contain advance information.

Notes:

17. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).

18. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.

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Thermal Resistance[19]

Parameter Description Test Conditions

TQFP

Package

BGA

Package

fBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

impedance, per EIA / JESD51.

31 45 46 °C/W

ΘJC Thermal Resistance

(Junction to Case)

673°C/W

Capacitance[19]

Parameter Description Test Conditions

TQFP

Package

BGA

Package

fBGA

Package Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 2.5V

589pF

CCLK Clock Input Capacitance 5 8 9 pF

CI/O Input/Output Capacitance 5 8 9 pF

AC Test Loads and Waveforms

Notes:

19. Tested initially and after any design or process change that may affect these parameters

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

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Switching Characteristics Over the Operating Range[24, 25]

Parameter Description

250 MHz 200 MHz 167 MHz

UnitMin. Max Min. Max

tPOWER VDD(Typical) to the first Access[20] 111 ms

Clock

tCYC Clock Cycle Time 4.0 56 ns

tCH Clock HIGH 1.7 2.0 2.2 ns

tCL Clock LOW 1.7 2.0 2.2 ns

Output Times

tCO Data Output Valid After CLK Rise 2.6 3.0 3.4 ns

tDOH Data Output Hold After CLK Rise 1.0 1.3 1.3 ns

tCLZ Clock to Low-Z[21, 22, 23] 1.0 1.3 1.3 ns

tCHZ Clock to High-Z[21, 22, 23] 2.6 3.0 3.4 ns

tOEV OE LOW to Output Valid 2.6 3.0 3.4 ns

tOELZ OE LOW to Output Low-Z[21, 22, 23] 000 ns

tOEHZ OE HIGH to Output High-Z[21, 22, 23] 2.6 3.0 3.4 ns

Setup Times

tAS Address Set-up Before CLK Rise 1.2 1.4 1.5 ns

tADS ADSC, ADSP Set-up Before CLK Rise 1.2 1.4 1.5 ns

tADVS ADV Set-up Before CLK Rise 1.2 1.4 1.5 ns

tWES GW, BWE, BWX Set-up Before CLK Rise 1.2 1.4 1.5 ns

tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns

tCES Chip Enable Set-Up Before CLK Rise 1.2 1.4 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.3 0.4 0.5 ns

tADH ADSP , ADSC Hold After CLK Rise 0.3 0.4 0.5 ns

tADVH ADV Hold After CLK Rise 0.3 0.4 0.5 ns

tWEH GW,BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns

tDH Data Input Hold After CLK Rise 0.3 0.4 0.5 ns

tCEH Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns

Shaded areas contain advance information.

Notes:

20. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

can be initiated.

21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions

23. This parameter is sampled and not 100% tested.

24. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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CY7C1382D

Document #: 38-05543 Rev. *A Page 21 of 29

Switching Waveforms

Read Cycle Timing[26]

Notes:

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

BWx

ata Out (Q) High-Z

tCLZ tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 22 of 29

Write Cycle Timing[26, 27]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 23 of 29

Read/Write Cycle Timing[26, 28, 29]

Notes:

28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

29. GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 24 of 29

Switching Waveforms (continued)

Z Mode Timing

[30

31]

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Part and Package Type

Operating

Range

250 CY7C1380D-250AXC

CY7C1382D-250AXC

A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1380D-250BGC

CY7C1382D-250BGC

BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1380D-250BZC

CY7C1382D-250BZC

BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1380D-250BGXC

CY7C1382D-250BGXC

BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1380D-250BZXC

CY7C1382D-250BZXC

BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

200 CY7C1380D-200AXC

CY7C1382D-200AXC

A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

CY7C1380D-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382D-200BGC

CY7C1380D-200BZC BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-200BZC

CY7C1380D-200BGXC BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382D-200BGXC

CY7C1380D-200BZXC BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-200BZXC

167 CY7C1380D-167AXC

CY7C1382D-167AXC

A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm)

CY7C1380D-167BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382D-167BGC

CY7C1380D-167BZC

CY7C1382D-167BZC

BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 25 of 29

CY7C1380D-167BGXC BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382D-167BGXC

CY7C1380D-167BZXC

CY7C1382D-167BZXC

BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

167 CY7C1380D-167AXI

CY7C1382D-167AXI

A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1380D-167BGI

CY7C1382D-167BGI

BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1380D-167BZI BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZI

CY7C1380D-167BGXI

CY7C1382D-167BGXI

BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1380D-167BZXI BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZXI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Lead-free BG packages (Ordering Code:

BGX) will be available in 2005.

Notes:

30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

31. DQs are in high-Z when exiting ZZ sleep mode.

Ordering Information (continued)

Speed

(MHz) Ordering Code

Package

Name Part and Package Type

Operating

Range

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 26 of 29

Package Diagrams

DIMENSIONS ARE IN MILLIMETERS.

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R0.08MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL A

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 27 of 29

Package Diagrams (continued)

51-85115-*B

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 28 of 29

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM

Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

51-85180-**

165 FBGA 13 x 15 x 1.40 MM BB165D

PRELIMINARY

CY7C1380D

CY7C1382D

Document #: 38-05543 Rev. *A Page 29 of 29

Document History Page

Document Title: CY7C1380D/CY7C1382D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Document Number: 38-05543

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 254515 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

non-compliance with 1149.1

Removed 225Mhz and 133Mhz Speed Bins

Added lead-free information for 100-Pin TQFP , 119 BGA and 165 FBGA Packages

Added comment of ‘Lead-free BG packages availability’ below the Ordering Infor-

mation